KR20100034878A - Non-volatile memory device - Google Patents

Abstract

PURPOSE: A non-volatile memory device is provided to reduce the number of pass transistors connected to each word line by sharing a word line between adjacent blocks. CONSTITUTION: A first and a second memory regions have a plurality of strings, respectively. Each string comprises a string selection transistor, a ground selection transistor, and a memory cells. A string selection transistor(SST) is connected to the string selection line. The ground selection transistor(GST) is connected to the ground selection line. A memory cell(M0~M31) is respectively connected to corresponding word lines. Word lines and a ground selection line forms a closed circuit.

Description

Non-volatile memory device

The present invention relates to a nonvolatile memory device, and more particularly, to a NAND type nonvolatile memory device having improved integration.

Generally, a nonvolatile memory device is an element capable of electrically erasing and storing data and preserving data even when a power supply is cut off. Accordingly, the use of nonvolatile memory devices has recently increased in various fields.

These nonvolatile memory devices form various types of memory cell transistors, and are classified into NAND type and NOR type according to a cell array structure. NAND type nonvolatile memory cell transistors and NOR type nonvolatile memory cell transistors have advantages and disadvantages, which are classified into high integration and high speed.

In particular, NAND type nonvolatile memory devices are advantageous for high integration due to a cell string structure in which a plurality of memory cell transistors are connected in series. In addition, since the NAND type nonvolatile memory device adopts an operation method of simultaneously changing the information stored in the plurality of memory cell transistors, the information update rate is much faster than that of the NOR type nonvolatile memory device. Due to this high density and fast update rate, NAND type nonvolatile memory devices are mainly used in portable electronic products requiring mass storage such as digital cameras or MP3 players.

An object of the present invention is to provide a nonvolatile memory device with improved integration.

The problem to be solved by the present invention is not limited to the above-mentioned problem, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a nonvolatile memory device according to an embodiment of the present invention includes first and second memory regions each having a plurality of strings, each string comprising a string select transistor connected to a bit line, A ground select transistor connected to the common source line, and memory cells connected in series between the string and ground select transistors, the string select transistor connected to the string select line, the ground select transistor connected to the ground select line, and the memory cell Are connected to corresponding word lines, respectively, and in the first and second memory areas, word lines corresponding to each other and ground select lines form a closed circuit.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the nonvolatile memory device of the present invention, by sharing word lines between adjacent blocks, the number of pass transistors connected to the respective word lines can be reduced. Therefore, the degree of integration of the nonvolatile memory device can be improved.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, the words "comprises" and / or "comprising" refer to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Hereinafter, a reference voltage generator circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a NAND type nonvolatile memory device includes a memory cell array 10, a row decoder 20, a page buffer 30, and a column decoder 40.

The memory cell array 10 may include a plurality of memory blocks BLK0 to BLKn, and the memory blocks BLK0 to BLKn may include a plurality of word lines, bit lines, and memory cells to store data. have. The memory blocks BLK0 to BLKn will be described in detail with reference to FIGS. 2 and 3.

The row decoder 20 selects memory blocks BLK0 to BLKn of the memory cell array and selects word lines of the selected memory block according to the address information.

The page buffer 30 may temporarily store data to be stored in the memory cells or sense data stored in the memory cells according to an operation mode. The page buffer 30 may operate as a write driver circuit in a program operation mode and may operate as a sense amplifier circuit in a read operation mode. Although not shown in the drawing, the page buffer 30 may include page buffers respectively connected to bit lines or connected to bit line pairs, respectively.

The column decoder 40 may provide a data transfer path between the page buffer circuit 110 and an external device (eg, a memory controller).

2 is a circuit diagram illustrating a portion of a nonvolatile memory device according to an embodiment of the present invention. 2 illustrates two memory blocks BLK0 and BLK1.

Referring to FIG. 2, each of the memory blocks BLK0 and BLK1 includes bit lines BL0, BL1,..., And a common source line CSL, and each of the bit lines BL0, BL1,... A plurality of strings 11 are included between the lines CSL. Each string 11 includes a string select transistor SST and a ground select transistor GST, and a plurality of memory cell transistors M0 to M31 between the string select transistor SST and the ground select transistor GST. ) Are connected in series. Although 32 memory cell transistors M0 to M31 are illustrated in the figure, the number of memory cell transistors may vary. The drain of the string select transistor SST is connected to the bit lines BL0, BL1,..., And the source of the ground select transistor GST is connected to the common source line CSL.

The string select transistors SST included in each of the memory blocks BLK0 and BLK1 are connected to the string select lines SSL0 and SSL1, respectively, and the ground select transistors GST are common to the ground select line GSL. Connected. In addition, the memory cell transistors M0 to M31 are connected to corresponding word lines WL0 to WL31, respectively.

The string select lines SSL0 and SSL1, the word lines WL0 to WL31, and the ground select line GSL of the memory blocks BLK0 and BLK1 are connected to the row decoder 20. The bit lines BL0, BL1,... Are connected to the page buffer 30 of FIG. 1.

The first and second memory blocks BLK0 and BLK1 adjacent to each other are mirror symmetric with respect to the common source line CSL, and the mirror symmetric strings 11 are formed in the bit lines BL0, BL1, …) Can be shared.

In the first and second memory blocks BLK0 and BLK1 adjacent to each other, word lines WL0 to WL31 corresponding to each other are electrically connected to each other. That is, the first and second memory blocks BLK0 and BLK1 share corresponding word lines WL0 to WL31.

In detail, the word lines WL0 to WL31 commonly connected to the first and second memory blocks BLK0 and BLK1 may form a closed circuit structure. For example, the first memory cell transistors M0 of the first memory block BLK0 and the first memory cell transistors M0 of the second memory block BLK1 may be connected to the first word line WL0. Commonly connected.

In addition, adjacent first and second memory blocks BLK0 and BLK1 may also share ground select lines GSL0 and GSL1. That is, the ground select lines GSL0 and GSL1 may form a closed circuit structure over the first and second memory blocks BLK0 and BLK1.

In the nonvolatile memory device according to an embodiment of the present invention, a layout showing an arrangement structure of the string select lines SSL, the word lines WL0 to WL31 and the ground select lines GSL0 and GSL1 is illustrated in FIG. 3. It is. In FIG. 3, the first and second memory regions MR1 and MR2 may correspond to the first and second memory blocks BLK0 and BLK1 of FIG. 2, respectively.

In detail, as shown in FIG. 3, a nonvolatile memory device according to an exemplary embodiment of the present invention includes first and second memory regions MR1 and MR2.

Over the adjacent first and second memory regions MR1 and MR2, the word lines WL0 to WL31 and the ground select line GSL each form a closed circuit (or a closed curve). Such a closed circuit structure may be formed using a double patterning technology (DPT).

Briefly, a first mask pattern in the form of a line is formed on the stacked gate conductive films, and a second mask pattern in the form of a spacer is formed around the first mask pattern. Here, the first and second mask patterns are formed of a material having an etching selectivity. Thereafter, the stacked gate conductive layers may be etched using the second mask pattern to form word lines WL0 to WL31 and a string select line SSL of a closed circuit structure.

That is, each of the ground select line GSL and the word lines WL0 to WL31 may have a quadrangular shape over the first and second memory regions MR1 and MR2. In other words, each of the ground select line GSL and the word lines WL0 to WL31 may be disposed in the first and second memory regions MR1 and MR2, respectively, and be parallel to each other. Second lines connecting both ends. Therefore, the second lines cross the first and second memory regions MR1 and MR2.

In addition, the line width of each of the ground select line GSL and the word lines WL0 to WL31 may be the ground select line GSL and the word lines disposed in the same region (the first or second memory regions MR1 and MR2). It is smaller than the interval between (WL0 to WL31).

The common source line CSL is positioned in the closed selection ground selection line GSL. That is, the common source line CSL is formed in common across the first and second memory regions MR1 and MR2 and may be surrounded by the ground select line GSL. The common source line CSL may be an impurity region formed by doping impurities.

As such, the ground selection line GSL and the word lines WL0 to WL31 forming a closed curve over the first and second memory regions MR1 and MR2 have a separation distance from the common source line CSL. It is arranged gradually.

In addition, string select lines SSL0 and SSL1 are positioned in each of the first and second memory regions MR1 and MR2. Unlike the word lines WL0 to WL31 and the ground select line GSL, the string select lines SSL0 and SSL1 may be formed by performing a separate patterning process. The string select lines SSL0 and SSL1 are disposed in parallel with the long axis direction of the closed line word lines WL0 to WL31.

Referring back to FIG. 2, the ground select line GSL and the word lines WL0 to WL31 connected to the adjacent first and second memory blocks BLK0 and BLK1 in common, and the first and second memory blocks. Each of the string select lines SSL0 and SSL1 is connected to the pass (or transfer) transistors SP0, SP1, GP, PT0 to PT31 of the row decoder 20.

The pass transistors SP0, SP1, GP and PT0 to PT31 are controlled by the pass control signal PS, and the signal lines SSL0 and SSL1 corresponding to the selection signals SS1, SS2, GS, and S0 to S31. , GSL, WL0 ~ WL31). The selection signals SS1, SS2, GS and S0 to S31 are signals decoded according to the address signal, and the memory blocks BLK0 and BLK1 and the word line are decoded according to the selection signals SS1, SS2, GS and S0 to S31. WL0 to WL31 can be selected.

In an embodiment of the present invention, since the adjacent memory blocks BLK0 and BLK1 share the word lines WL0 to WL31 and the ground select line GSL corresponding to each other, the word lines included in the memory cell array. The number of pass transistors SP0, SP1, GP, PT0 through PT31 respectively connected to WL0 through WL31 may be reduced.

Hereinafter, the operation of the nonvolatile memory device sharing the word lines WL0 to WL31 and the ground select line SSL between adjacent memory blocks BLK0 and BLK1 will be described. In one embodiment of the present invention, the string select signals SS1 and SS2 are used as ground select and memory block select signals.

During the program operation, the pass control signal PS is activated to turn on the pass transistors SP0, SP1, GP, PT0 to PT31. Accordingly, the power supply voltage Vcc may be provided to the string select line SSL0 or SSL1 of the selected memory block, and the ground voltage 0V may be provided to the string select line SSL0 or SSL1 of the non-selected memory block. That is, voltage levels opposite to each other are applied to the first and second string select lines SSL0 and SSL1. The program voltage Vpgm is provided to one selected word line among the word lines WL0 to WL31, and a pass voltage Vpass is provided to the remaining word lines. In addition, the ground select line GSL is provided with a ground voltage 0V. Accordingly, data is stored in memory cells connected to the selected memory block and the selected word line.

In the erase operation, the ground voltage 0V is provided to the word lines WL0 to WL31 through the pass transistors PT0 to PT31, and the erase voltage Verase is applied to the semiconductor substrate of the memory cell transistor. do. The string select lines SSL0 and SSL1, the ground select line GSL, and the common source line CSL are floated.

As such, when voltages are provided to the signal lines of the memory cell array, the word lines WL0 to WL31 are shared between the adjacent memory blocks BLK0 and BLK1, and thus the memory in the adjacent blocks BLK0 and BLK1 is shared. The cells are erased at the same time. That is, the erase operation may be performed in at least two memory blocks in the nonvolatile memory device according to an embodiment of the present invention.

4 is a schematic diagram of a memory system including a nonvolatile memory device according to example embodiments.

Referring to FIG. 4, the memory system 1100 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, It can be applied to a memory card or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes a controller 1110, an input / output device 1120 such as a keypad, a keyboard, and a display, a memory 1130, an interface 1140, and a bus 1150. The memory 1130 and the interface 1140 communicate with each other via the bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or similar other processing devices. Memory 1130 may be used to store instructions performed by the controller. The input / output device 1120 may receive data or a signal from the outside of the system 1100 or output data or a signal to the outside of the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display element.

The memory 1130 includes a nonvolatile memory device according to embodiments of the present invention. The memory 1130 may also further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The interface 1140 transmits data to the communication network or receives data from the network.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a block diagram of a nonvolatile memory device according to an embodiment of the present invention.

2 is a circuit diagram illustrating a portion of a nonvolatile memory device according to an embodiment of the present invention.

3 is a plan view illustrating a portion of a nonvolatile memory device according to an embodiment of the present invention.

4 is a schematic diagram of a memory system having a nonvolatile memory device according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

10: memory cell array 20: row decoder

30: page buffer 40: column decoder

Claims (7)

First and second memory regions each having a plurality of strings, Each string includes a string select transistor connected to a bit line, a ground select transistor connected to a common source line, and memory cells connected in series between the string and the ground select transistors, The string select transistor is connected to a string select line, the ground select transistor is connected to a ground select line, the memory cells are respectively connected to corresponding word lines, The word lines and the ground select line corresponding to each other in the first and second memory regions form a closed circuit. The method of claim 1, And the word lines and the ground select line each form a closed curve over the first and second memory regions. The method of claim 2, The common source line is commonly located in the first memory area and the second memory area, and the ground select line is adjacent to the common source line to surround the common source line. The method of claim 3, wherein And the word lines forming the closed curve are arranged with increasing distance from the common source line. The method of claim 2, Each of the ground select line and the word line, First lines positioned in the first and second memory regions and parallel to each other, and second lines formed over the first and second memory regions and connecting both ends of the first lines. Nonvolatile Memory Device. The method of claim 5, The line width of the first lines is less than the distance between the first lines located in the first or second memory area. The method of claim 1, And the string select lines are located in respective first and second memory regions.

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