KR20120091687A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device is provided to prevent the degradation of reliability due to the reduction of read margin by providing driving signals with a constant rising slope to a memory cell array. CONSTITUTION: A memory cell array(110) includes a plurality of memory cells laminated in an orthogonal direction to a substrate. A row selection circuit(130) is connected to a memory cell array with word lines. A voltage generating circuit(120) generates voltages provided to word lines. The voltage generating circuit generates voltages which gradually increase to a target voltage level.

Description

Nonvolatile Memory Device {NONVOLATILE MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device.

A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge, Germanium), gallium arsenide (GaAs, gallium arsenide), or indium phospide (InP). to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory devices are largely divided into NOR type and NAND type.

Recently, a semiconductor memory device having a three-dimensional array structure has been studied to improve the integration degree of the semiconductor memory device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device for providing drive signals having a constant rising slope to a memory cell array and a memory system including the same.

In an embodiment, a nonvolatile memory device may include a memory cell array including a plurality of memory cells stacked in a direction orthogonal to a substrate; A row select circuit coupled to the memory cell array through word lines; And a voltage generator circuit for generating voltages to be provided to the word lines, wherein the voltage generator circuit generates the voltages in a stepwise increment up to a target voltage level.

In an embodiment, the voltage generation circuit generates a voltage signal that gradually increases to a pass voltage level during a program operation.

In example embodiments, the voltage generator circuit may include: a first voltage generator configured to generate a first voltage signal gradually increasing to a program voltage level; And a second voltage generator for generating a second voltage signal that gradually increases to a pass voltage level.

In an embodiment, the row selection circuit provides the second voltage signal as driving signals to unselected word lines among the word lines, and the driving signals provided to the unselected word lines have the same rising slope. .

In an embodiment, the voltage generation circuit generates a voltage signal that gradually increases to an unselected read voltage level during a read operation.

In example embodiments, the voltage generation circuit may include: a first voltage generator configured to generate a first voltage signal that is incrementally increased to a select read voltage level; And a second voltage generator for generating a second voltage signal that increases stepwise to an unselected read voltage level.

In an embodiment, the row selection circuit provides the second voltage signal as driving signals to unselected word lines among the word lines, and the driving signals provided to the unselected word lines have the same rising slope. .

In example embodiments, the voltage generator circuit may include: a first voltage generator configured to generate a first voltage signal gradually increasing to a program voltage level; A second voltage generator for generating a second voltage signal that gradually increases to a pass voltage level; A third voltage generator for generating a third voltage signal that is incrementally increased to a select read voltage level; And a fourth voltage generator for generating a fourth voltage signal that increases stepwise to an unselected read voltage level.

In example embodiments, the apparatus may further include ramping logic configured to control the voltage generation circuit to have different ramping steps according to target voltage levels of the voltages.

In an embodiment, memory cells on a plane parallel to the substrate share the same word line.

The nonvolatile memory device according to an embodiment of the present invention can provide driving signals having a constant rising slope to the memory cell array. Therefore, a decrease in reliability due to a decrease in read margin can be prevented.

1 is a block diagram illustrating a nonvolatile memory device in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a memory cell array of FIG. 1.
FIG. 3 is a perspective view illustrating a first embodiment of one of the memory blocks of FIG. 2.
4 is a cross-sectional view taken along line II ′ of the memory block of FIG. 3.
5 is a cross-sectional view illustrating the transistor structure of FIG. 4.
FIG. 6 is a circuit diagram illustrating an equivalent circuit in accordance with a first embodiment of a memory block described with reference to FIGS. 3 to 5.
7 is a diagram illustrating a rising slope of driving signals in a general case.
8 is a block diagram illustrating in detail the high voltage generation circuit and the ramping logic of FIG. 1.
FIG. 9 is a diagram illustrating a first voltage signal generated by the first voltage generator of FIG. 8.
FIG. 10 is a diagram illustrating a second voltage signal generated by the second voltage generator of FIG. 8.
FIG. 11 is a block diagram illustrating the row selection circuit of FIG. 1 in more detail.
FIG. 12 is a diagram for describing the driving block of FIG. 11 in more detail.
13 and 14 illustrate rising slopes of driving signals when voltage signals generated by the high voltage generation circuit of FIG. 1 are provided to word lines as driving signals.
15 is a block diagram illustrating a nonvolatile memory device according to another exemplary embodiment of the present invention.
16 to 18 are diagrams for explaining read disturbance caused by driving signals having different rising slops.
FIG. 19 is a block diagram illustrating an example embodiment of the high voltage generation circuit and the ramping logic of FIG. 1.
20 is a block diagram illustrating another embodiment of the high voltage generation circuit and the ramping logic of FIG. 1.
FIG. 21 is a circuit diagram illustrating an equivalent circuit BLKi_2 according to the second embodiment of the memory block BLKi described with reference to FIGS. 3 to 5.
FIG. 22 is a circuit diagram illustrating an equivalent circuit according to a third embodiment of the memory block described with reference to FIGS. 3 to 5.
FIG. 23 is a circuit diagram illustrating an equivalent circuit according to a fourth embodiment of the memory block described with reference to FIGS. 3 to 5.
FIG. 24 is a circuit diagram illustrating an equivalent circuit according to a fifth embodiment of the memory block described with reference to FIGS. 3 to 5.
FIG. 25 is a perspective view illustrating a second embodiment of one of the memory blocks of FIG. 2.
FIG. 26 is a perspective view illustrating a modified example of the memory block of FIG. 25.
FIG. 27 is a perspective view illustrating a third embodiment of one of the memory blocks of FIG. 3.
FIG. 28 is a cross-sectional view taken along line III-III ′ of the memory block of FIG. 27.
29 is a perspective view illustrating a modified example of the memory block of FIG. 27.
FIG. 30 is a cross-sectional view taken along line IV-IV 'of the memory block of FIG. 31.
FIG. 31 is a perspective view illustrating a fourth embodiment of one of the memory blocks of FIG. 3.
32 is a cross-sectional view taken along line VV ′ of the memory block of FIG. 31.
33 is a perspective view illustrating a modified example of the memory block of FIG. 31.
FIG. 34 is a cross-sectional view taken along line VI-VI ′ of the memory block of FIG. 33.
35 is a perspective view illustrating a fifth embodiment of one of the memory blocks of FIG. 2.
FIG. 36 is a cross-sectional view taken along a line 'VIII' of the memory block of FIG. 35.
FIG. 37 is a block diagram illustrating a memory system including the nonvolatile memory device of FIG. 1 or 14.
FIG. 38 is a block diagram illustrating an application example of the memory system of FIG. 37.
FIG. 39 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 38.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. . For convenience of description, like elements will be referred to using like reference numerals. Similar components will be referred to using similar reference numerals.

In a nonvolatile memory device including a memory block having a three-dimensional structure, rising slopes of driving signals provided to word lines may be different due to process factors. This difference in rising slop may cause a read fail due to a decrease in read margin. The nonvolatile memory device according to an embodiment of the present invention maintains the rising slope of the driving signals by using a ramping technique. Therefore, the reduction of the read margin can be minimized. Hereinafter, for convenience of description, embodiments of the present invention will be described based on the program operation. However, the technical idea of the present invention can be applied to read and erase operations.

1 is a block diagram illustrating a nonvolatile memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, a nonvolatile memory device 100 may include a memory cell array 110, a high voltage generation circuit 120, a row selection circuit 130, a read and write circuit 140, a data input / output circuit 150, Control logic 160, and ramping logic 170.

The memory cell array 110 is connected to the row select circuit 130 through word lines WL and to the read and write circuit 140 through bit lines BL. The memory cell array 110 includes memory blocks having a three-dimensional structure, and each memory block includes a plurality of memory cells. In exemplary embodiments, each memory block of the memory cell array 110 includes a plurality of memory cells capable of storing one or more bits per cell.

The high voltage generation circuit 120 generates the first voltage signal VS_1 and the second voltage signal VS_2 in response to the control of the ramping logic 170. Here, the first voltage signal VS_1 is a voltage signal whose target voltage is a program voltage Vpgm, and the second voltage signal VS_2 is a voltage signal whose target voltage is a pass voltage.

In the program operation, the high voltage generation circuit 120 increases the voltage level of the first voltage signal VS_1 to the program voltage Vpgm in a constant ramping step in response to the control of the ramping logic 170. Let's do it. The first voltage signal VS_1 is provided to the selected word line through the row select circuit 130. That is, the selected word line is provided with a first voltage signal VS_1 which gradually increases to the program voltage Vpgm.

Similarly, the high voltage generation circuit 120 increases the voltage level of the second voltage signal VS_2 to the pass voltage Vpass in a constant ramping step in response to the control of the ramping logic 170. The second voltage signal VS_2 is provided to the unselected word lines through the row select circuit 130.

The row select circuit 130 receives the first voltage signal VS_1 and the second voltage signal VS_2 from the high voltage generation circuit 120. In the program operation, the row selection circuit 130 provides the first voltage signal VS_1 to the selected word line and the second voltage signal VS_2 to the unselected word lines. The row select circuit 130 includes a word line driver 131 and a row decoder 133.

The word line driver 131 receives the first voltage signal VS_1 and the second voltage signal VS_2 from the high voltage generation circuit 120. The word line driver 131 provides the first voltage signal VS_1 or the second voltage signal VS_2 to each signal line SL in response to the address RAi of a part of the row address RA.

For example, in a program operation, the word line driver 131 provides the first voltage signal VS_1 as a driving signal DS to a signal line corresponding to the selected word line. The word line driver 131 provides the second voltage signal VS_2 as driving signals DS to signal lines corresponding to unselected word lines.

The row decoder 133 receives the driving signals DS from the word line driver 131. The row decoder 133 selects the word lines WL to which the driving signals DS are to be provided in response to the remaining address RAj among the row addresses RA.

For example, the address RAj provided to the row decoder 133 may be an address for selecting a memory block. In this case, the row decoder 133 selects a memory block in response to the address RAj and transfers driving signals DS to word lines of the selected memory block, respectively. Accordingly, the first voltage signal VS_1 is provided to the selected word line as the driving signal DS, and the second voltage signal VS_2 is provided to the unselected word lines as the driving signal DS, respectively.

The read and write circuit 140 is connected to the memory cell array 110 through the bit lines BL and to the data input / output circuit 150 through the data lines DL. The read and write circuit 140 receives data from the data input / output circuit 150 and writes the received data to the memory cell array 110. The read and write circuit 140 reads data from the memory cell array 110 and transfers the read data to the data input / output circuit 150. In exemplary embodiments, the read and write circuit 140 may include components such as a page buffer (or page register) that performs reading and writing of data, and a column selection circuit that selects bit lines BL.

The data input / output circuit 150 is connected to the read and write circuit 140 through the data lines DL. The data input / output circuit 150 operates under the control of the control logic 160. The data input / output circuit 150 is configured to exchange data DATA with an external device. The data input / output circuit 150 transfers the data DATA transmitted from the outside to the read and write circuit 140 through the data lines DL. The data input / output circuit 150 outputs the data DATA transferred from the read and write circuit 140 through the data lines DL to the outside. In exemplary embodiments, the data input / output circuit 150 may include a component such as a data buffer.

The control logic 160 controls overall operations of the nonvolatile memory device 100. The control logic 160 is configured to control the high voltage generation circuit 120, the row selection circuit 130, the read and write circuit 140, and the data input / output circuit 150. Referring to FIG. 1, the control logic 160 includes a ramping logic 170.

The ramping logic 170 controls the high voltage generation circuit 120 to generate the first and second voltage signals VS_1 and VS_2 that increase in stages. That is, during the program operation, the ramping logic 170 controls the high voltage generation circuit 120 to generate the first voltage signal VS_1 that increases stepwise to the program voltage Vpgm. In addition, the ramping logic 170 controls the high voltage generation circuit 120 to generate the second voltage signal VS_2 that increases stepwise to the pass voltage Vpass.

As described above, the nonvolatile memory device 100 generates the first and second voltage signals VS_1 and VS_2 that increase in steps (that is, in units of ramping steps) up to a target voltage. This is provided to the word lines as a driving signal DS.

Since the voltage levels of the first and second voltage signals VS_1 and VS_2 increase step by step in the ramping step, the driving signals provided to the word lines can maintain a constant rising slope regardless of the resistance difference of each word line. have. Accordingly, the nonvolatile memory device 100 can prevent a decrease in read margin due to a program speed difference. Hereinafter, the structure of the memory cell array 110 according to an embodiment of the present invention will be described in more detail.

2 is a block diagram illustrating the memory cell array 110 of FIG. 1. Referring to FIG. 2, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or a vertical structure). For example, each memory block BLK includes structures extending along first to third directions. For example, each memory block BLK may include a plurality of NAND strings NS that extend in the second direction. For example, a plurality of NAND strings NS may be provided along the first and third directions.

Each NAND string NS is connected to a bit line BL, a string select line SSL, a ground select line GSL, word lines WL, and a common source line CSL. That is, each memory block includes a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, and a common source line CSL. Will be connected to). The memory blocks BLK1 to BLKz are described in more detail with reference to FIG. 3.

In exemplary embodiments, the memory blocks BLK1 to BLKz are selected by the row select circuit 130 shown in FIG. 1. For example, the row select circuit 130 selects the memory block BLK corresponding to the decoded row address among the memory blocks BLK1 to BLKz.

3 is a perspective view illustrating a first embodiment of one of the memory blocks BLK1 to BLKz of FIG. 2. 4 is a cross-sectional view taken along line II ′ of the memory block BLKi of FIG. 3. 3 and 4, the memory block BLKi includes structures extending along the first to third directions.

First, the substrate 111 is provided. In exemplary embodiments, the substrate 111 may be a well having a first type. For example, the substrate 111 may be a p well formed by implanting a Group 5 element such as boron (B). For example, the substrate 111 may be a pocket p well provided in an n well. Hereinafter, it is assumed that the substrate 111 is a p well. However, the substrate 111 is not limited to being a p well.

On the substrate 111, a plurality of doped regions 311 ˜ 314 extending along the first direction are provided. For example, the plurality of doped regions 311 to 314 may have a second type different from that of the substrate 111. For example, the plurality of doped regions 311 ˜ 314 may have an n type. Hereinafter, it is assumed that the first to fourth doped regions 311 to 314 have an n type. However, the first to fourth doped regions 311 to 314 are not limited to those having an n type.

On the region of the substrate 111 between the first and second doped regions 311 and 312, a plurality of insulating materials 112 extending along the first direction are sequentially provided along the second direction. For example, the plurality of insulating materials 112 may be provided spaced apart by a certain distance along the second direction. Illustratively, the insulating materials 112 will comprise an insulating material such as silicon oxide.

On the region of the substrate 111 between the first and second doped regions 311 and 312, a plurality of pillars are disposed sequentially in the first direction and penetrate the insulating materials 112 along the second direction. Fields 113 are provided. In some embodiments, the pillars 113 may be connected to the substrate 111 through the insulating materials 112.

Illustratively, each pillar 113 will comprise a plurality of materials. For example, the surface layer 114 of each pillar 113 may comprise a silicon material having a first type. For example, the surface layer 114 of each pillar 113 may comprise a silicon material having the same type as the substrate 111. In the following, it is assumed that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to containing p-type silicon.

The inner layer 115 of each pillar 113 is comprised of an insulating material. For example, the inner layer 115 of each pillar 113 may include an insulating material such as silicon oxide. For example, the inner layer 115 of each pillar 113 may include an air gap.

In the region between the first and second doped regions 311 and 312, an insulating film 116 is provided along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. In exemplary embodiments, the insulating layer 116 provided on the exposed surface of the last insulating material 112 provided in the second direction toward the second direction may be removed.

In exemplary embodiments, the thickness of the insulating layer 116 may be less than 1/2 of the distance between the insulating materials 112. That is, between the insulating film 116 provided on the lower surface of the first insulating material among the insulating materials 112, and the insulating film 116 provided on the upper surface of the second insulating material under the first insulating material, the insulating materials ( A region may be provided in which materials other than 112 and the insulating film 116 may be disposed.

In the region between the first and second doped regions 311 and 312, first conductive materials 211-291 are provided on the exposed surface of the insulating film 116. For example, a first conductive material 211 extending in a first direction is provided between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, a first conductive material 211 extending in the first direction is provided between the insulating film 116 on the lower surface of the insulating material 112 adjacent to the substrate 111 and the substrate 111.

Hereinafter, heights of the first conductive materials 211 to 291, 212 to 292, and 213 to 293 are defined. The first conductive materials 211 to 291, 212 to 292, and 213 to 293 are defined as having first to ninth heights sequentially from the substrate 111. That is, the first conductive materials 211 to 213 adjacent to the substrate 111 have a first height. The first conductive materials 291 to 293 adjacent to the second conductive materials 331 to 333 have a ninth height. As the distance between the first conductive material and the substrate 111 increases, the height of the first conductive material increases.

Between the insulating film 116 of the upper surface of the specific insulating material among the insulating materials 112 and the insulating film 116 of the lower surface of the insulating material disposed on the specific insulating material, a first conductive material extending along the first direction is formed. Is provided. In exemplary embodiments, a plurality of first conductive materials 221 to 281 extending in the first direction are provided between the insulating materials 112. In exemplary embodiments, the first conductive materials 211 to 291 may be metal materials. In exemplary embodiments, the first conductive materials 211 to 291 may be conductive materials such as polysilicon.

In the region between the second and third doped regions 312 and 313, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. For example, in the region between the second and third doped regions 312 and 313, a plurality of insulating materials 112 extending in the first direction, sequentially disposed along the first direction, and arranged in the third direction. Accordingly, a plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112, and an insulating layer 116 provided on the exposed surface of the plurality of pillars 113. A plurality of first conductive materials 212 to 292 extending along one direction are provided.

In the region between the third and fourth doped regions 313 and 314, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. For example, in the region between the third and fourth doped regions 312 and 313, a plurality of insulating materials 112 extending in the first direction, sequentially disposed along the first direction, and arranged in the third direction. Accordingly, a plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112, and an insulating layer 116 provided on the exposed surface of the plurality of pillars 113. A plurality of first conductive materials 213 to 293 extending along one direction are provided.

Drains 320 are provided on the plurality of pillars 113, respectively. In exemplary embodiments, the drains 320 may be silicon materials doped with a second type. For example, the drains 320 may be silicon materials doped with n type. Hereinafter, it is assumed that the drains 320 include n type silicon. However, the drains 320 are not limited to containing n type silicon. In exemplary embodiments, the width of each drain 320 may be larger than the width of the corresponding pillar 113. For example, each drain 320 may be provided in the form of a pad on the top surface of the corresponding pillar 113.

On the drains 320, second conductive materials 331 ˜ 333 extending in the third direction are provided. The second conductive materials 331 ˜ 333 are sequentially disposed along the first direction. Each of the second conductive materials 331 to 333 is connected to the drains 320 of the corresponding region. In exemplary embodiments, the drains 320 and the second conductive material 333 extending in the third direction may be connected through contact plugs, respectively. In exemplary embodiments, the second conductive materials 331 ˜ 333 may be metal materials. In exemplary embodiments, the second conductive materials 331 ˜ 333 may be conductive materials such as polysilicon.

3 and 4, each pillar 113 forms a string together with an adjacent region of the insulating layer 116 and an adjacent region among the plurality of first conductive lines 211 to 291, 212 to 292, and 213 to 293. . For example, each pillar 113 forms a NAND string NS together with an adjacent region of the insulating layer 116 and an adjacent region among the first conductive lines 211 to 291, 212 to 292, and 213 to 293. The NAND string NS includes a plurality of transistor structures TS. Transistor structure TS is described in more detail with reference to FIG. 5.

FIG. 5 is a cross-sectional view illustrating the transistor structure TS of FIG. 4. 3 to 5, the insulating layer 116 includes first to third sub insulating layers 117, 118, and 119.

The surface layer 114 comprising p-type silicon of pillar 113 will act as a body. The first sub insulating layer 117 adjacent to the pillar 113 may act as a tunneling insulating layer. For example, the first sub insulating layer 117 adjacent to the pillar 113 may include a thermal oxide layer.

The second sub insulating layer 118 may operate as a charge storage layer. For example, the second sub insulating film 118 will act as a charge trapping layer. For example, the second sub insulating film 118 may include a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, or the like).

The third sub insulating layer 119 adjacent to the first conductive material 233 may act as a blocking insulating layer. In exemplary embodiments, the third sub insulating layer 119 adjacent to the first conductive material 233 extending in the first direction may be formed in a single layer or multiple layers. The third sub insulating film 119 may be a high dielectric film (eg, aluminum oxide film, hafnium oxide film, etc.) having a higher dielectric constant than the first and second sub insulating films 117 and 118.

The first conductive material 233 will act as a gate (or control gate). That is, the first conductive material 233 serving as a gate (or control gate), the third sub insulating film 119 serving as a blocking insulating film, the second sub insulating film 118 serving as a charge storage film, and the tunneling insulating film are operated. The first sub insulating layer 117 and the surface layer 114 including p-type silicon operating as a body will form a transistor (or a memory cell transistor structure). In exemplary embodiments, the first to third sub insulating layers 117 to 119 may constitute an oxide-nitride-oxide (ONO). Hereinafter, the surface layer 114 including the p-type silicon of the pillar 113 is defined as operating as a body in the second direction.

The memory block BLKi includes a plurality of pillars 113. That is, the memory block BLKi includes a plurality of NAND strings NS. In more detail, the memory block BLKi includes a plurality of NAND strings NS extended in a second direction (or a direction perpendicular to the substrate).

Each NAND string NS includes a plurality of transistor structures TS disposed along a second direction. At least one of the plurality of transistor structures TS of each NAND string NS operates as a string select transistor SST. At least one of the plurality of transistor structures TS of each NAND string NS operates as a ground selection transistor GST.

The gates (or control gates) correspond to the first conductive materials 211 to 291, 212 to 292, and 213 to 293 extending in the first direction. That is, the gates (or control gates) extend in the first direction to form word lines and at least two select lines (eg, at least one string select line SSL and at least one ground select line). GSL)).

The second conductive materials 331 ˜ 333 extending in the third direction are connected to one end of the NAND strings NS. In exemplary embodiments, the second conductive materials 331 ˜ 333 extending in the third direction operate as bit lines BL. That is, in one memory block BLKi, a plurality of NAND strings are connected to one bit line BL.

Second type doped regions 311 to 314 extending in the first direction are provided at the other end of the NAND strings. The second type doped regions 311 to 314 extending in the first direction operate as the common source line CSL.

In summary, the memory block BLKi includes a plurality of NAND strings extending in a direction perpendicular to the substrate 111 (a second direction), and the plurality of NAND strings NS are disposed on one bit line BL. It acts as a connected NAND flash memory block (eg, charge trapping type).

3 to 5, the first conductive lines 211 to 291, 212 to 292, and 213 to 293 are described as being provided in nine layers. However, the first conductive lines 211 to 291, 212 to 292, and 213 to 293 are not limited to those provided in nine layers. For example, the first conductive lines may be provided in at least eight layers forming memory cells and at least two layers forming select transistors. The first conductive lines may be provided in at least sixteen layers constituting memory cells and at least two layers constituting select transistors. In addition, the first conductive lines may be provided in a plurality of layers forming memory cells and at least two layers forming select transistors. For example, the first conductive lines may also be provided in the layer forming the dummy memory cells.

3 to 5, three NAND strings NS are connected to one bit line BL. However, the three NAND strings NS are not limited to one bit line BL. For example, m NAND strings NS may be connected to one bit line BL in the memory block BLKi. At this time, the number and common of the first conductive materials 211 to 291, 212 to 292, and 213 to 293 extending in the first direction by the number of NAND strings NS connected to one bit line BL. The number of doped regions 311 to 314 operating as the source line CSL may also be adjusted.

3 to 5, three NAND strings NS are connected to one first conductive material extending in the first direction. However, the three NAND strings NS are not limited to one first conductive material. For example, n NAND strings NS may be connected to one first conductive material. In this case, the number of bit lines 331 ˜ 333 may also be adjusted by the number of NAND strings NS connected to one first conductive material.

As described with reference to FIGS. 3 to 5, the cross-sectional areas of the pillars 113 in the first and third directions may decrease as the substrate 111 approaches the substrate 111. For example, the cross-sectional areas of the pillars 113 in the first and third directions may be varied due to process characteristics or errors.

In an exemplary embodiment, the pillar 113 is formed by providing materials such as a silicon material and an insulating material in a hole formed by etching. As the depth to be etched increases, the area along the first and third directions of the hole formed by the etching may decrease. That is, cross-sectional areas of the pillars 113 in the first and third directions may decrease as the substrate 111 approaches the substrate 111.

6 is a circuit diagram illustrating an equivalent circuit BLKi_1 according to the first embodiment of the memory block BLKi described with reference to FIGS. 3 to 5. 3 to 6, NAND strings NS11 to NS31 are provided between the first bit line BL1 and the common source line CSL. NAND strings NS12, NS22, and NS32 are provided between the second bit line BL2 and the common source line CSL. NAND strings NS13, NS23, NS33 are provided between the third bit line BL3 and the common source line CSL. The first to third bit lines BL1 to BL3 may correspond to the second conductive materials 331 to 333 extending in the third direction, respectively.

The string select transistor SST of each NAND string NS is connected to the corresponding bit line BL. The ground select transistor GST of each NAND string NS is connected to the common source line CSL. Memory cells MC are provided between the string select transistor SST and the ground select transistor GST of each NAND string NS.

Hereinafter, NAND strings NS are defined in units of rows and columns. The NAND strings NS connected in common to one bit line form one column. For example, the NAND strings NS11 to NS31 connected to the first bit line BL1 may correspond to the first column. The NAND strings NS12 to NS32 connected to the second bit line BL2 may correspond to the second column. The NAND strings NS13 to NS33 connected to the third bit line BL3 may correspond to the third column.

NAND strings NS connected to one string select line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the first string select line SSL1 form a first row. The NAND strings NS21 to NS23 connected to the second string select line SSL2 form a second row. The NAND strings NS31 to NS33 connected to the third string select line SSL3 form a third row.

In each NAND string NS, a height is defined. For example, in each NAND string NS, the height of the ground select transistor GST is defined to be one. The height of the memory cell MC1 adjacent to the ground select transistor GST is defined as two. The height of the string select transistor SST is defined as nine. The height of the memory cell MC7 adjacent to the string select transistor SST is defined as eight. As the distance between the memory cell MC and the ground select transistor GST increases, the height of the memory cell MC increases. That is, the first to seventh memory cells MC1 to MC7 are defined as having second to eighth heights, respectively.

Each NAND string NS shares a ground select line GSL. The ground select line GSL may correspond to the first conductive lines 211 to 213 having the first height. That is, it may be understood that the ground select transistors GST also have a first height.

Memory cells MC having the same height of the NAND strings NS in the same row share the word line WL. Word lines WL of the NAND strings NS having the same height and corresponding to different rows are commonly connected. That is, memory cells MC having the same height share the word line WL.

First conductive lines 221 ˜ 223 having a second height are commonly connected to form a first word line WL1. First conductive lines 231 to 233 having a third height are commonly connected to form a second word line WL2. First conductive lines 241 to 243 having a fourth height are commonly connected to form a third word line WL3. First conductive lines 251 to 253 having a fifth height are connected in common to form a fourth word line WL4. First conductive lines 261 ˜ 263 having a sixth height are commonly connected to form a fifth word line WL5. The first conductive lines 271 to 273 having the seventh height are connected in common to form a sixth word line WL6. The first conductive lines 281 to 283 having the eighth height are commonly connected to form the seventh word line WL7.

NAND strings NS of the same row share the string select line SSL. The NAND strings NS of different rows are connected to different string select lines SSL1, SSL2, SSL3, respectively. The first to third string select lines SSL1 to SSL3 may correspond to the first conductive lines 291 to 293 having a ninth height, respectively.

Hereinafter, the first string select transistors SST1 are defined as string select transistors SST connected to the first string select line SSL1. The second string select transistors SST2 are defined as string select transistors SST connected to the second string select line SSL2. The third string select transistors SST3 are defined as string select transistors SST connected to the third string select line SSL3.

The common source line CSL is commonly connected to the NAND strings NS. For example, in the active region on the substrate 111, the first to fourth doped regions 311 to 314 may be connected to each other to form a common source line CSL.

As illustrated in FIG. 6, word lines WL having the same height are connected in common. Therefore, when the word line WL of a specific height is selected, all the NAND strings NS connected to the selected word line WL will be selected.

The NAND strings NS of different rows are connected to different string select lines SSL. Therefore, by selecting and deselecting the string select lines SSL1 to SSL3, the NAND strings NS of the non-selected row among the NAND strings NS connected to the same word line WL are separated from the corresponding bit line. And the NAND strings NS of the selection row may be connected to the corresponding bit line.

In exemplary embodiments, one of the string select lines SSL1 to SSL3 may be selected during a program and a read operation. That is, the program and read operations may be performed in units of rows of NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33.

In exemplary embodiments, during a program and read operation, a select voltage may be applied to a select word line of a select row, and a select voltage may be applied to unselect word lines. For example, the selection voltage may be a program voltage Vpgm or a selection read voltage Vrd. For example, the unselected voltage may be a pass voltage Vpass or an unselected read voltage Vread. That is, the program and read operations may be performed in units of word lines of selected rows of the NAND strings NS11 to NS13, NS21 to NS23, and NS31 to NS33.

7 is a diagram illustrating a rising slope of driving signals in a general case.

As described with reference to FIGS. 3 to 5, the cross-sectional areas of the pillars 113 in the first and third directions decrease as the substrate 111 approaches the substrate 111 due to process characteristics or errors. For example, the cross-sectional area along the first and third directions of the pillar 113 corresponding to the second height is smaller than the cross-sectional area along the first and third directions of the pillar 113 corresponding to the eighth height.

Reduction of the cross-sectional area of the pillars 113 in the first and third directions means an increase in the cross-sectional areas of the first conductive lines in the second and third directions. That is, the cross-sectional area of the word lines along the second and third directions increases as the substrate 111 approaches the substrate 111. For example, as illustrated in FIG. 4, cross-sectional areas along the second and third directions of the first conductive lines 221 ˜ 223 having the second height are first conductive lines 281 having an eighth height. 283) is larger than the cross-sectional area along the second and third directions. That is, referring to FIG. 6, cross-sectional areas along the second and third directions of the first word line WL1 having the second height are in the second and third directions of the seventh word line WL7 having the eighth height. Larger than the cross-sectional area. Therefore, since the resistance of the word line is inversely proportional to the cross-sectional area, the resistance of the first word line WL1 is smaller than the resistance of the seventh word line WL7.

As described above, the word line resistance of the memory cell array having the three-dimensional structure is smaller as it is closer to the substrate. Therefore, in the general nonvolatile memory device, the driving signal provided to the word line close to the substrate has a rising slope larger than the driving signal applied to the word line far from the substrate. The difference in the slope of the rising slope may cause a decrease in the read margin due to the program speed difference.

For example, referring to FIG. 7, during the program operation, the rising of 'γ' while the first driving signal DS <1> provided to the first word line WL1 rises to the pass voltage Vpass. The seventh driving signal DS <7> having the slope and provided to the seventh word line WL7 has a rising slope of 'α' while increasing to the pass voltage Vpass. That is, while rising to the pass voltage Vpass, the rising slope of the first driving signal DS <1> is larger than the rising slope DS <7> of the seventh driving signal.

Further, for example, the first driving signal DS <1> and the seventh driving signal DS <7> are 'β' and 'δ, respectively, while rising from the pass voltage Vpass to the program voltage Vpgm. Have lysine slop. That is, while rising to the program voltage Vpgm, the rising slope of the first driving signal DS <1> is larger than the rising slope DS <7> of the seventh driving signal.

Therefore, when memory cells connected to the first word line WL1 and the seventh word line WL7 are programmed, memory cells connected to the first word line WL1 may be memory cells connected to the seventh word line WL7. Compared to faster programming. The program speed difference of these memory cells causes a decrease in read margins.

In order to minimize such a problem, the nonvolatile memory device 100 (see FIG. 1) according to an exemplary embodiment of the present disclosure may gradually increase to a program voltage Vpgm in response to the control of the ramping logic 170 (see FIG. 1). The second voltage signal VS_2 is gradually increased to the first voltage signal VS_1 and the pass voltage Vpass. The nonvolatile memory device 100 provides the first voltage signal VS_1 and the second voltage signal VS_2 to the selected word line and the unselected word lines as the driving signal DS. Hereinafter, the high voltage generation circuit 120 and the ramping logic 170 according to an embodiment of the present invention will be described in more detail.

FIG. 8 is a block diagram illustrating the high voltage generation circuit 120 and the ramping logic 170 of FIG. 1 in more detail. Referring to FIG. 8, the high voltage generator circuit 120 includes a first high voltage generator 121 and a second high voltage generator 122. Ramping logic 170 includes a first sub ramping logic 171 and a second sub ramping logic 172.

In response to the control of the first sub ramping logic 171, the first voltage generator 121 generates a first voltage signal VS_1 that gradually increases to the program voltage Vpgm. In the program operation, the first voltage signal VS_1 is provided to the word line selected as the driving signal DS.

In response to the control of the second sub ramping logic 172, the second voltage generator 122 generates a second voltage signal VS_2 that increases stepwise to the pass voltage Vpass. In the program operation, the second voltage signal VS_2 is provided to word lines unselected as the driving signal DS.

FIG. 9 is a diagram illustrating a first voltage signal VS_1 generated by the first voltage generator 121 of FIG. 8.

Referring to FIG. 9, the rising slope of the first voltage signal VS_1 is set lower than that in the general case (that is, when the first sub ramping logic 171 (see FIG. 8) is not provided). For example, as shown in FIG. 9, the rising slope of the first voltage signal VS_1 may be set based on the seventh driving signal DS <7> (see FIG. 7) having the lowest rising slope.

In this case, the rising slope of the first voltage signal VS_1 may be applied to the seventh driving signal DS <7> provided to the word line having the largest resistance (that is, the seventh word line WL7 (see FIG. 6)). Same as Rising Slop. Accordingly, the rising slop of the first voltage signal VS_1 may refer to word lines having lower resistance than the seventh word line WL7 (that is, the first to sixth word lines WL1 to WL6 (see FIG. 6). It can be kept constant at)).

FIG. 10 is a diagram illustrating a second voltage signal VS_2 generated by the second voltage generator 122 of FIG. 8.

Referring to FIG. 10, the rising slope of the second voltage signal VS_2 is set lower than that in the general case (ie, when the second sub ramping logic 172 (see FIG. 8) is not provided). For example, similar to the first voltage signal VS_1 of FIG. 9, the rising slope of the second voltage signal VS_2 may be set based on the rising slope of the seventh driving signal DS <7>. Therefore, the rising slope of the second voltage signal VS_2 may be constantly maintained at the first to seventh word lines WL1 to WL7 (see FIG. 6).

As described with reference to FIGS. 8 to 10, the first and second voltage generators 121 and 122 are each having a low rising slope in response to control of the first and second subramping logics 171 and 172, respectively. The first and second voltage signals VS_1 and VS_2 may be generated. For example, the rising slopes of the first and second voltage signals VS_1 and VS_2 may be set to be the same as the rising slope of the seventh driving signal DS <7>. However, this is merely exemplary, and the rising slopes of the first and second voltage signals VS_1 and VS_2 may be set to be lower or higher than a rising slope of the seventh driving signal DS <7>.

In the program operation, the first voltage signal VS_1 is provided as a driving signal to the selected word line, and the second voltage signal VS_2 is provided as a driving signal to the unselected word lines. 11 and 12, the configuration of the row select circuit 130 (see FIG. 1) for providing the first and second voltage signals VS_1 to the word lines as driving signals will be described in more detail.

11 is a block diagram illustrating the row selection circuit 130 of FIG. 1 in more detail. Referring to FIG. 11, the row select circuit 130 includes a word line driver 131 and a row decoder 132. The word line driver 131 includes a decoding block 131_a and first to seventh driving blocks 131_b1 to 131_b7.

The decoding block 131_a receives the row address RAi. The decoding block 131_a decodes the received row address RAi to generate decoded row addresses DRAi. The decoding block 131_a transfers the decoded row addresses DRAi to the corresponding driving blocks among the first to seventh driving blocks 131_b1 to 131_b7, respectively.

The first to seventh driving blocks 131_b1 to 131_b7 receive the decoded row addresses DRAi from the decoding block 131_a, respectively. The first to seventh driving blocks 131_b1 to 131_b7 receive the first voltage signal VS_1 and the second voltage signal VS_2 from the high voltage generation circuit 120 (see FIG. 1), respectively. The first to seventh driving blocks 131_b1 to 131_b7 may drive one of the first voltage signal VS_1 and the second voltage signal VS_2 in response to the decoded row addresses DRAi. Each prints out. Each driving block is described in more detail in FIG. 12 below.

The row decoder 133 is connected to the word line driver 131 through signal lines SL1 to SL7. The row decoder 133 is connected to the plurality of memory blocks BLK1 to BLKz, and each memory block is connected to the row decoder 133 through word lines WL1 to WL7. The row decoder 133 receives the row address RAj and selects a memory block in response to the row address RAj. The row decoder 133 receives the driving signals DS <1> to DS <7> through the signal lines SL1 to SL7 and selects the driving signals DS <1> to DS <7>. The word lines WL1 to WL7 of the memory block are provided.

FIG. 12 is a diagram for describing the driving block of FIG. 11 in more detail. In FIG. 12, the first driving block 131_1b is shown as an example. Referring to FIG. 12, the first driving block 131_b1 includes a first switch S / W1 and a second switch S / W2.

The first switch S / W1 receives the first voltage signal VS_1 and the first activation signal EN_1 from the high voltage generation circuit 120 (see FIG. 1) and the control logic 160 (see FIG. 1), respectively. The second switch S / W2 receives the second voltage signal VS_2 and the second activation signal EN_2 from the high voltage generation circuit 120 and the control logic 160, respectively. The first switch S / W1 and the second switch S / W2 are in response to the decoded row address DRAi1 provided from the decoding block 131_a, and thus, the first voltage signal VS_1 and the second voltage signal VS_2. ) Is output as the first driving signal DS <1>.

13 and 14 illustrate rising slopes of driving signals when voltage signals generated by the high voltage generation circuit 120 of FIG. 1 are provided to word lines as driving signals.

Specifically, in FIG. 13, the first voltage signal VS_1 is provided to the seventh word line WL7 selected as the driving signal, and the second voltage signal VS_2 is unselected as the driving signal (ie, the first word lines). The case provided to the sixth word lines WL1 to WL6 is illustrated. In FIG. 14, the first voltage signal VS_1 is provided to the first word line WL1 selected as the driving signal, and the second voltage signal VS_2 is unselected as the driving signal (ie, second to seventh). The case provided to the word lines WL2 to WL7 is illustrated.

As shown in FIG. 13, when the seventh word line WL7 is selected during the program operation, the seventh driving signal DS <7> is respectively increased to the pass voltage Vpass and the program voltage Vpgm. It has a rising slope of 'α' and 'β'. In this case, the driving signals DS <1> to DS <6> having a rising slop of 'α' are applied to the unselected first to sixth word lines WL1 to WL6 while rising to the pass voltage Vpass. Each is provided.

As illustrated in FIG. 14, when the program operation first word line WL1 is selected, the first driving signal DS <1>, like the seventh driving signal DS <1>, has a pass voltage ( Vpass) and a rising slope of 'α' and 'β', respectively, while rising to the program voltage Vpgm. In this case, the driving signals DS <2> to DS <7 having a rising slop of 'α' are applied to the unselected second to seventh word lines WL2 to WL7 while rising to the pass voltage Vpass. >) Are provided respectively.

As a result, the nonvolatile memory device 100 (refer to FIG. 1) according to an embodiment of the inventive concept may provide driving signals having the same rising slope to the word lines regardless of the resistance difference between the word lines. Accordingly, the nonvolatile memory device 100 can prevent a decrease in read margin due to a program speed difference.

On the other hand, the embodiments described in Figures 1 to 14 are to be understood as illustrative, the technical spirit of the present invention is not limited thereto. The technical spirit of the present invention can be applied to various embodiments and applications. Hereinafter, other embodiments and application examples of the present invention will be described in more detail.

15 is a block diagram illustrating a nonvolatile memory device 200 according to another exemplary embodiment. The nonvolatile memory device 200 of FIG. 15 is similar to the nonvolatile memory device 100 of FIG. 1 except that the RAMPM control unit 270 is implemented outside the control logic 260. That is, while the nonvolatile memory device 100 of FIG. 1 allocates a part of the control logic 160 (see FIG. 1) to the ramping control logic 170 (see FIG. 1), the nonvolatile memory device 200 of FIG. Is implemented in a separate module where the ramping control unit 270 is distinct from the control logic 260.

In this case, the ramping control unit 270 operates in response to the control of the control logic 260, and the high voltage generation unit 220 increases stepwise in response to the control of the ramping control unit 270. The voltage signals VS_1 and VS_2 are generated. Since the operation of the high voltage generation unit 220 is similar to the operation of the high voltage generation unit 120 of FIG. 1, detailed description thereof will be omitted.

1 through 15, nonvolatile memory devices 100 and 200 according to example embodiments of the inventive concepts provide driving signals having the same rising slope to each word line during a program operation. However, this is merely an example, and the nonvolatile memory devices 100 and 200 according to example embodiments may be applied to a read operation. This is described in more detail with reference to FIGS. 16 to 20 below.

16 to 18 are diagrams for explaining read disturbance caused by driving signals having different rising slops.

In FIG. 16, a distribution of threshold voltages of the memory cell MC is illustrated. For example, it is assumed that the memory cell MC has a distribution of threshold voltages corresponding to four logic states E, P1, P2, and P3. In other words, it is assumed that the memory cell MC stores two bits. However, the memory cell MC is not limited to storing two bits.

In FIG. 17, a read operation by driving signals having different rising slops is illustrated. For convenience of explanation, it is assumed that the rising slop of the driving signal provided to the first to seventh word lines WL1 to WL7 increases as the closer to the substrate. In addition, it is assumed that a read operation is performed on the second word line WL2.

In FIG. 18, the channel voltage of one NAND string of the NAND strings corresponding to the selected string line of FIG. 17 is illustrated. Specifically, FIG. 18 illustrates the channel voltage of the NAND string at the sixth time t6 (see FIG. 17). The first to seventh memory cells MC1 to MC7 correspond to memory cells belonging to the same NAND string among the memory cells of the first to seventh word lines WL1 to WL7 of FIG. 6, respectively. For convenience of explanation, it is assumed that the third memory cell MC3 has a threshold voltage corresponding to the logic state P3. It is assumed that the first, second, fourth to seventh memory cells MC1, MC2, and MC4 to MC7 have threshold voltages corresponding to the erase state E. FIG.

16 to 18, first, the bit line BL is precharged to the bit line precharge voltage VBL. Thereafter, the string selection voltage VSSL and the ground selection voltage VGSL are provided to the selected string selection line Selected SSL and the ground selection line GSL, respectively. In addition, the first selected read voltage Vrd1 is provided to the selected second word line WL2, and the unselected read voltage Vread is provided to the unselected word lines WL1 and WL3 to WL7.

As the closer to the substrate 111 is closer to the rising slope, the first to seventh driving signals DS <1> to DS <7> provided to the first to seventh word lines WL1 to WL7 are sequentially disposed. The first select read voltage Vrd1 level is reached. In this case, since the memory cells MC1, MC2, and MC4 to MC7 except the third memory cell MC3 have threshold voltages of the erase state E, the memory cells MC1, MC2, and MC4 to MC7 are sequentially disposed. Is turned on. For example, the first memory cell MC1 is turned on at the fastest third time t3 compared to the memory cells in other erase states, and the seventh memory cell MC7 is best compared to the memory cells in other erase states. It is turned on at the slow fifth time t5.

Meanwhile, since the third memory cell MC3 has a threshold voltage corresponding to the logic state P3, the third memory cell MC3 is provided with the third driving signal DS <3 provided to the third word line WL3. >), For example, turns on only when the unselected read voltage Vread is reached. Accordingly, the third memory cell MC3 may be turned on at the sixth time t6 that is slower than the other memory cells MC1, MC2, and MC4 to MC7.

In this case, as shown in FIG. 18, the channel voltage of the NAND string including the first to seventh memory cells MC1 to MC7 may be separated around the third memory cell MC3. That is, since the third memory cell MC3 is turned off and the other memory cells MC1, MC2, and MC4 to MC7 are turned on at the sixth time t6, the channel voltage of the NAND string is changed to the third memory cell. The ground voltage Vss and the bit line precharge voltage VBL are respectively divided based on the MC3. This difference in channel voltage can cause read disturbance by hot electron injection, which can lead to a reduction in read margin.

In order to prevent the above-described read disturbance, the nonvolatile memory devices 100 and 200 according to the embodiments of the present invention generate a voltage signal that gradually increases to a target voltage during a read operation, and uses the word lines as a driving signal. To provide. This is described in more detail in FIGS. 19 and 20 below.

FIG. 19 is a block diagram illustrating an example embodiment of the high voltage generation circuit 120 and the ramping logic 170 of FIG. 1. Referring to FIG. 19, the high voltage generator circuit 120 includes first and second voltage generators 121 and 122, and the ramping logic 170 includes first and second sub ramping logics 171 and 172. do.

As shown in FIG. 19, the first voltage generator 121 generates a first voltage signal VS_1 that increases in stages to the select read voltage Vrd in response to the control of the first subramping logic 171. do. That is, the first voltage generator 121 generates the first voltage signal VS_1 which gradually increases to the program voltage Vpgm during the program operation and gradually increases to the selected read voltage Vrd during the read operation. The first voltage signal VS_1 is generated. The first voltage signal VS_1 generated by the first voltage generator 121 is then provided as a drive signal to the selected word line.

Similarly, in response to the control of the second subramping logic 172, the second voltage generator 122 generates a second voltage signal VS_2 that gradually increases to the pass voltage Vpass during a program operation, and reads it. In operation, a second voltage signal VS_2 that is gradually increased to the unselected read voltage Vread is generated. The second voltage signal VS_2 generated by the second voltage generator 122 is then provided as a drive signal to unselected word lines.

As described above, the first and second voltage generators 121 and 122 generate the first and second voltage signals VS_1 and VS_2 which increase in stages during the read operation, respectively, thereby preventing read disturb. .

Meanwhile, in FIG. 19, it is assumed that the first and second voltage generators 121 and 122 operate not only in the program operation but also in the read operation. However, this should be understood as exemplary, and the high voltage generation circuit 120 according to another embodiment of the present invention may include a voltage generator that operates during a program operation and a voltage generator that operates during a read operation. This is described in more detail in FIG. 20 below.

20 is a block diagram illustrating another embodiment of the high voltage generation circuit 120 and the ramping logic 170 of FIG. 1. Referring to FIG. 20, the high voltage generation circuit 120 may include first to fourth voltage generators 121 to 124, and the ramping logic 170 may include first to fourth sub ramping logics 171 to 174. It includes.

As shown in FIG. 20, the first and second voltage generators 121 and 122 operate when a program operation is performed, and in response to the control of the first and second subramping logics 171 and 172, respectively. The first voltage signal VS_1 gradually increases to the program voltage Vpgm and the second voltage signal VS_2 gradually increases to the pass voltage Vpass. The third and fourth voltage generators 173 and 174 operate when a read operation is performed, and gradually step up to the selected read voltage Vrd in response to the control of the third and fourth subramping logics 173 and 174, respectively. The third voltage signal VS_3 and the fourth voltage signal VS_4 gradually increasing to the unselected read voltage Vread are generated. Therefore, the reduction of the read margin during the program operation and the read disturb during the read operation can be prevented, respectively.

Meanwhile, for convenience of description, it is assumed that the voltage generation circuits of FIGS. 19 and 20 are applied to the nonvolatile memory device 100 of FIG. 1, but may also be applied to the nonvolatile memory device 200 of FIG. 15. .

Meanwhile, in FIGS. 1 to 20, nonvolatile memory devices 100 and 200 according to example embodiments of the present disclosure may receive a first voltage signal VS_1 and a second voltage signal VS_2 that gradually increase to a target voltage. It is assumed to occur. However, this is for exemplary purposes only, and the technical idea of the present invention is not limited thereto. For example, nonvolatile memory devices according to example embodiments of the inventive concepts may be generated by gradually increasing only a second voltage signal VS_2 to be provided to unselected word lines to a target voltage.

Meanwhile, the ramping logic 170 may flexibly adjust the sizes of the ramping steps of the first and second voltage signals VS_1 and VS_2 according to the operation of the nonvolatile memory device 100. For example, the ramping logic 170 may control the high voltage generation circuit 120 to have different ramping steps according to levels of target voltages of the first and second voltage signals VS_1 and VS_2.

Meanwhile, in FIG. 6, it is described that the memory block BLKi described with reference to FIGS. 3 to 5 corresponds to the equivalent circuit BLK_1 according to the first embodiment. However, this is exemplary and embodiments of the present invention are not limited thereto. Hereinafter, an equivalent circuit according to the second to fifth embodiments of the memory block BLKi described with reference to FIGS. 3 to 5 will be described.

FIG. 21 is a circuit diagram illustrating an equivalent circuit BLKi_2 according to the second embodiment of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the equivalent circuit described with reference to FIG. 6, the side transistor LTR is additionally provided to each NAND string NS of the memory block BLKi_3.

In each NAND string NS, the side transistor LTR is connected between the ground select transistor GST and the common source line CSL. The gate (or control gate) of the side transistor LTR is connected to the ground select line GSL together with the gate (or control gate) of the ground select transistor GST.

As described with reference to FIGS. 3 to 6, the first conductive lines 211, 212, and 213 having the first height correspond to the ground select line GSL.

When a specific voltage is applied to the first conductive lines 211, 212 and 213 having the first height, a channel is formed in the region of the surface layer 114 adjacent to the first conductive lines 211, 212 and 213. That is, channels are formed in the ground select transistors GST. In addition, when a specific voltage is applied to the first conductive lines 211, 212 and 213, a channel is formed in the region of the substrate 111 adjacent to the first conductive lines 211, 212 and 213.

The first doped region 311 is connected to the channel generated in the substrate 111 by the voltage of the first conductive line 211. The channel generated in the substrate 111 by the voltage of the first conductive line 211 is connected to the channel generated in the surface layer 114 operating as the body in the second direction by the voltage of the first conductive line 211. .

Similarly, a channel is formed in the substrate 111 by the voltages of the first conductive lines 211, 212, and 213. The first to fourth doped regions 311 to 314 are surface layers operating as a body in a second direction through a channel generated in the substrate 111 by the voltages of the first conductive lines 211, 212, and 213. Respectively connected to 114.

As described with reference to FIGS. 3 to 6, the first to fourth doped regions 311 to 314 are commonly connected to form a common source line CSL. The common source line CSL and the channels of the memory cells MC1 to MC7 are electrically connected to each other by a channel perpendicular to the substrate 111 and a channel parallel to the substrate 111 formed by the voltage of the ground select line GSL. Connected.

That is, it may be understood that between the common source line CSL and the memory cells MC1 to MC3, a transistor driven by the ground select line GSL and perpendicular to the substrate and a transistor parallel to the substrate are provided. A transistor perpendicular to the substrate may be understood as a ground select transistor GST, and a transistor parallel to the substrate may be understood as a side transistor LTR.

FIG. 22 is a circuit diagram illustrating an equivalent circuit BLKi_4 according to a third embodiment of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi_1 of FIG. 6, in each NAND string NS, two ground select transistors GST1 and GST2 may be provided between the memory cells MC1 to MC6 and the common source line CSL. The ground select transistors GST1 and GST2 are connected to one ground select line GSL.

FIG. 23 is a circuit diagram illustrating an equivalent circuit BLKi_5 according to a fourth embodiment of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi_3 of FIG. 22, in each NAND string NS, two string select transistors SST1 and SST2 may be provided between the memory cells MC1 to MC5 and the bit line BL. have.

In NAND strings of the same row, string select transistors SST of the same height will share one string select line SSL. For example, in the NAND strings NS11 to NS13 of the first row, the first string select transistors SST1 share the eleventh string select line SSL11. The second string select transistors SST2 share the twenty-first string select line SSL21.

In the NAND strings NS21 to NS23 of the second row, the first string select transistors SST1 share the twelfth string select line SSL12. The second string select transistors SST2 share the twenty-second string select line SSL22.

In the NAND strings NS31 to NS33 of the third row, the first string select transistors SST1 share the thirteenth string select line SSL13. The second string select transistors SST2 share the twenty-third string select line SSL23.

FIG. 24 is a circuit diagram illustrating an equivalent circuit BLKi_6 according to the fifth embodiment of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the memory block BLKi_4 of FIG. 23, the string select lines SSL corresponding to the NAND strings NS of the same row are connected in common.

Meanwhile, the memory block described with reference to FIGS. 3 to 5 among the memory blocks of FIG. 2 may be implemented in various modifications. Hereinafter, modified examples of the memory block according to the embodiment of the present invention will be described.

FIG. 25 is a perspective view illustrating a second embodiment BLKj of one of the memory blocks BLK1 to BLKz of FIG. 2. A cross-sectional view along the line II ′ of the memory block BLKj is the same as the cross-sectional view shown in FIG. 4.

Compared to the memory block BLKi of FIG. 3, in the memory block BLKj, the pillars 113 ′ may be provided in the form of a square pillar. In addition, insulating materials 101 are provided between the pillars 113 ′ spaced apart by a specific distance along the first direction. In exemplary embodiments, the insulating materials 101 may extend along the second direction to contact the substrate 111.

The first conductive materials 211 to 291, 212 to 292, and 213 to 293 described with reference to FIG. 3 are formed by the insulating materials 101, and the first portions 211a to 291a and 212a to 292a and 213a to 293a. ) And second portions 211b to 291b, 212b to 292b, and 213b to 293b.

In the region on the first and second doped regions 311 and 312, each pillar 113 ′ is formed of the first portions 211a to 291a of the first conductive materials and the insulating layer 116 and one NAND string NS. ) And one NAND string NS different from the second portions 211b to 291b of the first conductive materials and the insulating layer 116.

In the region on the second and third doped regions 312 and 313, each pillar 113 ′ is formed of the first portions 212a to 292a of the first conductive materials and the insulating layer 116 and one NAND string NS. ) And one NAND string NS different from the second portions 212b to 292b of the first conductive materials and the insulating layer 116.

In the region on the third and fourth doped regions 313 and 314, each pillar 113 ′ is formed of the first portions 213a to 293a of the first conductive materials and the insulating layer 116 and one NAND string NS. ) And one NAND string NS different from the second portions 213b to 293b of the first conductive materials and the insulating layer 116.

That is, by separating the first and second portions 211a to 291a and 211b to 291b of the first conductive materials provided on both sides of each pillar 113 ′ using the insulating material 101. 113 ′ may form two NAND strings NS.

The memory block BLKj may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 21 through 24. During the program operation, the rising slope of the program voltage Vpgm and the pass voltage Vpass provided to the word lines of the memory block BLKj may be kept constant. Therefore, reduction of the read margin due to the program speed difference can be prevented. During the read operation, the rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKj may be kept constant. Thus, read disturb can be prevented.

FIG. 26 is a perspective view illustrating a modified example BLKj ′ of the memory block BLKj of FIG. 25. A cross-sectional view along the line I-I 'of the memory block BLKj' is the same as the cross-sectional view shown in FIG. Except that one pillar of the memory block BLKj 'includes the first sub-pillar 113a and the second sub-pillar 113b, the memory block BLKj' is the memory block described with reference to FIG. BLKj).

One pillar in the memory block BLKj 'includes a first sub pillar 113a and a second sub pillar 113b. The first sub pillars 113a and the second sub pillars 113b may be configured in the same manner as described with reference to FIGS. 17 and 18.

One pillar 113 ′ forms two NAND strings NS. The first portions 211a to 291a and the second portions 211b to 291b, 212b to 292b, and 213b to 293b of the first conductive materials are ground select lines GSL, word lines WL, and a string. Corresponds to the selection lines SSL. Word lines WL of the same height may be connected in common.

The memory block BLKj 'may be implemented with the equivalent circuits described with reference to FIGS. 6 or 21 to 24. In the program operation, the rising slope of the program voltage Vpgm and the pass voltage Vpass provided to the word lines of the memory block BLKj 'may be constantly adjusted. Therefore, reduction of the read margin due to the program speed difference can be prevented. During the read operation, the rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKj 'may be adjusted. Thus, read disturb can be prevented.

FIG. 27 is a perspective view illustrating a third embodiment BLKm of one of the memory blocks BLK1 to BLKz of FIG. 3. FIG. 28 is a cross-sectional view taken along line III-III ′ of the memory block BLKm of FIG. 27. Except that the n-type doped region 315 forming the common source line CSL is provided in the form of a plate, the memory block BLKm may be the memory block BLKi described with reference to FIGS. 3 to 5. It is configured in the same way. By way of example, n-type doped region 315 may be provided as an n-type well.

The memory block BLKm may be implemented with the equivalent circuits described with reference to FIGS. 6 or 21 to 24. During the program operation, the rising slope of the program voltage Vpgm and the pass voltage Vpass provided to the word lines of the memory block BLKm may be kept constant. Therefore, reduction of the read margin due to the program speed difference can be prevented. During the read operation, the rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKm may be kept constant. Thus, read disturb can be prevented.

FIG. 29 is a perspective view illustrating a modified example BLKm ′ of the memory block BLKm of FIG. 27. FIG. 30 is a cross-sectional view taken along line IV-IV 'of the memory block BLKm' of FIG. 29. The memory block BLKm 'is described with reference to FIGS. 27 and 28 except that one pillar of the memory block BLKm' includes the first sub-pillar 113a and the second sub-pillar 113b. It is the same as the memory block BLKm.

One pillar in the memory block BLKm 'includes a first sub pillar 113a and a second sub pillar 113b. The first sub pillars 113a and the second sub pillars 113b may be configured in the same manner as described with reference to FIGS. 22 and 21. As described with reference to FIGS. 27 and 28, an n-type doped region 315 forming a common source line CSL is provided in the form of a plate.

The memory block BLKm 'may be implemented with the equivalent circuits described with reference to FIG. 6 or FIGS. 21 through 24. In the program operation, the rising slope of the program voltage Vpgm and the pass voltage Vpass provided to the word lines of the memory block BLKm 'may be constantly adjusted. Therefore, reduction of the read margin due to the program speed difference can be prevented. During the read operation, the rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKm 'may be adjusted. Thus, read disturb can be prevented.

FIG. 31 is a perspective view illustrating a fourth embodiment BLKn of one of the memory blocks BLK1 to BLKz of FIG. 3. 32 is a cross-sectional view taken along line VV ′ of the memory block BLKn of FIG. 31. 31 and 32, the n-type doped region 315 forming the common source line CSL is provided in a plate form as described with reference to FIGS. 27 and 28.

Compared to the memory block BLKi described with reference to FIGS. 3 and 4, the first conductive lines 221 ′ through 281 ′ forming the word lines WL1 ˜ WL7 are provided in a plate form. do.

The surface layer 116 ′ of each pillar 113 ′ includes an insulating film. The surface layer 116 ′ of the pillar 113 ′ is configured to store data similarly to the insulating film 116 described with reference to FIG. 5. For example, the surface layer 116 ′ may include a tunneling insulating film, a charge storage film, and a blocking insulating film. The intermediate layer 114 'of the pillar 113' includes p-type silicon. The intermediate layer 114 ′ of the pillar 113 ′ acts as a body in the second direction. The inner layer 115 'of the pillar 113' includes an insulating material.

For example, when the eighth height first conductive line 281 ′ is used as the string select line SSL, the eighth height first conductive line 281 ′ is the ninth height first conductive line 291. Will be split like ').

The memory block BLKn may be implemented with the equivalent circuits described with reference to FIGS. 6 or 21 to 24. During the program operation, the rising slope of the program voltage Vpgm and the pass voltage Vpass provided to the word lines of the memory block BLKn may be kept constant. Therefore, reduction of the read margin due to the program speed difference can be prevented. During the read operation, the rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKn may be kept constant. Thus, read disturb can be prevented.

33 is a perspective view illustrating a modified example BLKn ′ of the memory block BLKn of FIG. 31. 34 is a cross-sectional view taken along line VI-VI 'of the memory block BLKn' of FIG. 33. The memory block BLKn 'is described with reference to FIGS. 31 and 32 except that one pillar of the memory block BLKn' includes the first sub-pillar 113a and the second sub-pillar 113b. Same as the memory block BLKn.

In the memory block BLKn ', one pillar includes a first sub pillar 113a and a second sub pillar 113b. The first sub pillars 113a and the second sub pillars 113b may be configured in the same manner as described with reference to FIGS. 22 and 21.

The memory block BLKn 'may be implemented with the equivalent circuits described with reference to FIGS. 6 or 21 to 24. During the program operation, the rising slope of the program voltage Vpgm and the pass voltage Vpass provided to the word lines of the memory block BLKn 'may remain constant. Therefore, reduction of the read margin due to the program speed difference can be prevented. During the read operation, the rising slope of the selected read voltage Vrd and the unselected read voltage Vread provided to the word lines of the memory block BLKn 'may be kept constant. Thus, read disturb can be prevented.

FIG. 35 is a perspective view illustrating a fifth embodiment BLKo of one of the memory blocks BLK1 to BLKz of FIG. 2. FIG. 36 is a cross-sectional view taken along a line 'VIII' of the memory block BLKo of FIG. 35.

35 and 36, on the substrate 111, first to fourth upper word lines UW1 to UW4 extending along the first direction are sequentially provided along the second direction. The first to fourth upper word lines UW1 to UW4 are spaced apart by a specific distance along the second direction. The first upper pillars UP1 are disposed to be spaced apart by a specific distance along the first direction and penetrate the first to fourth upper word lines UW1 to UW4 along the second direction.

On the substrate 111 spaced apart from the first to fourth upper word lines UW1 to UW4 in the third direction, the first to fourth lower word lines DW1 to DW4 extending along the first direction are formed. It is provided sequentially along the second direction. The first to fourth lower word lines DW2 to DW4 are spaced apart by a specific distance along the second direction.

First lower pillars DP1 are spaced apart from each other by a specific distance along the first direction and penetrate the first to third lower word lines DW1 to DW4. In addition, second lower pillars DP2 are disposed to be spaced apart by a specific distance along the first direction and penetrate the first to fourth lower word lines DW1 to DW4 along the second direction. In exemplary embodiments, the first lower pillars DP1 and the second lower pillars DP2 may be arranged in parallel along the second direction.

On the substrate 111 spaced apart from the lower word lines DW1 to DW4 in the third direction, the fifth to eighth upper word lines UW5 to UW8 extending along the first direction extend along the second direction. It is provided sequentially. The fifth to eighth upper word lines UW5 to UW8 are spaced apart by a specific distance along the second direction. The second upper pillars UP2 are disposed to be spaced apart by a specific distance along the first direction and penetrate the fifth to eighth upper word lines UW5 to UW8 along the second direction.

The common source line CSL extending in the first direction is provided on the first and second lower pillars DP1 and DP2. In exemplary embodiments, the common source line CSL may include a silicon material having n type. In exemplary embodiments, when the common source line CSL is formed of a conductive material having no polarity such as metal or polysilicon, the common source line CSL may be disposed between the common source line CSL and the first and second lower pillars DP1 and DP2. Sources of type n may additionally be provided. In exemplary embodiments, the common source line CSL and the first and second lower pillars DP1 and DP2 may be connected through contact plugs, respectively.

Drains 320 are provided on the first and second upper pillars UP1 and UP2, respectively. In exemplary embodiments, the drains 320 may include a silicon material having an n type. A plurality of bit lines BL1 to BL3 extending along the third direction are sequentially provided along the first direction on the drains 320. In exemplary embodiments, the bit lines BL1 to BL3 may be made of metal. In exemplary embodiments, the bit lines BL1 to BL3 and the drains 320 may be connected through contact plugs.

Each of the first and second upper pillars UP1 and UP2 includes a surface layer 116 ″ and an inner layer 114 ″. Each of the first and second lower pillars DP1 and DP2 includes a surface layer 116 ″ and an inner layer 114 ″. The surface layer 116 ″ is configured to store data similarly to the insulating film 116 described with reference to FIG. 5. For example, the surface layer 116 ″ of the first and second upper pillars UP1 and UP2 and the first and second lower pillars DP1 and DP2 may include a blocking insulating layer, a charge storage layer, and a tunneling insulating layer. Will include.

The tunnel insulating film will include a thermal oxide film. The charge storage film 118 may include a nitride film or a metal oxide film (eg, an aluminum oxide film, a hafnium oxide film, or the like). The blocking insulating layer 119 may be formed in a single layer or multiple layers. The blocking insulating film 119 may be a high dielectric film (eg, an aluminum oxide film, a hafnium oxide film, etc.) having a higher dielectric constant than the tunnel insulating film and the charge storage film. In exemplary embodiments, the tunnel insulation layer, the charge storage layer, and the blocking insulation layer may constitute an oxide-nitride-oxide (ONO).

The first and second upper pillars UP1 and UP2 and the inner layer 114 ″ of the first and second lower pillars DP1 and DP2 may include a silicon material having a p type. The first and second upper pillars UP1 and UP2 and the inner layer 114 ″ of the first and second lower pillars DP1 and DP2 operate as bodies in a second direction.

In the substrate 111, the first upper pillars UP1 and the first lower pillars DP1 are connected through the first pipeline contacts PC1. In exemplary embodiments, the surface layers 116 ″ of the first upper pillars UP1 and the first lower pillars DP1 may be connected through the surface layers of the first pipeline contacts PC1, respectively. The surface layers of the first pipeline contacts PC1 may be made of the same materials as the surface layers 116 ″ of the first upper pillars UP1 and the first lower pillars DP1.

In exemplary embodiments, the inner layers 114 ″ of the first upper pillars UP1 and the first lower pillars DP1 may be connected through the inner layers of the first pipeline contacts PC1, respectively. The inner layers of the first pipeline contacts PC1 may be made of the same materials as the inner layers 114 ″ of the first upper pillars UP1 and the first lower pillars DP1.

That is, the first upper pillars UP1 and the first to fourth upper word lines UW1 to UW4 form first upper strings, and the first lower pillars DP1 and the first to fourth lower words. The lines DW1 to DW4 form first lower strings. The first upper strings and the first lower strings are each connected through first pipeline contacts PC1. The drains 320 and the bit lines BL1 to BL3 are connected to one end of the first upper strings. The common source line CSL is connected to one end of the first lower strings. That is, the first upper strings and the first lower strings form a plurality of strings connected between the bit lines BL1 to BL3 and the common source line CSL.

Similarly, the second upper pillars UP2 and the fifth to eighth upper word lines UW5 to UW8 form second upper strings, and the second lower pillars DP2 and the first to fourth lower words. The lines DW1 to DW4 form second lower strings. The second upper strings and the second lower strings are connected through second pipeline contacts PC2. The drains 320 and the bit lines BL1 to BL3 are connected to one end of the second upper strings. The common source line CSL is connected to one end of the second lower strings. That is, the second upper strings and the second lower strings form a plurality of strings connected between the bit lines BL1 to BL3 and the common source line CSL.

Equivalent circuit of the memory block BLKo is shown in FIG. 6 except that eight transistors are provided in one string, and two strings are connected to each of the first to third bit lines BL1 to BL3. will be. However, the number of word lines, bit lines, and strings of the memory block BLKo is not limited.

For example, first and second pipeline contact gates (not shown) may be provided to form a channel in an inner layer acting as a body in the first and second pipeline contacts PC1 and PC2, respectively. Can be. By way of example, first and second pipeline contact gates (not shown) may be provided on the surface of the first and second pipeline contacts PC1, PC2.

For example, for convenience of description, the conductive lines UW1 to UW8 and DW1 to DW4 extending in the first direction are described as word lines. However, the upper word lines UW1 and UW8 adjacent to the bit lines BL1 to BL3 may be used as the string select lines SSL.

FIG. 37 is a block diagram illustrating a memory system 1000 including the nonvolatile memory devices 100 and 200 of FIG. 1 or 14. Referring to FIG. 37, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

The nonvolatile memory device 1100 may be configured and operate as described with reference to FIGS. 1 to 36. That is, the nonvolatile memory device 1100 continuously generates rising voltages (eg, Vpgm / Vpass or Vrd / Vread) to the target voltage, thereby uniformly increasing the rising slope of the driving signals provided to the word lines. Will keep. Thus, reduction of read margins and read disturbances will be prevented.

The controller 1200 is connected to a host and the nonvolatile memory device 1100. In response to a request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the nonvolatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1100.

In exemplary embodiments, the controller 1200 may further include well-known components, such as random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operating memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls the overall operation of the controller 1200.

The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-express) protocol, an advanced technology attachment (ATA) protocol, External (host) through at least one of a variety of interface protocols, such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol. Are configured to communicate with each other. The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be configured to additionally include an error correction block. The error correction block is configured to detect and correct an error of data read from the nonvolatile memory device 1100 using an error correction code (ECC). By way of example, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device such that a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, Memory cards such as SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS) and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive SSD, an operation speed of a host connected to the memory system 1000 is significantly improved.

As another example, the memory system 1000 may be a computer, an ultra mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless device. Wireless phones, mobile phones, smart phones, e-books, portable multimedia players, portable game consoles, navigation devices, black boxes ), Digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital video player ( digital picture player, digital video recorder, digital video player, device that can send and receive information in wireless environment, one of various electronic devices that make up home network, computer network Ha Is provided as one of various components of an electronic device, such as one of various electronic devices, one of various electronic devices constituting a telematics network, one of various components constituting an RFID device, or a computing system.

In exemplary embodiments, the nonvolatile memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), and plastic dual in. Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer -Can be packaged and implemented in the same way as Level Processed Stack Package (WSP).

FIG. 38 is a block diagram illustrating an application example of the memory system 1000 of FIG. 37. Referring to FIG. 38, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of nonvolatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. In FIG. 38, the plurality of nonvolatile memory chips are illustrated to communicate with the controller 2200 through the first through kth channels CH1 through CHk.

Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS. 1 to 36. That is, the nonvolatile memory chip generates voltages (eg, Vpgm / Vpass or Vrd / Vread) that increase step by step to the target voltage, thereby keeping the rising slope of the drive signals provided to the word lines constant. Thus, reduction of read margins and read disturbances will be prevented.

In FIG. 38, a plurality of nonvolatile memory chips are connected to one channel. However, it will be appreciated that the memory system 2000 can be modified such that one nonvolatile memory chip is connected to one channel.

FIG. 39 is a block diagram illustrating a computing system 3000 including the memory system 2000 described with reference to FIG. 38. Referring to FIG. 39, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, and a memory system 2000. .

The memory system 2000 is electrically connected to the CPU 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 39, the nonvolatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the nonvolatile memory device 2100 may be configured to be directly connected to the system bus 3500.

In FIG. 39, the memory system 2000 described with reference to FIG. 38 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 37.

In exemplary embodiments, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 37 and 38.

In the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

100, 200; Nonvolatile memory device
110; Memory cell array
BLK1 to BLKz; Memory block
NS; NAND string
Vpgm; Program voltage
Vpass; Pass voltage
Vrd; Read voltage optional
Vread; Non-selective read voltage
VS_1: first voltage signal
VS_2: second voltage signal

Claims (10)

A memory cell array including a plurality of memory cells stacked in a direction orthogonal to the substrate;
A row select circuit coupled to the memory cell array through word lines; And
A voltage generation circuit for generating voltages to be provided to said word lines,
And the voltage generator circuit generates the voltages in a stepwise increment up to a target voltage level. The method of claim 1,
And the voltage generation circuit generates a voltage signal that gradually increases to a pass voltage level during a program operation. The method of claim 1,
The voltage generator circuit
A first voltage generator for generating a first voltage signal that gradually increases to a program voltage level; And
And a second voltage generator for generating a second voltage signal that increases in stages to a pass voltage level. The method of claim 3, wherein
The row selection circuit provides the second voltage signal as driving signals to unselected word lines among the word lines, and the driving signals provided to the unselected word lines have the same rising slope. . The method of claim 1,
And the voltage generation circuit generates a voltage signal that increases in steps to an unselected read voltage level in a read operation. The method of claim 1,
The voltage generator circuit
A first voltage generator for generating a first voltage signal in increments up to a select read voltage level; And
And a second voltage generator for generating a second voltage signal that increments gradually to an unselected read voltage level. The method according to claim 6,
The row selection circuit provides the second voltage signal as driving signals to unselected word lines among the word lines, and the driving signals provided to the unselected word lines have the same rising slope. . The method of claim 1,
The voltage generator circuit
A first voltage generator for generating a first voltage signal that gradually increases to a program voltage level;
A second voltage generator for generating a second voltage signal that gradually increases to a pass voltage level;
A third voltage generator for generating a third voltage signal that is incrementally increased to a select read voltage level; And
And a fourth voltage generator for generating a fourth voltage signal that is incrementally increased to an unselected read voltage level. The method of claim 1,
And a ramping logic to control the voltage generation circuit to have different ramping step sizes according to target voltage levels of the voltages. The method of claim 1,
And memory cells on a plane parallel to the substrate share the same word line.

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