JPH09231754A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep constant the boosted voltage of a boosting circuit independently of the capacity of memory and easily change the capacity of memory depending on the application. SOLUTION: The memory device is composed of a plurality of memory cores MCO1 ,..., MCO5 , a control circuit 1 used in common by these memory cores, a column decoder 2, a read/write amplifier 3 and a data bus DUBUS. Each memory core is provided with a boosting circuit 10, a row decoder 20, a memory cell array 30 and a sense amplifier array 40, each memory core is arranged in the wiring direction of the data bus DBUS, the control circuit 1 and column data 2 are arranged on the extending line and the memory cell of each memory core is selectively connected the data bus DBUS depending on the memory core selection signal from the control circuit. Therefore, access is made only to the selected memory core and memory capacity can easily be changed depending on application by increasing or decreasing the number of memory cores.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device in which the design of memory capacity and bit configuration can be easily changed.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated,
It is becoming more common to combine a logic circuit and a memory on a single semiconductor chip. When focusing on a memory embedded together with a logic circuit, it is desirable that the memory capacity be optimized to some extent, and that the memory capacity and the bit configuration have independent parameters.

[0003]

However, in the development of the conventional memory device, since the development was carried out on the basis of a certain specific specification, for example, the capacity or bit configuration of the memory, each memory constituting the memory cell array was developed. When boosting the level of the word line connected to the gate electrode of the cell, only one boosted voltage supply circuit is arranged in one semiconductor chip.

For example, in a memory device composed of a DRAM, when data of a high word line level is written, a voltage higher than a power supply voltage V _dd by a threshold voltage V _{th of} a transistor forming a memory cell is used. You will need it. A booster circuit is generally used to generate this high voltage.

FIG. 5 is a circuit diagram showing the structure of a general booster circuit. In FIG. 5, φ is the input terminal of the boosting clock signal, V _dd is the power supply voltage, GND is the ground potential, INV ₁
Is an inverter, ND ₀ is a node, NT ₀ is an nMOS transistor, C ₁ is a boosting capacitor, C ₂ is a node ND
Each shows a parasitic capacitance of ₀ . As shown, in this booster circuit, the input terminal φ for the boosting clock signal φ
Is connected to the gate electrode of the nMOS transistor NT ₀ , and further connected to the node ND ₀ to be boosted via the inverter INV ₁ . Also, the drain electrode of the nMOS transistor NT ₀ is connected to the supply line of the power supply voltage V _dd , and the source electrode is connected to the node ND ₀ .

Here, the boosting capacitor C of the boosting circuit is used.
The capacitance of ₁ is C _B , the parasitic capacitance of the node ND ₀ to be boosted is C _P, and in the booster circuit shown in FIG. 5, the capacitance C _B of the capacitor C ₁ for boosting and the node ND ₀ to be boosted are used.
The boosted voltage is determined by the ratio to the parasitic capacitance C _{P of} .

Now, consider the case where, for example, the power supply voltage V _dd and the ground potential are mutually applied to the input terminal φ. When a high level voltage, that is, the power supply voltage V _dd is applied to the input terminal φ, the voltage of the node ND ₀ is V _dd −V
It becomes _th . The boosting capacitor C ₁ is charged by this voltage. When a low level voltage, that is, a ground potential is applied to the input terminal φ, the inverter I
The output terminal of NV ₁ is at a high level, for example, the power supply voltage V
_The voltage becomes _dd level, the node ND ₀ is raised by the boosting capacitor C ₁ , and the voltage thereof is expressed by the following equation.

[0008]

[Equation 1]

FIG. 6 shows a timing chart of the booster circuit shown in FIG. As shown, when the input terminal φ is held at a high level, for example, the power supply voltage V _dd level, the node ND ₀ is held at a voltage level of V _dd -V _th . Then, the input terminal φ is at a low level, for example,
When the level changes to the ground potential, the node ND ₀ is raised by the boosting capacitor C ₁ and boosted to the voltage level shown in the equation (1).

As shown in equation (1), when the number of memory cells forming the memory cell array changes, the node ND ₀
The parasitic capacitance C _P also changes and the boosted potential changes.
Therefore, the boosted voltage is low and may not reach the reference value. In this case, the voltage of the node ND ₀ to be boosted is low, the amount of charges written in the selected memory cell is small, and a data write error may occur.
On the other hand, when the voltage of the node ND ₀ to be boosted is higher than the reference value, extra stress is applied to the memory cell to be written, and the reliability of the memory is deteriorated.

Further, since the data extraction line in each memory core is usually wired in parallel with the word line,
When the number of memory cores increases, the number of data fetch lines from the memory core also increases. Therefore, conventionally, it is necessary to redesign each time the memory capacity is different.

The present invention has been made in view of such circumstances, and an object thereof is to keep the boosted voltage of the booster circuit constant regardless of the capacity of the memory, and to easily increase the capacity of the memory according to the application. It is to provide a semiconductor memory device that can be changed.

[0013]

To achieve the above object, the present invention provides a semiconductor memory device having a plurality of memory cores each including at least a memory cell array and a selection circuit for selecting a memory cell from the memory cell array. A booster circuit that supplies a predetermined voltage to the memory cell selected by the selection circuit is provided for each memory core.

Further, according to the present invention, there is provided a semiconductor memory device having a plurality of memory cores each including at least a memory cell array and a selection circuit for selecting a memory cell from the memory cell array, wherein the plurality of memory cores have a common data bus. It is connected to the.

According to the present invention, in the semiconductor memory device including a plurality of memory cores, the booster circuit is provided for each memory core. As a result, the capacity of the semiconductor memory device can be set according to the application by arbitrarily increasing or decreasing the number of memory cores, the boosted voltage by the booster circuit is maintained at a predetermined voltage value, and the boosted voltage by the change in the storage capacity is increased. Fluctuations are prevented.

Further, according to the present invention, in a semiconductor memory device composed of a plurality of memory cores, these memory cores have a common data bus. Further, for example, by providing a switching circuit whose on / off state is controlled according to a control signal between the selected memory cell and the common data bus in each memory core, the memory in the selected memory core is provided. Only cells are connected to a common data bus and are accessed. A plurality of memory cores are arranged side by side in the wiring direction of the data bus. For example, by arranging a peripheral circuit such as a control circuit on an extension line of the peripheral circuit, by adjusting the number of memory cores, a predetermined storage capacity can be obtained. The semiconductor memory device can be configured, redesign of peripheral circuits, data buses, etc. is not required, and the capacity of the semiconductor memory device can be easily changed according to the application.

[0017]

1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. In FIG. 1, MCO ₁ , MCO ₂ , MCO ₃ , MCO ₄ , MCO
₅ is a memory core, 1 is a control circuit, 2 is a column decoder,
3 is a read / write amplifier (R / W Amp.),
CL is a column line, DBUS is a data bus, 10 is a booster circuit, 20 is a row decoder, 30 is a memory cell array, 4
Reference numeral 0 indicates a sense amplifier array, respectively.

As shown in FIG. 1, for example, five notes
Recore MCO₁, MCO_Two, MCO _Three, MCO_Four, MC
O_FiveAnd control circuit 1, column decoder 2, read /
A semiconductor memory device is configured by the write amplifier 3.
I have. And the memory core MCO₁, MCO_Two, MC
O_Three, MCO_Four, MCO_FiveIs control circuit 1, column decoder
2, read / write amplifier 3 and data bus D
We share BUS.

The control circuit 1 is used for each memory core MCO.₁, MC
O_Two, MCO_Three, MCO_Four, MCO _FiveWriting data
Read and read operations. Column data 2 is input
Predetermined column line CL according to the applied column address
Select and set to the active state. Read / write
Integral amplifier 3 is used for each memory core MCO₁, MCO_Two, MC
O_Three, MCO_Four, MCO_FiveData written to and
Each memory core MCO₁, MCO_Two, MCO_Three, MC
O_Four, MCO_FiveThe data read from is amplified.

Then, each memory core MCO ₁ , MC
O ₂ , MCO ₃ , MCO ₄ , and MCO ₅ are booster circuits 10,
It includes a row decoder 20, a memory cell array 30, and a sense amplifier array 40. The memory cores MCO ₁ , MCO ₂ , MCO ₃ , MCO ₄ , MCO ₅
Have the same configuration, only the internal configuration of the memory core MCO ₁ is shown in FIG.

Each memory core MCO ₁ , MCO ₂ , MCO
₃ , MCO ₄ and MCO ₅ are selected by the memory core selection signal from the control circuit 1, and in the selected memory core, a common column decoder and a row decoder in each memory core are used to select a predetermined memory cell from the memory cell array 30. Is selected and is accessed. That is, the data input from the external circuit is written to the selected memory cell via the shared data bus, and the data stored in the selected memory cell is read to the external circuit.

FIG. 2 is a circuit diagram showing the configuration of the memory cores MCO _n and MCO _{n + 1} . In FIG. 2, 10 is a booster circuit, 20 is a row decoder, 30 is a memory cell array, 4
0 is a sense amplifier array, WL ₀ and WL ₁ are word lines,
BL ₀ , / BL ₀ , BL ₁ , / BL ₁ , ..., BL ₃ , /
BL ₃ is a bit line, CL ₀ and CL ₁ are column lines, D
B ₀ , / DB ₀ , DB ₁ , / DB ₁ are data buses DBU
Each data line constituting S, SN, SP are voltage input terminals of the sense amplifier, m ₀ , m ₁ are memory core selection signal input terminals, MC ₀₀ , MC ₁₀ , MC ₀₁ , MC ₁₁ , ..., MC ₀₃ , M
C ₁₃ is each memory cell forming the memory cell array 30,
SA ₀ , SA ₁ , ..., SA ₃ are sense amplifier arrays 40.
, SW _m is a switching circuit controlled by the memory core selection signal input to the memory core selection signal input terminals m ₀ and m ₁ , and SW _c is input to the column lines CL ₀ and CL ₁ . The respective switching circuits controlled by signals are shown.

The memory core MCO _n and the memory core M
Although it has the same configuration as CO _{n + 1} , in FIG. 2, the booster circuit 10 and the row decoder 20 of the memory core MCO _{n + 1} are shown.
Are omitted, and the internal configurations of the memory cell array 30a and the sense amplifier array 40a are also omitted.

As shown, each memory cell array 30
Memory cells MC arranged in matrix ₀₀, MC_Ten, M
C₀₁, MC₁₁, ..., MC₀₃, MC₁₃Composed by
Each column of memory cells has a word line WL₀WL₁Contact
Each memory cell row is connected to the bit line BL.₀,
/ BL₀, BL₁, / BL₁,…, BL_Three, / BL_ThreeTo
It is connected. And these bit lines BL₀, /
BL₀, BL₁, / BL₁,…, BL_Three, / BL_ThreeIs
Sense amplifier SA₀, SA₁,,, SA_ThreeThrough the
Ching circuit SW_m, SW_CVia the data bus DBUS
Each data line DB₀, / DB₀, DB₁, / DB₁Contact
Has been continued.

The switching circuit SW _m is composed of, for example, a plurality of nMOS transistors, and each nMO is provided.
The gate electrodes of the S transistors are connected to the memory core selection signal input terminals m ₀ and m ₁ , respectively. The switching circuit SW _C is composed of, for example, a plurality of nMOS transistors, and the gate electrodes of the nMOS transistors are connected to the column lines CL ₀ and CL ₁ , respectively. Further, the nMOS transistors forming the switching circuits SW _m and SW _C are respectively connected to the sense amplifier S
_{A 0, SA 1, ...,} SA 3 and the data the data lines DB ₀ that comprise bus _{DBUS, / DB 0, DB 1} , / are connected in series between the DB _1.

The operation of the semiconductor memory device according to the present embodiment having the above structure will be described below. Here, for example, the memory core MCO _n is selected, and data writing and reading operations are performed with respect to the memory cells therein. When the memory core MCO _n is selected, the control circuit 1 shown in FIG.
An active selection signal, for example, a high-level memory core selection signal is input to the memory core selection signal input terminal m ₀ of O _n . Therefore, each nMOS transistor forming the switching circuit SW _m is set to the conductive state.

Then, according to the column address input by the column decoder 2 shown in FIG.
The column line CL ₀ is selected and set to the active state, that is, the high level state. Therefore, in the switching circuit SW _C , the nMOS transistors connected to the sense amplifiers SA ₀ and SA ₁ are set to the conductive state, and the bit lines BL ₀ , / BL ₀ , BL ₁ and / BL ₁ are selected bits. Become a line.

Further, the memory core MCO_nAt
C. Depending on the row address input to the decoder 20,
For example, word line WL₀Is selected, the word line W
L₀And the selected bit line BL₀, / BL₀, BL₁,
/ BL₁Memory cell MC at the intersection with₀₀, MC₀₁Is selected
Selected. As shown in FIG. 2, the memory core MCO
_{n + 1}Also, the column line CL in the active state₀
Switching circuit SW_COf which, the sense amplifier S
A ₀, SA₁NMOS transistor connected to is conductive
Is set to the state, but the memory core MCO_{n + 1}Is a non-selected
Memory core selection signal input terminal m₁To non
Active state select signal, for example, low level select signal
Selection signal is input and switching circuit SW_mMake up
Each nMOS transistor is set to the non-conducting state,
SAMP SA₀, SA₁Bit line BL connected to₀,
/ BL₀, BL₁, / BL₁Shared data bus D
BUS data line DB₀, / DB₀, DB₁, / DB₁
Unselected memory core MCO_{n + 1}In
Access to the memory cell is avoided. Therefore, each
The memory core can share the data bus.

At the time of read operation, in the selected memory core MCO _n , the selected memory cells MC ₀₀ , MC _00
The data stored in ₀₁ are the bit lines BL ₀ and / B, respectively.
It is read by L ₀ , BL ₁ , / BL ₁ and further amplified by the sense amplifiers SA ₀ , SA ₁ . Of the switching circuits SW _m and SW _C , the data lines DB ₀ , / DB ₀ ,
Since the nMOS transistors connected to DB ₁ and / DB ₁ are set to the conductive state, the sense amplifier SA ₀ ,
The data amplified by SA ₁ is the data lines DB ₀ , /
Output to DB ₀ , DB ₁ , / DB ₁ .

In the write operation 3, the switching circuit SW
_m , SW _C inner data line DB ₀ , / DB ₀ , DB ₁ , /
Since the nMOS transistor connected to DB ₁ is set to the conductive state, the data lines DB ₀ , / DB ₀ , DB
_The data input to ₁ and / DB ₁ are transmitted through the switching circuits SW _m and SW _C , respectively, to the sense amplifiers SA ₀ and
It is input to SA ₁ , amplified by the sense amplifiers SA ₀ , SA ₁ , and then bit lines BL ₀ , / BL ₀ , BL ₁ , / B.
The selected memory cells MC ₀₀ and MC ₀₁ output to L ₁
Is written to.

As described above, according to the semiconductor memory device of the present embodiment, in the selected memory core MCO _n , the memory cells MC ₀₀ and MC ₀₁ selected according to the input column address and row address are selected. A read or write operation is performed, the data stored in the selected memory cell is read to the external circuit, and the data input from the external circuit is written to the selected memory cell.

On the other hand, in the unselected memory core MCO _{n + 1} , since the inactive selection signal is input to the memory core selection signal input terminal m ₁ , the switching circuit SW _C
Access to the memory cells in the non-selected memory core MCO _{n + 1} without connecting each memory cell forming the memory cell array to the data bus DBUS. Is prevented.

FIG. 3 shows the sense amplifier SA _{0 according to the} present invention.
FIG. 3 is a circuit diagram showing the configuration of FIG. The sense amplifier S
Since A ₀ , SA ₁ , SA ₂ , and SA ₃ have the same configuration, the sense amplifier SA ₀ will be described here as an example. In FIG. 3, PT ₁ and PT ₂ are pMOS transistors,
NT ₁ and NT ₂ are nMOS transistors, ND ₁ and ND
₂ is a node, and SN and SP are voltage input terminals, respectively. For example, a high level voltage is applied to the voltage input terminal SP, and a low level voltage is applied to the voltage input terminal SN.

As shown, the pMOS transistor PT
₁ and the gate electrode of the nMOS transistor NT ₁ are connected, and these connection points are connected to the node ND _2.
The gate electrodes of the S transistor PT ₂ and the nMOS transistor NT ₂ are connected, and the connection point between them is the node ND ₁
It is connected to the. That is, the pMOS transistor P
The transistor pair of T ₁ , nMOS transistor NT ₁ and pMOS transistor PT ₂ , nMOS transistor NT ₂ respectively constitutes an inverter, and the input terminal and output terminal of these inverters are connected to each other. Further, the bit line BL ₀ is connected to the node ND ₁ and the bit line / BL ₀ is connected to the node ND ₂ .

At the time of reading and writing data,
Signals of mutually opposite levels are applied to the bit lines BL ₀ and / BL ₀ . For example, if a high level signal is applied to the bit lines BL _0, signal always low level to the bit line / BL ₀ is applied.

In such a state of the bit lines BL ₀ and / BL ₀ , the nMOS transistor NT ₂ is in a conductive state, and the low level potential applied to the input terminal SN is applied to the node ND ₂ and the bit line / BL ₀ . Is output. As a result, the pMOS transistor PT ₁ is in the conductive state, and the high level voltage applied to the voltage input terminal SP is output to the node ND ₁ and the bit line BL ₀ . The nMOS transistor NT ₁ and the pMOS transistor PT ₂ are held in the non-conducting state.

When the states of the voltages input to the bit lines BL ₀ and / BL ₀ are different from the above, the low level voltage applied to the input terminal SN is applied to the bit line BL ₀ in a similar manner to the above description. The high-level voltage that is input and applied to the voltage input terminal SP is input to the bit line / BL ₀ . As described above, the sense amplifier SA ₀
The voltage applied to the bit lines BL ₀ , / BL ₀ is applied to the voltage input terminals SP, SN by the sense amplifier SA ₀ , respectively.
It is amplified to the voltage level applied to.

FIG. 4 is a timing chart showing the read operation of the memory core MCO _n shown in FIG. As shown in this timing chart, at the time of reading, the row decoder 20 first selects, for example, the word line WL ₀ according to the input row address and sets it to the active state, for example, the high level state. As a result, the memory cell MC ₀₀ is selected, and the data stored in the memory cell MC ₀₀ is transferred to the bit lines BL ₀ , /.
Read to BL ₀ .

Next, the voltage input terminals SN and SP are activated.
Is set to the active state, that is, the voltage input terminals SN and S
Low level and high level voltages are applied to P respectively.
Bit line BL₀, / BL₀Read to
Data is sense amplifier SA ₀Is amplified by So
After that, by the control circuit 1 and the column decoder 2,
Memory core selection signal and column line CL₀Is active
State, that is, the memory core selection signal line input end
Child m₀High-level selection signal is input to the
Ram line CL₀A high-level selection signal is input to. This
As a result, the switching circuit SW_m, SW_CGiven
The nMOS transistor is set to the conductive state and the bit line
BL₀, / BL₀And data line DB₀, / DB₀Each
Connected to the sense amplifier SA₀Amplified by
Data line DB₀, / DB₀Output to
You.

At this time, in the unselected memory core, for example, the memory core MCO _{n + 1} shown in FIG. 2, the inactive selection signal, that is, the low level signal is input to the memory core selection signal input terminal m _1. Signal is input, the data is read only to the selected memory core without connecting the bit line in the non-selected memory core to the data bus DBUS. In this way, the number of memory cores can be set arbitrarily, a predetermined memory core is selected by the memory core selection signal, and only the selected memory core is accessed via the data bus. It becomes possible to share the bus.

As described above, according to this embodiment, a plurality of memory cores MCO ₁ , MCO ₂ , ..., MCO are provided.
₅ and a control circuit 1, a column decoder 2, a read / write amplifier 3, a data bus DBUS and the like shared by these memory cores constitute a memory device, and each memory core has a booster circuit 10, a row decoder 20, a memory cell array 30 and a memory cell array 30. A good sense amplifier array 40 is provided, each memory core is arranged side by side in the wiring direction of the data bus DBUS, the control circuit 1, the column decoder 2 and the like are arranged on the extension line thereof, and each memory core is arranged from the control circuit. Since the switching circuit whose ON / OFF state is controlled by the selection signal is selectively connected to the data bus DBUS, only the selected memory core is accessed and the number of memory cores is changed according to the application. The storage capacity can be easily changed by increasing or decreasing.

[0042]

As described above, according to the semiconductor memory device of the present invention, the boosted voltage of the booster circuit can be held constant regardless of the memory capacity, and the memory capacity can be easily changed according to the application. There are advantages.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a memory core according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of a sense amplifier.

FIG. 4 is a timing chart when reading a memory core.

FIG. 5 is a circuit diagram showing a configuration of a booster circuit.

FIG. 6 is a timing chart of a booster circuit.

[Explanation of symbols]

1 ... Control circuit, 2 ... Column decoder, 3 ... Read / write amplifier, 10 ... Booster circuit, 20 ... Row decoder,
30 ... Memory cell array, 40 ... Sense amplifier array,
MCO ₁ , MCO ₂ , MCO ₃ , MCO ₄ , MCO ₅ ...
Memory core, WL ₀ , WL ₁ ... Word line, CL, C
L ₀ , CL ₁ ... Column line, DBUS ... Data bus, BL
₀ , / BL ₀ , BL ₁ , / BL ₁ , ..., BL ₃ , / BL
₃ ... bit line, DB ₀ , / DB ₀ , DB ₁ , / DB ₁ ...
Data line, SN, SP ... Sense amplifier voltage input terminal, P
T ₁ , PT ₂ ... pMOS transistor, NT ₁ , NT ₂
... nMOS transistor, ND ₀ , ND ₁ , ND ₂ ... node, φ ... boosting clock signal input terminal, INV ₁ ... inverter, C ₁ ... boosting capacitor, C ₂ ... parasitic capacitance,
m ₀ , m ₁ ... Memory core selection signal input terminal, MC ₀₀ , M
C ₁₀ , MC ₀₁ , MC ₁₁ , ..., MC ₀₃ , MC ₁₃ ... Memory cell, SA ₀ , SA ₁ , ..., SA ₃ ... Sense amplifier, SW
_m , SW _c ... switching circuit, V _dd ... power supply voltage, GN
D ... Ground potential

Claims (5)

[Claims] 1. A semiconductor memory device having a plurality of memory cores configured by at least a memory cell array and a selection circuit for selecting a memory cell from the memory cell array, wherein the memory cell selected by the selection circuit for each memory core. A semiconductor memory device in which a booster circuit for supplying a predetermined voltage is provided. 2. The memory cores are arranged in parallel,
The semiconductor memory device according to claim 1, wherein a control circuit for controlling these memory cores is arranged on an extension line of this array. 3. A semiconductor memory device having a plurality of memory cores each comprising at least a memory cell array and a selection circuit for selecting a memory cell from the memory cell array, wherein the plurality of memory cores are connected to a common data bus. Semiconductor memory device. 4. The semiconductor memory device according to claim 3, further comprising connecting means for selectively connecting each memory cell array of each memory core and the common data bus in response to a selection signal. 5. The semiconductor memory according to claim 3, wherein each of the memory cores is arranged in a wiring direction of the common data bus, and a control circuit for controlling these memory cores is arranged on an extension line thereof. apparatus.