JPH02248069A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an element from deteriorating in characteristics by a method wherein a conductive amorphous thin film or an oxide film is deposited on a gate electrode at the implantation of ions for the formation of a gently sloped drain structure. CONSTITUTION:A conductive amorphous thin film or an oxide film 7 which serves as a stopper at the implantation of ions is formed on the whole face of a substrate 1, then an well 3 side is covered with a resist pattern 8, and phosphorus ions are implanted to form an N<-> layer 9. Then, the film 7 is removed, and SiO2 is deposited on the whole surface of the substrate 1, which is anisotropically etched to form a side wall 10 on both the sides of a gate electrode 6. By this method, a gate electrode is protected against channeling caused by the implantation of ions, and a knock-on phenomenon of impurity inside the gate electrode is prevented by the film 7, so that a semiconductor device of this design can be prevented from deteriorating in characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
It is suitable for use in manufacturing an OS integrated circuit (CMO8LSI).

BACKGROUND OF THE INVENTION In recent years, the development of CMO8LSI has been remarkable, and its high degree of integration is unrivaled by other semiconductor devices, especially in the sense that it can take full advantage of its advantage of low power consumption. Now, various process flows of conventional CMO8LSI manufacturing methods have been proposed. For example, it is described on pages 26 to 27 of Submicron Device I (Electronic Materials Series, published by Maruzen Co., Ltd.) by Mitsumasa Koyanagi. but,
As miniaturization progresses, processes become more complex, and it becomes necessary to propose new structures and process changes accordingly. A hot carrier effect has become a very serious problem in recent LSI development. This occurs because the applied power supply voltage does not decrease and remains at the conventional 5 volts even though the element dimensions of the MOS device have been reduced in accordance with the scaling law. In other words, the high electric field generated inside the MOS device causes an electron detachment phenomenon, and the so-called hot carriers with high energy generated at this time are trapped in the gate oxide film of the MOS device, leading to deterioration of device characteristics. be. As one of the countermeasures, a structure called LDD (low slope drain) was proposed, and the current 1μm
Commonly used in nearby devices. A manufacturing method before and after forming a source/drain of a MOS device that takes this into consideration is shown below as a recent conventional example, which is added to the process flow of the 0MO8LSI described above.

FIGS. 3(a) to 3(e) show process flow diagrams of conventional CMOS devices. As shown in FIG. 3(a), P-well 2 and PMO 8 are formed on the silicon substrate.
After forming a thick field oxide film (10 to 25 nm) 4 on each element, a low resistance gate electrode (polycrystalline silicon or metal into which impurities have been introduced) 8 is formed. . Next, as shown in FIG. 3(b), the N well 3 side is covered with a resist pattern 8, and, for example, phosphorus is ion-implanted (acceleration voltage: 40 K e V, implantation amount: 1 to 3E13/cm") at a surface concentration of 1. ~IE1
The n-layer 9 is formed to have a thickness of about 8/cm''.

This part weakens the high electric field mentioned above.

Naturally, phosphorus is also injected into the gate electrode 8 at this time. Next, as shown in FIG. 3(C), further outside this is a side wall (hereinafter referred to as side wall) 1 which plays the role of positioning for forming a high concentration layer that will become a so-called source/drain.
form 0. This can be easily achieved by forming an insulating film over the entire surface and then performing an anisotropic etchback vertically on only the thickness of the insulating film. After forming the sidewall 10, FIG. 3(d)
After covering the N-well layer 3 with a resist pattern 14 as shown in FIG.
s) ion implantation (acceleration voltage 40-80KeV14-E
By doing so, a source/drain layer with a gentle concentration gradient is formed, and the local electric field can be considerably relaxed.

Naturally, arsenic is also implanted into the gate electrode 6 at this time.

Although this conventional example shows an example of electric field relaxation only on the N channel side, which is more problematic, it may also be applied on the P channel side as necessary. Similarly, source/drain layers on the P channel side are also formed.

For example, as shown in FIG. 3(e), after covering the P-well layer 2 with a resist pattern 12, the highly-concentrated source/drain layer 13 is implanted with BFs (accelerating voltage 20 to 60%).
Kev11-5E15/Cm2). After that, you can follow the usual process (such as the above-mentioned literature).

Here, source/drain regions are formed using NMO8°PMO
Although an example is shown in which the source/drain regions are formed in the order of PMO81NMO8 and according to the conventional manufacturing method, the ion implantation for forming the LDD structure or the formation of the source/drain layer is There was a problem in that channeling to the gate electrode occurred during ion implantation.

In other words, during the aforementioned ion implantation, a large amount of phosphorus or arsenic penetrates deeply into the grains of polycrystalline silicon, which is the gate electrode, and reaches the substrate, deteriorating the device characteristics. This channeling problem is caused by the fact that polycrystalline silicon grown on an insulating film (gate oxide film) has a plane orientation, so the implanted ions may be oriented along grain boundaries or in specific plane orientations within grains. Arising from reaching very deep in a particular direction. Gate length is 0.8μ
In NMO8 with m1 gate oxide film of 16 nm, n-
Phosphorous layer implantation (40K e V+ 2 E 13/
c m”)+n+ source/drain layer with arsenic (80K
e V, 6E15/cm2), approximately 1
For 0% NMO8, an IDD (drain current')-VG (gate voltage) characteristic with a hump shape as shown in FIG. 4(a) was observed. Also, Fig. 4(b) shows NMO8
FIG. 3 is a normal IDD-VG characteristic diagram of FIG. The phenomenon of deterioration of device characteristics seen in Figure 4 is due to the thin gate oxide film.
It has also been confirmed that this problem becomes more pronounced as the gate length becomes shorter, and has been one of the major problems associated with the miniaturization of MO8F'ET.

Methods to prevent such channeling effects include: ■ Eliminate the orientation of the polycrystalline silicon that is the gate electrode; ■ Cover the gate electrode with resist to act as an injection stopper.
Possible countermeasures include lowering the acceleration voltage for ion implantation. However, 1. Technically complex problems remain (advanced control is required during the deposition of polycrystalline silicon, and it is difficult to maintain the amorphous state because it undergoes high-temperature heat treatment during the process from deposition to before ion implantation); 2. 3. With the miniaturization of devices, it is difficult to accurately form resists on small gate electrodes (mask misalignment has a large effect on device characteristics); 3. Although it is easy to realize, it is necessary to check the resistance of the injection part and leakage, and although the probability of occurrence is reduced, it seems impossible to completely eliminate it, and other problems remain.

The present invention has been made in view of the above-mentioned problems, and aims to prevent implanted ions from entering the gate electrode using a conductive amorphous thin film or oxide film formed on the gate electrode. An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent deterioration of characteristics of an element.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses a method of coating a conductive amorphous thin film or oxide film on the gate electrode during ion implantation when forming an LDD structure. It is.

Effect of the present invention In accordance with the method described above, accelerated ions are implanted into the source/drain region, but are not implanted into the gate electrode at all. The knock-on phenomenon can also be prevented, and ideal MOS LDSI element characteristics having an LDD structure can be obtained.

Embodiment FIGS. 1(a) to 1(g) show process flow diagrams according to a first embodiment of the present invention. As shown in FIG. 1(a), a P-well 2 in which NMO8 is formed on a silicon substrate 1 and a PM
An N well 3 in which O8 is formed is provided. Each element has 5
They are separated by a thick field oxide film 4 of about 0.00 nm. After forming a thin gate oxide film (10 nm to 25 nm) 5, polycrystalline silicon doped with impurities at a high concentration is deposited to a thickness of 30 nm and etched to form a gate electrode 8. Next, as shown in FIG. 1(b), this step is one of the features of the present invention, and a conductive amorphous thin film or oxide film (about 10 nm to 20 nm) 7 is formed on the entire surface of the substrate. Forms a stopper during ion implantation. The advantage of using an oxide film as a stopper is that the formation process is simple. The advantage of using a conductive amorphous thin film (for example, tungsten silicide or titanium silicide) as a stopper is that if an insulating material is used as a stopper, if the stopper film is When the thickness is different, the film thickness at the time of contact opening is different, so there is a problem that the contact will not open due to insufficient contact etching, and if contact etching is performed too much to prevent the above, problems such as junction leakage may occur. growing. However, when a conductive amorphous thin film is used as a stopper, even if the thickness of the stopper on the gate electrode and the source/drain region is different and insufficient contact etching occurs, the contact will not open because the stopper is conductive. Things don't happen. Next, as shown in FIG. 1(C), the N well 3 side is covered with a resist pattern 8, and phosphorus is ion-implanted (
Accelerating voltage 40 K e V, injection amount 1-3E 13
/am'') 1. The n-layer 9 is formed so that the surface concentration is approximately ˜IE18/cm''. At this time, the gate electrode on the NMO8 side is covered with a stopper, so the NM
No penetration of phosphorus into the OS gate electrode 5 occurs.

(The LDD structure of PMO8 is not specifically described here, but the LDD structure of PMO8 is not described here, but it is
Needless to say, it may be created before forming the No. 8 LDD structure. ) Next, a conductive amorphous thin film or oxide film 7, which is one of the features of the present invention, is formed on the entire surface of the substrate.
remove. Next, a 150% CVD5iOa film is applied to the entire surface of the substrate.
After depositing a thickness of 0.15 μm to 250 nm, anisotropic etching is performed, that is, etching the CVD 5iO* deposited film thickness only in the vertical direction to form a layer of 0.15 μm-0 on the side surface of the gate electrode 6.
When the sidewall 10 with a width of 25 μm is formed, as shown in FIG.
d).

Next, as shown in FIG. 1(e), this step is also one of the features of the present invention, and a conductive amorphous thin film or oxide film (approximately 10 nm to 20 nm) 11 is formed on the entire surface of the substrate. Form a stopper during ion implantation (same as above). Next, as shown in FIG. 1(f), the P-well 2 side is covered with a resist pattern 12, and BF2 is ion-implanted (acceleration voltage: 40
K e V.

Injection amount 3E 15/cm”)l, source of PMO8
A drain region 13 is formed. Next, as shown in FIG. 1(g), the N well 3 side is covered with a resist pattern 14, and arsenic (80KeV18E15/am") is implanted to form NMO8.
Source/drain regions 15 are formed. Here, an example was shown in which the source/drain regions are formed in the order of NMO81PMO8, but the source/drain regions are formed in the order of PMO8 and NMO8.
Needless to say, a drain region may also be formed.

When source/drain regions are formed in this way,
Since the stopper is formed on the gate electrode, it is possible to prevent gate electrode channeling due to ion implantation, and also to prevent knock-on of impurities in the gate Po1y-8i due to ion implantation.

FIGS. 2(a) to 2(g) show process flow diagrams according to a second embodiment of the present invention. The process up to the formation of the sidewall 10 is the same as that shown in FIG.

Next, as shown in FIG. 2(e), the P well 2 side is covered with a resist pattern 12, and BF2 is ion-implanted (acceleration voltage 40 K e V, implantation amount 3E15/cm") L
Source/drain regions 13 of PMO 8 are formed. Next, as shown in FIG. 2(f), this step is one of the characteristics of the present invention, and a conductive amorphous thin film or oxide film (about 10 nm to 20 nm) 11 is formed on the entire surface of the substrate. Form a stopper during ion implantation (same as above).

Next, as shown in FIG. 2(g), the N well 3 side is covered with a resist pattern 14, and arsenic (80K e V18E15
/cm”) into the source/drain region 1 of NMO8.
form 5. When the NMOS source/drain regions are formed using this method, since a stopper is formed on the gate electrode of NMO8, channeling of arsenic to the gate electrode can be prevented, and furthermore, the gate electrode channeling of arsenic can be prevented.

Knock-on of impurities in 1l-8t can also be prevented.

In this example, a double-well type 0MO8 structure was used, but a single-well type 0MO8 structure was used, such as an N-well using a P-type silicon substrate and a P-well using an N-type silicon substrate i.
It may be. Furthermore, in the above description, the gate electrode 6 may have a silicide structure or a metal gate instead of polycrystalline silicon. Further, although the above explanation uses a silicon substrate, it goes without saying that a compound semiconductor substrate such as GaAs may also be used.

Note that although the above embodiment has a 0MO8 structure, the present invention is not limited to this and can be applied to any FET structure other than the 0MO8 structure.

Effects of the Invention As is clear from the above description, the present invention eliminates the channeling effect of ion implantation or impurities in the gate electrode due to ion implantation by covering the gate electrode with a conductive amorphous thin film or oxide film. Since the knock-on phenomenon is prevented, there is no deterioration of device characteristics. Moreover, it has become possible with a very simple method without requiring any new steps.

[Brief explanation of drawings]

Figures 1(a) to (g) are cross-sectional views of the process flow of a 0MO8) transistor in the first embodiment of the present invention, and Figures 2(a) to (g) are the second embodiment of the present invention. CMO in
S) Process flow cross-sectional diagram of transistor, Figure 3 (a)
~(e) is a cross-sectional diagram of the conventional process flow, and FIG. 4(a)
is an IDD-VG characteristic diagram showing the hump phenomenon of an NMO8) transistor created using a conventional process flow.
Figure (b) shows the NM created using the conventional process flow.
O8) is a normal IDD-VG characteristic diagram of a transistor. 1...Silicon Mitt, 2...P well, 3...
- N well, 4... Field oxide film, 5... Gate oxide film, 6... Gate electrode, 7.11... Conductive amorphous thin film or oxide film, 8.12. 14...Resist pattern, 9...n'' layer, 10...Side wall, 13...P◆ layer, 15...n0 layer. Name of agent: Patent attorney Shigetaka Awano Figure Figure Figure 1 size C'J Figure

Claims (2)

[Claims] (1) forming a gate oxide film on the semiconductor substrate;
forming a gate electrode on the gate oxide film; forming a first film made of a conductive amorphous thin film or oxide film on the gate electrode; and forming an LDD structure on the substrate by ion implantation. a step of forming a sidewall around the gate electrode; and a second coating made of a conductive amorphous thin film or an oxide film on the gate electrode. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a source/drain region in the substrate by ion implantation. (2) forming a gate oxide film on the semiconductor substrate;
forming a gate electrode on the gate oxide film; forming a first film made of a conductive amorphous thin film or oxide film on the gate electrode and on the wafer surface; and forming a first film on the substrate by ion implantation. a step of forming an LDD structure; a step of removing the first film; a step of forming sidewalls around the gate electrode; and a step of forming source/drain regions of a PMOS transistor by ion implantation.
The method comprises the steps of forming a second film made of a conductive amorphous thin film or oxide film on the gate electrode, and forming source and drain regions of the NMOS transistor on the substrate by ion implantation. A method for manufacturing a semiconductor device, characterized by: