JPH02247752A - Information processor - Google Patents

Abstract

PURPOSE:To suppress the regeneration of a memory error by providing an information processor with an address conversion table allocating real addresses corresponding to virtual addresses, a register for holding the real addresses, an error information storing part, and a comparator. CONSTITUTION:In the case of forming the address conversion table 2, a virtual address is applied to the table 2 and its corresponding real address is read out, inputted to the comparator 4 through the register 1 and compared with error information (address) read out from the error information storing part 3. When both the addresses are equal, a coincidence signal for informing that the formation of the table 2 is abnormally ended is outputted from the comparator 4. Thereby, processing for allocating the virtual address to another real memory is executed and the real memory from which an once correctable or uncorrectable error is detected is inhibited from being used later. Since the reallocation of the address to the real memory from which the memory error is once detected is inhibited, the regeneration of a memory error is suppressed and the reliability of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an information processing device that is equipped with a memory check means and is capable of controlling a virtual storage method, and the present invention relates to an information processing device that is equipped with a memory check means and is capable of controlling a virtual storage method, and when a correctable or uncorrectable error is detected, virtual address allocation is performed. Attachment is intended to prevent memory errors from occurring again by notifying abnormal termination and assigning other real addresses, and is configured to be rewritable, and includes an address translation table in which real addresses are assigned to virtual addresses, and an address translation table in which real addresses are assigned to virtual addresses. A register that holds the real address corresponding to the virtual address read from the table; an error information storage unit that stores the error address when a correctable or uncorrectable error is detected; and a register. The actual address specified by the actual address is compared with the error address stored in the error information storage section, and when they match, a comparison circuit is provided that outputs a match signal.

[Industrial Field of Application] The present invention relates to an improvement in an information processing apparatus controlled by a virtual storage system, which is provided with means for checking the normality of data from a memory.

In recent years, computer systems have come to play an important role in society, and there is a demand for improved reliability of computer systems. For this reason, automatic data correction functions and uncorrectable error detection functions are provided, but
If an uncorrectable error occurs in data from memory, the system may stop, so it is necessary to prevent memory errors from occurring as much as possible.

[Prior Art] FIG. 3 shows an example of the configuration of main parts of a conventional information processing apparatus that employs a virtual storage method and has a function of checking the normality of data from memory. In the figure, 20 is a virtual memory, 30 is an address translation table, and 40 is a real memory. The address conversion table 30 is a table in which real addresses are assigned to virtual addresses, and the assignment is created by a processor (operating system) not shown. In the case shown, the starting address A of block M in real memory is virtual address a1, block N in real memory.
The starting address B of block 1 of the real memory block 1 is allocated to the virtual address b1, and the starting address C of block 1 of the real memory is allocated to the virtual address C, respectively.

In such a processing device, the real memory 40 is divided into blocks (block 0, block 1, . . . block N), and a virtual address is assigned to each block, so that the real memory 40 is divided into block units (block 0, block 1, ... block N), and a virtual address is assigned to each block. Memory is managed so that there is only the size indicated by the virtual address.

[Problems to be Solved by the Invention] However, in such conventional information processing devices, even if a correctable error or an uncorrectable error is detected in a certain real memory block, the system cannot operate. Otherwise, a virtual address will be allocated to that memory again. Therefore, for example, even if a correctable error is once detected, a virtual address is allocated and used again, which causes a problem that the error develops into an uncorrectable error and the system stops.

The present invention has been made in view of the above problem, and for memory in which a correctable or uncorrectable error has been detected, virtual address allocation sometimes notifies abnormal termination and disables other implementations. It is an object of the present invention to provide an information processing device that can prevent memory errors from occurring again by assigning addresses.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a register that holds a virtual address for converting a virtual address to a real address, and also holds a real address corresponding to the virtual address read from the address conversion table 2. The address translation table 2 is a table that is configured to be rewritable and has real addresses assigned to virtual addresses.

3 is for storing error information (error address) when a correctable or uncorrectable error is detected (the detection is performed by well-known means and illustrations and explanations are omitted here). This is an error information storage section.

Reference numeral 4 denotes a comparison circuit that compares the specified real address and the error address in the error information storage section, and when they match, outputs a match signal indicating that the creation of the address conversion table has ended abnormally.

[Operation] In such a configuration, when creating the address conversion table 2, a virtual address is given to the address conversion table 2, the corresponding real address is read out and taken into the register 1, and this is input to the comparison circuit 4. Error information storage section 3
Compare with the error information (address) of If the two addresses match, the comparison circuit outputs a match signal to notify that the creation of the address conversion table has ended abnormally.

Therefore, when a match signal is output, that is, when it is notified that address translation table creation has ended abnormally, the virtual address is allocated to another real memory, and once a correctable or uncorrectable error is detected. The real memory that has been deleted can be made unusable after that to prevent the memory error from occurring again.

[Example 2] FIG. 2 is a block diagram of one embodiment of the present invention. In the figure,
Components equivalent to those in FIG. 1 are given the same reference numerals. 10 is the first
This processor includes the register 1 shown in the figure, and also has functions such as creating an address translation table. 5 checks whether there is a correctable or uncorrectable error when reading the address on the real memory 6, and if there is an error, outputs the error address of the real address to the error information storage unit 3. It is a circuit.

In such a configuration, for example, when address K on the real memory 6 is read and the check circuit 3 detects a correctable or uncorrectable error, the block number on the real memory 6 is recorded as error information. The error information is stored in the error information storage section 3.

Next, when the processor 10 allocates an address conversion table, the specified real address and the error address in the error information storage section 3 are compared in the comparison circuit 4, and if the two addresses match, the processor 10 will be notified.

The processor 10 learns from this notification that the creation of the address translation table has ended abnormally, and allocates the virtual address to a different real address. As a result, the real address is no longer used, and it is possible to prevent a memory error from occurring again in the same block.

In the above embodiment, the comparison circuit is provided as hardware, but it is also possible to prepare it as a microprogram or software and achieve the same function.

[Effects of the Invention] As explained above, according to the present invention, addresses are not allocated again to real memory where a memory error has been detected once, so recurrence of memory errors can be suppressed, and the system reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a configuration diagram of main parts showing an example of a conventional information processing device. 1 and 2, 1 is a register, 2 is an address conversion table, 3 is an error information storage section, 4 is a comparison circuit, 5 is a check circuit, and 6 is a real memory.

Claims (1)

[Scope of Claims] In an information processing device controlled by a virtual memory method that is equipped with means for checking the normality of data from memory, an address conversion device configured to be rewritable and in which a real address is assigned to a virtual address. a table (2), and a register (1) that holds a real address corresponding to the virtual address read from the address conversion table (2) for converting a virtual address to a real address.
and an error information storage unit (3) for storing the error address when a correctable or uncorrectable error is detected; and a real address specified by the register (1) and the error information. A comparison circuit (4) which compares the error address stored in the storage unit (3) and outputs a match signal indicating that the creation of the address conversion table has ended abnormally when they match.
), and when a match signal is output from the comparison circuit (4) when creating the address conversion table, the virtual address is not assigned to the real address, and the real address is reallocated to a different real address. An information processing apparatus characterized in that a real memory in which a correctable or uncorrectable error has once been detected cannot be used thereafter, thereby preventing recurrence of a memory error.