JPH09106693A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device having a continuously usable constitution, which can surely avoid the use of the generated defective memory cell without decreasing the processing capability. SOLUTION: In the semiconductor memory device having an MPU 107 and a main memory 108, a defect correcting memory having an address memory 101, an address comparator 102, an address register flag 103 and a data memory 104 is further provided. When a defective cell has occurred in the main memory 108, address registration for replacing the defective cell with the data memory cell of the data memory 104 is performed by the address memory 101 and the address register flag 103. In this constitution, the AND output of two outputs of the address comparator 102 and the address register flag 103 is required in writing/reading to and from the data memory cell. Therefore, the writing/ reading to and from the data cell can be surely performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a defective relief memory used when a defective memory cell occurs in a main memory.

[0002]

2. Description of the Related Art A computer is composed of various constituent elements, of which the main constituent element is a main memory (main memory). The main memory is
CPU (Central Processing Un
it) or MPU (Microprocessor)
Unit) and can directly access (write / read) by directly specifying an address set in the main memory by the CPU or MPU.

FIG. 3 is an explanatory diagram outlining the operation of a conventional semiconductor memory device. CPU (Central
Processing Unit) or MPU (Mi
When an address signal is transmitted from the processor unit 301 via the address line 304,
A cell at an address in the main memory 302 is designated according to the address signal, and data is transmitted / received through the data bus 305, whereby the designated cell can be written / read.

A cell in the main memory 302 may be defective due to damage or the like. In such a case, normal writing / reading to / from the defective memory cell (or block) 303 is performed. Can't do it.

Conventionally, as a countermeasure against a defective memory cell occurring when the main memory has no redundant configuration or has a redundant configuration but is fully used, that is, when the redundant configuration cannot be used. The main measure is to detect an error code caused by a defective memory cell by a parity check, or ECC (error correction code;
By correcting the error code caused by the defective memory cell by using Error Correcting Code or avoiding the use of the defective memory cell corresponding to the detected error code, the error caused by the defective memory cell can be avoided by software means. is there.

The ECC is an error detection code set so as to be able to automatically correct a certain kind of error, and is a redundant code added to correct an error in data, for example, in data transmission. By adding the ECC to the data to be transmitted in advance, the data in which an error has occurred is specified in bit units, detected, and automatically corrected. On this occasion,
The defective memory cell that caused the error can also be identified.

On the other hand, in the parity check, an extra 1 bit (parity bit) is added to the binary code so that the sum of the bits calculated including this is an odd number (or even number), If the sum of the bits is an even number (or an odd number) at the time of checking, it is determined that an error has occurred in the binary code.

In order to avoid an error caused by a defective memory cell by hardware means, not by software means, the memory card including the defective cell, the memory module, or the entire main memory is replaced. In some cases, measures to do so may be taken.

[0009]

However, the above-mentioned means for avoiding an error caused by a defective memory cell has the following problems.

In a system using ECC, an error correction process is performed on an error code every time an error code caused by the defective memory cell occurs. Therefore, when selecting a block including the defective memory cell, As the correction process is performed, the number of processing cycles is increased as compared with the normal operation, and therefore, extra time is required and the processing capability is reduced.

Further, although an error can be detected by the parity check, it is not possible to specify which code in the data in which the error has occurred has an error. Therefore, it is necessary to correct the error. I can't.

Further, when the memory card including the defective cell, the memory module, or the entire main memory is replaced, the use of the device is stopped during the time for replacement of the relevant parts and maintenance of the device. However, as a result, various inconveniences may occur.

The present invention has been made in view of the above problems, and an object thereof is to reliably use a defective memory cell generated in a main memory in which a redundant configuration cannot be used, without deteriorating the processing capacity of a semiconductor memory device. Another object of the present invention is to provide a semiconductor memory device having a configuration that can be avoided and can be continuously used.

[0014]

According to the semiconductor memory device of the present invention, a main memory device for writing / reading data to / from a memory cell in a memory block corresponding to a designated address, and a main memory device A processing / control device that generates an address signal that specifies the address of the memory cell and a write / read signal that writes / reads data to / from the memory cell corresponding to the specified address, and any memory in the main memory device When a defective memory cell occurs in a cell, a defective memory cell identifying means for identifying the address of the defective memory cell, and when the defective memory cell occurs, it is possible to functionally replace the defective memory cell in a cell unit, A usable address other than the address set for each memory cell in the main memory in the processing / control device is set for each cell. A data memory composed of one or more data memory cells and a number of address memory cells corresponding to the data memory cells, and each data memory cell is replaced in order to replace the defective memory cell with the data memory cell. Of each address memory cell provided by
Each address memory has an address memory in which the address of the defective memory cell is registered in the address memory corresponding to the data memory cell to replace the defective memory cell, and an address registration flag memory cell of the number corresponding to the data memory cell and the address memory. An address registration flag memory for flagging the address registration flag memory cell corresponding to the address memory cell in which the address of the defective memory cell is registered among the address registration flag memory cells provided corresponding to the cells When a defective memory cell occurs in the main memory device in which the redundant configuration cannot be used, the address of the defective memory cell is registered by the address memory and the address registration flag memory, and the defective memory cell is processed as a normal memory cell. I replaced it with a bad memory Since it is not necessary to perform error correction processing on the error code each time it occurs due to the error, the smooth operation is ensured and the deterioration of the processing capacity is prevented, and the replacement of parts and the maintenance of the device are performed. It is possible to significantly reduce the time required to perform the write operation, and write / read can be surely performed to a normal memory cell.

When the address of the defective memory cell is registered in the address memory, the address designation of the address memory cell forming the address memory and the address designation of the address registration flag memory cell forming the address registration flag memory are performed by the processing / control device. Since it is performed by an address other than the address assigned to the address space of the main memory in the above, it is not necessary to additionally provide means for only this address designation.

A main memory for writing / reading data to / from a memory cell in a memory block corresponding to a designated address, an address signal for designating an address of the memory cell in the main memory, and a designated address are provided. A processing / control device that generates a write / read signal for writing / reading data to / from a memory cell and an address of the defective memory cell when a defective memory cell occurs in any of the memory cells in the main memory device. Defective memory cell specifying means for specifying, a data memory including one or more data memory cells capable of functionally replacing the defective memory cells in a cell unit when a defective memory cell occurs, and a number corresponding to the data memory cells Address memory cells for replacing defective memory cells and data memory cells. The address memory in which the address of the defective memory cell is registered in the address memory corresponding to the data memory cell that replaces the defective memory cell among the address memory cells provided corresponding to An address registration flag memory cell corresponding to the address memory cell in which the address of the defective memory cell is registered among the address registration flag memory cells provided corresponding to each address memory cell Address registration flag memory that is flagged in the address memory, and when registering the address of the defective memory cell in the address memory, the address designation of the address memory cell that constitutes the address memory and the address registration flag memory cell that constitutes the address registration flag memory Addressing When a defective memory cell occurs in the main memory device that cannot use a redundant configuration, the address of the defective memory cell is registered by the address memory and the address registration flag memory. Since the defective memory cell is replaced with a normal memory cell, it is not necessary to perform error correction processing on the code each time an error code caused by the defective memory cell occurs, so that a smooth operation is ensured. The processing time can be prevented from lowering, the time required for parts replacement and device maintenance can be greatly reduced, and writing / reading can be surely performed to normal memory cells. . Further, by inputting a control signal from the processing / control device to the address memory select counter provided on the defect relief memory, the address designation on the address memory and the address registration flag memory on the defect relief memory at the time of address registration is performed. Therefore, it is not necessary to connect the data bus to the address memory, and the number of terminals on the substrate can be reduced.

Since the output value of the address memory select counter is controlled by the control signal from the processing / control device, it is not necessary to further provide this control signal generating means.

In writing / reading, when a predetermined address signal designating the same address as the address registered for replacement is designated, it is designated as the registered address according to the input of the predetermined address signal. The match output from the address comparator that indicates a match with the registered address and the registration confirmation output from the address registration flag memory that confirms that the flag indicating that the registered address has been registered are set. One side and the other side input A
Since the coincidence confirmation output of the ND gate is used as the data memory output command signal, it is possible to reliably write / read to / from the data memory cell replaced with the defective memory cell.

Since the coincidence confirmation output is further used as the main memory output interrupt prohibition signal, when the data memory cell replaced with the defective memory cell is written / read, the main memory erroneously outputs. No writing / reading is performed on the defective memory cell.

Since the replacement of the defective memory cell with the data memory cell can be performed in a block unit, it is possible to omit the labor for replacement when a plurality of defective memory cells occur.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor memory device according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram of a configuration of a first embodiment of a semiconductor memory device according to the present invention. Compared with the conventional configuration, the difference is that a defect relief memory 100 is provided in addition to the MPU 107 and the main memory 108. The address on the defect relief memory 100 is
A memory 101, an address comparator 102, an address registration flag memory 103, and a data memory 104 are provided. The MPU 107 and the main memory 108 are connected to each other by a data bus 110, and the address memory 101 and the data memory 104 are further connected to the data bus 110. The MPU 107 and the main memory 108 are also connected to each other by an address line 109.
An address memory 101 and an address comparator 102 are connected to. The signal outputs 106 from the address comparator 102 and the address registration flag memory 103 are input to one side input and the other side input of the AND gate, respectively, and the signal output 106 of the AND gate is input to the data memory 104 and the main memory 108. Also, MPU10
A write / read signal 10 that specifies whether to write or read the cell addressed by 7.
5 is an address memory 10 in addition to the main memory 108.
1, address registration flag memory 103, data memory 1
It is also input to 04.

If there are n cells forming the address memory 101, the address registration flag memory 103, and the data memory 104, the n cells are stored in the address space of the main memory 108 in the MPU 107. Addresses other than the addresses assigned to them, that is, unused addresses in the MPU 107 are assigned. For example, MP
The assignable address in U107 is m + from address 1.
If there are up to n addresses, of which the addresses allocated in the address space of the main memory 108 are from address 1 to address m−1, address m to m + n
Addresses up to the address are assigned to each of the above n cells.

The main memory 108 in the main memory 108 is inspected for good or defective by, for example, the above-mentioned ECC or the like.
Here, when the defective memory cell is found and specified, the defective memory cell is replaced with the data memory cell in the data memory 104.

In the configuration of the first embodiment shown in FIG. 1, the address designation of the address memory cells constituting the address memory 101 on the defect relief memory 100 and the address registration flag memory cells constituting the address registration flag memory 103 are performed. By performing addressing from the address line 109 and address registration from the data bus 110, the defective memory cell is replaced with the data memory cell in the data memory 104.

First, an address m other than the address assigned in the address space of the main memory 108 is input by the MPU 107 to the address memory 101 and the address registration flag memory 103 via the address line 109, and the address memory 101 stores the address m. Address m address memory cell and address registration flag memory 103
The address m address registration flag memory cell in the inside is designated respectively.

In response to this designation, it is confirmed whether or not the flag is already set in the m-address registration flag memory cell. If the flag has already been set, another address, for example, m + 1 address is designated again. m-address address registration flag When the flag is not set in the memory cell, the address of the defective memory cell is registered in the m-address memory cell in the address memory 101 from the MPU 107 via the data bus 110, and the m-address registration is performed. A flag indicating that the m-th address memory cell in the address memory 101 has been registered is set in the flag memory cell.

Assuming that the address memory 101, the address registration flag memory 103, and the data memory 104 each have n cells, by repeating the above procedure, the addresses of up to n defective memory cells are registered,
The defective memory cell can be replaced by the data memory cell in the data memory 104.

Writing / reading to / from the m-address data memory cell replaced with the defective memory cell as described above is performed as follows.

The address signal input from the MPU 107 is always input in parallel to the main memory 108 and the defect relief memory 100 via the address line 109, and is registered in the address memory 101 by the address comparator 102. The address of one or a plurality of defective memory cells present is compared with the address input from the MPU 107.

When the address of the defective memory cell registered in the address m memory cell and the address input from the MPU 107 match as a result of comparison, and the address m address registration flag memory cell is flagged. Is used for writing / reading of the data memory cell at the address m. At this time, the write / read operation is performed by a signal common to the write / read signal 105 for the main memory 108. The signal from the address comparator 102 and the AND gate from the address registration flag memory 103 is input to the main memory 108 as the main memory output interrupt prohibition signal 106, and the data is output from the main memory 108 to the data bus 110. Is prohibited and the data from the data memory 104 is output to the data bus 110.

However, even if the addresses compared by the address comparator 102 match, if the address address registration flag memory cell is not flagged, the address main memory cell of the main memory 108 is read / written. Then, the data from the main memory 108 is output to the data bus 110. If the initial value of the address of the address memory 101 matches, the main memory 10 is originally
This is to prevent erroneous writing / reading to / from the data memory 104 where writing / reading should be performed on the memory.

In the first embodiment described above, an address other than the address assigned to the address space of the main memory 108 in the MPU 107, that is, an unused address in the MPU 107 is used to generate an address. Since the address memory 101 and the address registration flag memory 103 on the defect relief memory 100 are designated at the time of registration,
This has the advantage that no additional means only for this addressing need be provided.

FIG. 2 is an explanatory diagram of the configuration of the second embodiment of the semiconductor memory device according to the present invention. Similar to the first embodiment, the defect relief memory 200 is provided in addition to the MPU 209 and the main memory 210. On the defect relief memory 200, an address memory 201,
Address comparator 202 and address registration flag memory 2
03, a data memory 204, and an address memory select counter 207. MPU20
9 and the main memory 210 are connected to each other by a data bus 110, and a data memory 204 is further connected to the data bus 110. In addition, MPU20
9 and the main memory 210 are also connected to each other by an address line 211.
11 includes an address memory 201 and an address comparator 202.
And are connected. The signal output 206 from the address comparator 202 and the address registration flag memory 203 is an AN.
Input to one side and the other side input of the D gate,
The signal output 206 of the AND gate is the data memory 20.
4 and the main memory 210. Also, MPU
The write / read signal 205 for specifying whether to write or read the cell addressed by 209 is used in addition to the main memory 210 and the data memory 20.
4 is also input.

The main difference in configuration compared with the first embodiment is that an address memory select counter 207 is provided on the defect relief memory 200, and the address memory select counter 207 receives a control signal 208 from the MPU 209. Is the point that is entered. Therefore, the data bus 212 is not connected to the address memory.

When it is assumed that the number of cells forming the address memory 201, the address registration flag memory 203, and the data memory 204 is n, for each of these n cells, for example, from address m to address m + n. It is assumed that each address is assigned. In the second embodiment, the address designation for the address memory 201 and the address registration flag memory 203 on the defect relief memory 200 at the time of address registration is performed by the control signal 208 from the MPU 209 on the defect relief memory 200 as described later. Address memory select counter 2
Since it is carried out by inputting the data into the address 07, unlike the first embodiment, the address assigned to each cell of the data memory 204 is irrelevant to the address assignment to the address space of the main memory 210 in the MPU 209.

In the same manner as in the first embodiment, the inspection of the main memory cells in the main memory 210 is performed by the above-mentioned ECC or the like, and the defective memory cells are found and specified, as in the first embodiment. Then, the defective memory cell is replaced by the data memory cell in the data memory 204.

In the configuration of the second embodiment shown in FIG. 2, as described above, the address designation of the address memory cells and the address registration flag memory constituting the address memory 201 on the defect relief memory 200 at the time of address registration. Addressing of the address registration flag memory cells that make up the 203 is performed by the MPU 209 as described below.
By inputting the control signal 208 from the address memory select counter 207 on the defect relief memory 200.

First, a predetermined control signal 208 is input from the MPU 209 to the address memory select counter 207 on the defect relief memory 200, and the address memory select counter 207 takes the mth value. The address m address memory cell in the address memory 201 and the address m address registration flag memory cell in the address registration flag memory 203 are selected according to the counter value of the address memory select counter 207.

In this case, since the counter value of the address memory select counter 207 is automatically incremented, the selected m-address address registration flag memory cell is never flagged. Therefore, it is not necessary to confirm whether the flag is set or not.
The address of the defective memory cell is registered in the m-address memory cell in the address memory 201 from the U209 via the address line 211, and the m-address memory cell in the address memory 201 is registered in the m-address registration flag memory cell. Set a flag to indicate that it has been completed.

Assuming that the address memory 201, the address registration flag memory 203, and the data memory 204 each have n cells, by repeating the above procedure, the addresses of up to n defective memory cells are registered,
The defective memory cell can be replaced by the data memory cell in the data memory 204.

Writing / reading to / from the m-th address data memory cell replaced with the defective memory cell as described above is performed as follows, as in the first embodiment.

The address signal input from the MPU 209 is always input in parallel to the main memory 210 and the defect relief memory 200 via the address line 211, and is registered in the address memory 201 by the address comparator 202. The address of one or a plurality of defective memory cells present is compared with the address input from the MPU 209.

When the address of the defective memory cell registered in the address m memory cell and the address input from the MPU 209 match as a result of comparison, and the address m address register flag memory cell is flagged. Is used for writing / reading of the data memory cell at the address m. At this time, the write / read operation is performed by a signal common to the write / read signal 205 for the main memory 210. The signal from the address comparator 202 and the AND gate from the address registration flag memory 203 is input to the main memory 210 as a main memory output interrupt prohibition signal 206, and the data output from the main memory 210 to the data bus 212 is performed. Is prohibited and the data from the data memory 204 is output to the data bus 212.

However, even if the addresses compared by the address comparator 202 match, if the address address registration flag memory cell is not flagged, the address main memory cell of the main memory 210 is read / written. Then, the data from the main memory 210 is output to the data bus 212. When the initial value of the address in the address memory 201 matches, the main memory 21 is originally
This is to prevent writing / reading to / from the data memory 204 by mistake when writing / reading to / from 0.

In the second embodiment described above, the control signal 208 is sent from the MPU 209 to the address memory select counter provided on the defect relief memory 200.
By inputting, the address is specified for the address memory 201 and the address registration flag memory 203 on the defect relief memory 200 at the time of address registration. Therefore, it is not necessary to connect the data bus 212 to the address memory 201, and It has an advantage that the number of terminals is small.

[0047]

As described above, according to the semiconductor memory device of the present invention, when a defective memory cell occurs in a main memory device (main memory) in which a redundant configuration cannot be used, the defective memory cell Address registration is performed by two means (address memory and address registration flag memory) and the defective memory cell is replaced with a normal memory cell. Therefore, every time an error code caused by the defective memory cell occurs, Since it is not necessary to perform error correction processing, it is possible to ensure a smooth operation and prevent a decrease in processing capacity, and it is possible to greatly reduce the time required for parts replacement and device maintenance. writing/
Reading can also be surely performed on a normal memory cell.

In addition, in the first configuration, an address other than the address assigned to the address space of the main memory in the processing / control unit (MPU), that is, not used in the processing / control unit. Since the address is used to address the address memory and the address registration flag memory on the defect relief memory at the time of address registration, it is not necessary to additionally provide means only for this address specification.

In the second configuration, by inputting a control signal from the processing / control device to the address memory select counter provided on the defect relief memory, the address memory on the defect relief memory at the time of address registration. Since the address is designated to the address registration flag memory, it is not necessary to connect the data bus to the address memory, and the number of terminals on the substrate can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first configuration of a semiconductor memory device according to the present invention.

FIG. 2 is an explanatory diagram of a second configuration of the semiconductor memory device according to the present invention.

FIG. 3 is a schematic explanatory diagram of a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

 100, 200 defect relief memory 101, 201 address memory 102, 202 address comparator 103, 203 address registration flag memory 104, 204 data memory 105, 205 write / read signal 106, 206 main memory output interrupt inhibit signal 107, 209, 301 MPU (processing / control device) 108, 210, 302 Main memory (main memory device) 109, 211, 304 Address line 110, 212, 305 Data bus 207 Address memory select counter 208 Control signal 303 Bad memory cell

Claims (7)

[Claims] 1. A main memory device for writing / reading data to / from a memory cell in a memory block corresponding to a specified address; an address signal for specifying an address of the memory cell in the main memory device; Write / read data to / from the memory cell corresponding to the address
A processing / control device that generates a read signal; and a defective memory cell identification unit that identifies an address of the defective memory cell when a defective memory cell occurs in any one of the memory cells in the main memory device, When the defective memory cell occurs, it can be functionally replaced with the defective memory cell on a cell-by-cell basis, and an address set in the processing / control device in correspondence with each memory cell in the main memory device. A memory having one or more data memory cells having usable addresses other than those set for each cell; and a number of address memory cells corresponding to the data memory cells, the defective memory cells and the data Of the address memory cells provided corresponding to the data memory cells to replace the memory cells, the defective memory An address memory in which the address of the defective memory cell is registered in the address memory corresponding to the data memory cell to be replaced with a cell; and an address registration flag memory cell in a number corresponding to the data memory cell and the address memory, Of the address registration flag memory cells provided corresponding to the address memory cells, an address registration flag memory cell corresponding to the address memory cell in which the address of the defective memory cell is registered is registered. A semiconductor memory device comprising a flag memory. 2. The semiconductor memory device according to claim 1, wherein when the address of the defective memory cell is registered in the address memory, the address designation of the address memory cell forming the address memory and the address registration flag. The semiconductor memory device according to claim 1, wherein addressing of the address registration flag memory cell forming the memory is performed by an address other than an address assigned to an address space of a main memory in the processing / control device. 3. A main memory device for writing / reading data to / from a memory cell in a memory block corresponding to a specified address; an address signal for specifying an address of the memory cell in the main memory device; Write / read data to / from the memory cell corresponding to the address
A processing / control device that generates a read signal; and a defective memory cell identification unit that identifies an address of the defective memory cell when a defective memory cell occurs in any one of the memory cells in the main memory device, When the defective memory cell occurs, a data memory including one or more data memory cells that can be functionally replaced with the defective memory cell on a cell-by-cell basis, and a number of address memory cells corresponding to the data memory cell are provided. Of the address memory cells provided to correspond to the data memory cells for replacing the defective memory cells with the data memory cells, the data memory cells to be replaced with the defective memory cells. An address memory in which the address of the defective memory cell is registered in the address memory; Address registration flag memory cells corresponding to the address memory and the address memory, and the address of the defective memory cell among the address registration flag memory cells provided corresponding to each address memory cell is registered. An address registration flag memory that flags an address registration flag memory cell corresponding to the address memory cell; and an address memory cell that configures the address memory when registering an address of the defective memory cell in the address memory. A semiconductor memory device, comprising: an address memory select counter for addressing and addressing the address registration flag memory cells forming the address registration flag memory. 4. The semiconductor memory device according to claim 3, wherein the output value of the address memory select counter is
A semiconductor memory device controlled by a control signal from the processing / control device. 5. The semiconductor memory device according to claim 1, wherein during writing / reading, a predetermined address signal designating the same address as the address registered for the replacement is designated. In this case, the coincidence output from the address comparator indicating the coincidence between the registered address and the designated address in response to the input of the predetermined address signal, and the registered address have already been registered. The registration confirmation output from the address registration flag memory indicating the confirmation that the flag indicating that is set is used as the data memory output command signal, the coincidence confirmation output of the AND gate having one side and the other side inputs. And semiconductor memory device. 6. The semiconductor memory device according to claim 5, wherein the coincidence confirmation output is further used as an output interrupt prohibition signal for the main memory device. 7. The semiconductor memory device according to claim 1, wherein the defective memory cell can be replaced with the data memory cell in block units.