JPH02247709A - スキユー除去方法 - Google Patents

スキユー除去方法

Info

Publication number
JPH02247709A
JPH02247709A JP2037531A JP3753190A JPH02247709A JP H02247709 A JPH02247709 A JP H02247709A JP 2037531 A JP2037531 A JP 2037531A JP 3753190 A JP3753190 A JP 3753190A JP H02247709 A JPH02247709 A JP H02247709A
Authority
JP
Japan
Prior art keywords
data
clock
register
control
synchronized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2037531A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0544043B2 (OSRAM
Inventor
Thomas B Smith
トーマス・バシイール・スミス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH02247709A publication Critical patent/JPH02247709A/ja
Publication of JPH0544043B2 publication Critical patent/JPH0544043B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G06F11/184—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components where the redundant components implement processing functionality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2037531A 1989-02-23 1990-02-20 スキユー除去方法 Granted JPH02247709A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/314,608 US5020023A (en) 1989-02-23 1989-02-23 Automatic vernier synchronization of skewed data streams
US314608 1989-02-23

Publications (2)

Publication Number Publication Date
JPH02247709A true JPH02247709A (ja) 1990-10-03
JPH0544043B2 JPH0544043B2 (OSRAM) 1993-07-05

Family

ID=23220639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2037531A Granted JPH02247709A (ja) 1989-02-23 1990-02-20 スキユー除去方法

Country Status (4)

Country Link
US (1) US5020023A (OSRAM)
EP (1) EP0384177B1 (OSRAM)
JP (1) JPH02247709A (OSRAM)
DE (1) DE69024829T2 (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002058316A1 (en) * 2001-01-17 2002-07-25 Sony Corporation Data time difference absorbing circuit, and data receving method and device

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US5504878A (en) * 1991-02-04 1996-04-02 International Business Machines Corporation Method and apparatus for synchronizing plural time-of-day (TOD) clocks with a central TOD reference over non-dedicated serial links using an on-time event (OTE) character
US5594927A (en) * 1992-01-09 1997-01-14 Digital Equipment Corporation Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits
US5533188A (en) * 1992-10-19 1996-07-02 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Fault-tolerant processing system
US5914953A (en) * 1992-12-17 1999-06-22 Tandem Computers, Inc. Network message routing using routing table information and supplemental enable information for deadlock prevention
US5399901A (en) * 1994-04-20 1995-03-21 General Instrument Corp. Semiconductor devices having a mesa structure and method of fabrication for improved surface voltage breakdown characteristics
US5664226A (en) * 1994-09-08 1997-09-02 International Business Machines Corporation System for merging plurality of atomic data elements into single synchronized file by assigning ouput rate to each channel in response to presentation time duration
US5854898A (en) 1995-02-24 1998-12-29 Apple Computer, Inc. System for automatically adding additional data stream to existing media connection between two end points upon exchange of notifying and confirmation messages therebetween
US5664164A (en) * 1995-02-24 1997-09-02 Apple Computer, Inc. Synchronization of one or more data streams
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US5940608A (en) * 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US6912680B1 (en) * 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US5926047A (en) * 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US5940609A (en) * 1997-08-29 1999-08-17 Micorn Technology, Inc. Synchronous clock generator including a false lock detector
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) * 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6690757B1 (en) * 2000-06-20 2004-02-10 Hewlett-Packard Development Company, L.P. High-speed interconnection adapter having automated lane de-skew
JP3417476B2 (ja) * 2000-09-06 2003-06-16 日本電気株式会社 多入力データ同期回路
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
DE502005006441D1 (de) * 2004-10-25 2009-02-26 Bosch Gmbh Robert Verfahren und vorrichtung zur modusumschaltung und zum signalvergleich bei einem rechnersystem mit wenigstens zwei verarbeitungseinheiten
JP4669007B2 (ja) * 2004-10-25 2011-04-13 ローベルト ボッシュ ゲゼルシャフト ミット ベシュレンクテル ハフツング 少なくとも２つの処理ユニットを有する計算機システムにおいて切替及びデータを比較する方法及び装置
EP1812859B1 (de) * 2004-10-25 2009-01-07 Robert Bosch Gmbh Verfahren und vorrichtung zur modusumschaltung und zum signalvergleich bei einem rechnersystem mit wenigstens zwei verarbeitungseinheiten
US8595554B2 (en) * 2009-11-13 2013-11-26 International Business Machines Corporation Reproducibility in a multiprocessor system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3812476A (en) * 1971-11-16 1974-05-21 Texas Instruments Inc Memory device
GB1454781A (en) * 1973-04-03 1976-11-03 Marconi Co Ltd Counter synchronization circuit
US4275457A (en) * 1977-05-18 1981-06-23 Martin Marietta Corporation Apparatus and method for receiving digital data at a first rate and outputting the data at a different rate
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus
FR2573888B1 (fr) * 1984-11-23 1987-01-16 Sintra Systeme pour la transmission simultanee de blocs de donnees ou de vecteurs entre une memoire et une ou plusieurs unites de traitement de donnees
US4733353A (en) * 1985-12-13 1988-03-22 General Electric Company Frame synchronization of multiply redundant computers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002058316A1 (en) * 2001-01-17 2002-07-25 Sony Corporation Data time difference absorbing circuit, and data receving method and device
US7342945B2 (en) 2001-01-17 2008-03-11 Sony Corporation Data time difference absorbing circuit and data receiving method and device

Also Published As

Publication number Publication date
JPH0544043B2 (OSRAM) 1993-07-05
DE69024829T2 (de) 1996-08-08
EP0384177A3 (en) 1991-09-11
EP0384177B1 (en) 1996-01-17
US5020023A (en) 1991-05-28
EP0384177A2 (en) 1990-08-29
DE69024829D1 (de) 1996-02-29

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