JPH02246435A - Bit multiplexing system - Google Patents

Abstract

PURPOSE:To cope with the revision in a data rate without revising the hardware by providing a bit setting timing generating means generating a timing signal corresponding to the prescribed bit location of a parallel signal in response to the inputted set information. CONSTITUTION:A bit location setting timing generating means 13 generates a timing signal corresponding to the prescribed bit location of a parallel signal in response to the inputted setting information. For example, in the case of applying bit multiplexing (at transmission) to a low speed data, a data control means 15 inserts a data to the prescribed time area of a serial signal in response to the timing signal outputted from the bit location setting timing generating means 13 and a serial/parallel conversion means 11 converts the serial signal into a parallel signal succeedingly. Thus, when the data rate is changed, it is coped flexibly with the addition or revision of the hardware.

Description

[Detailed Description of the Invention] [Summary] Regarding the bit multiplexing method used in time division multiplexing devices, the purpose of this invention is to adapt to changes in data rate without changing the hardware. In a time division multiplexing device that performs a bit position setting timing generating means for generating a timing signal corresponding to a predetermined bit position; and a time range corresponding to the timing signal;
and data control means for inserting and extracting data into and from the serial signal.

[Industrial application field]

The present invention relates to a bit multiplexing method used in a time division multiplexing device for multiplexing signals from devices with different transmission speeds, transmitting them all to a high-speed digital line, and vice versa.

[Conventional technology]

The bit multiplexing section of the time division multiplexer bit multiplexes a low-speed data signal into a predetermined bit position of a time slot, and also separates data bits from a predetermined bit position of a time slot and converts them into a low-speed data signal. processing is performed.

FIG. 5 is a block diagram showing an example of the configuration of a conventional bit multiplexing section.

In the figure, the bit multiplexing section indicated by the dashed line has an 8-bit configuration (bo, b, . . . ) shown in FIG. 6, for example.

a bit arrangement unit 51 for arranging data bits at predetermined bit positions of a time slot (N bps) of (by) or extracting data bits at a predetermined bit position;
It includes a data control section 53 that separates and combines data signals corresponding to each bit arrangement section.

That is, when the data rate is N/8 bps, as shown in FIG. 5(1), it is composed of one bit arrangement section 511 and a corresponding data control section 531. Further, when the data rate is 2N/8 bps, as shown in FIG. 5(2), two bit arrangement sections 511.51 perform different bit arrangements and a corresponding data control section 53. It is composed of

Generally, the data rate is M N / 8 bps (1
≦M≦8), as shown in FIG. 5(3), M bit allocation units 5L each perform a different bit allocation.
, 51g, . . . , 51M and the corresponding data control section 53. It is composed of

In this way, the conventional bit multiplexing section has a fixed hardware configuration depending on its data rate.

[Problem to be solved by the invention]

Therefore, in the conventional bit multiplexing section, it is difficult to respond flexibly to changes in the data rate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit multiplexing method that can respond to changes in data rate without changing hardware.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the serial/parallel converter 11 is configured to convert a serial signal into a parallel signal and transmit it, and convert the received parallel signal into a serial signal.

The focus position setting timing generating means 13 is configured to generate a timing signal corresponding to a predetermined bit position of the parallel signal in accordance with input setting information.

The data control means 15 is configured to insert and remove data from the serial signal in a time range according to this timing signal.

Data control means 15 inserts data into a predetermined time range of the serial signal. Subsequently, the serial/parallel conversion means 11
However, by converting this serial signal into an 8-bit parallel signal, data can be placed in a predetermined bit position of the parallel signal (time slot) and converted into high-speed data.

Further, when high-speed data is demultiplexed (during reception), an 8-bit parallel signal containing data at a predetermined bit position is converted into a serial signal by the serial/parallel conversion means 11. Subsequently, the data control means 15 extracts the data in the predetermined time range according to the timing signal output from the bit position setting timing generation means 13, thereby obtaining desired data and converting it into low-speed data. can.

[For production]

The present invention is useful when bit multiplexing low-speed data (at the time of transmission).
[Embodiment] Hereinafter, embodiments of the present invention will be described in detail based on the drawings in accordance with the timing signal output from the bit position setting timing generating means 13.

FIG. 2 is a plot diagram showing the configuration of an embodiment of the present invention.

In the figure, a serial-to-parallel converter 21 is connected to the high-speed line side, and performs serial-to-parallel conversion between an 8-bit parallel signal (Nbps) and a serial signal (No. 8 (Nbps)) using, for example, a shift register.

The bit position signal generating section 23 is composed of, for example, a counter, and generates a reference bit position signal. The bit position comparator 25 is composed of, for example, a decoder, and compares the bit position signal (2) with externally input setting information, and generates a timing signal (2) corresponding to a predetermined bit position.

The input/output control section 27 is composed of, for example, a buffer gate, and performs data input/output control according to the timing signal (2). The data memory 29 is configured with a flip-flop, for example, and receives a data signal (MN/8 bps) on the data generation source side.
Absorbs the phase difference between (1) and the input/output control unit 27 side. Here, M is the number of occupied bits of the 8-bit parallel signal (1
≦M≦8).

Further, a common clock signal (N)Iz) is input to each part.

The serial/parallel converter 11, the bit position setting timing generator 13, and the data controller 15 shown in the block diagram of the principle of the present invention in FIG. 1 are the serial/parallel converter 2, respectively.
1 corresponds to the bit position signal generation section 23, bit position comparison section 25, input/output control section 27, and data memory 29.

The operation of the embodiment of the present invention will be described below with reference to the time charts shown in FIGS. 2 and 3.

Note that the signal ■ shown in FIG. Furthermore, as shown in FIG. 4, when data is set in 2 bits (bz, ba) of a time slot with an 8-bit configuration (bo, b, . . . , bi) (M-2
) will be explained.

When converting low-speed data into high-speed data by bit multiplexing (at the time of transmission), the input/output control unit 27 outputs the timing signal ■
Accordingly, data D is placed on the corresponding time domain of the serial signal.
, ,D, (data signal ■) is inserted into a signal ■. This signal (■) is input to the serial/parallel converter 21, where the bit correspondence shown in the signal (■) is taken, and by latching the 8-bit data at the timing of the bit position (bz, bi), the corresponding bit position (bz, bi) is data (Do, D
+) is obtained.

When demultiplexing high-speed data and converting it to low-speed data (during reception), the serial/parallel converter 21 converts the data into predetermined bit positions (b
A parallel signal in which data (DO, D) is superimposed on z, bi) is serial-parallel converted into a signal ■.

The input/output control unit 27 extracts data D (1+D1) in the time domain indicated by the signal ■ from the signal ■ according to the timing signal ■, and the data signal ■ is obtained via the data memory 29.

As described above, according to the method of the present invention, it is possible to set the bit position of the time slot where data is inserted/removed using a timing signal according to the setting information. Therefore, it can be easily handled without changing the hardware.

〔Effect of the invention〕

As described above, according to the present invention, the data rate and the bit position corresponding to the data can be changed according to the setting information. That is, when the data rate changes, whether before or during operation, it is possible to flexibly respond by simply changing the setting information without adding or changing hardware.

Therefore, the versatility of the time division multiplexing device based on the bit multiplexing method of the present invention is increased, and the development efficiency of communication equipment using the same can be greatly improved, making it extremely useful in practice.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram showing the configuration of an embodiment of the present invention, and Figure 3 is a block diagram of the principle of the present invention.
Figure 4 is a time chart explaining the operation of the embodiment of the present invention; Figure 4 is a diagram showing time slots used to explain the embodiment; Figure 5 is a block diagram showing an example of the configuration of a conventional bit multiplexer; The figure is a diagram showing time slots used to explain a conventional example. In the figure, 11 is a serial/parallel conversion means, 13 is a bit position setting timing generation means, 15 is a data control means, 21 is a serial/parallel conversion section, 23 is a bit position signal generation section, 25 is a bit position comparison section, and 27 is an input. 29 is a data memory, 51 is a data arrangement section, and 53 is a data control section. Fig. 2 Block diagram showing the configuration of the embodiment Fig. 1 Block diagram of the principle of the present invention Fig. 1 Time chart of the latch timing embodiment Fig. 3

Claims (1)

[Claims] (1) In a time division multiplexing device that performs bit multiplexing, a serial/parallel conversion means (11) that converts a serial signal into a parallel signal and transmits it, and converts the received parallel signal into a serial signal; bit position setting timing generating means (13) for generating a timing signal corresponding to a predetermined bit position of the parallel signal according to setting information; A bit multiplexing method characterized by comprising a data control means (15) for inserting and removing the data.