JPH02245855A - Select signal generator for input/output device - Google Patents

Abstract

PURPOSE:To easily change conversion contents with a relatively simple circuit constitution by constituting a select signal generator of a random access memory which is accessed by an address signal generated from a central processing unit and outputs a select signal of an input/output device preliminarily stored in the address. CONSTITUTION:The select a signal generator consists of a random access memory 2 which is accessed by the address signal generated from a central processing unit 1 and outputs a select signal of input/output devices 3-1 to 3-n preliminarily stored in the address. Since the select signal generator consists of one random access memory 2, the constitution is simplified, and it is sufficient if stored contents of the memory 2 are changed when conversion contents are changed, and they are easily changed and corrected.

Description

[Detailed Description of the Invention] [Summary] When selecting a plurality of input/output devices organized in a central processing unit, an address signal from the central processing unit is decoded to generate a select signal for a predetermined input/output device. Regarding a select signal generating device for an input/output device, the purpose is to be able to configure a select signal generating device for an input/output device with a relatively simple circuit configuration, and to easily change conversion contents. The select signal generating device as described above is constituted by a random access memory that is accessed by an address signal generated by a central processing unit and outputs a select signal of an input/output device stored in advance at the address.

(Industrial Application Field) The present invention relates to a select signal generation device for an input/output device,
In particular, the present invention relates to a select signal generating device that decodes an access signal from a central processing unit and generates a select signal for a predetermined input/output device when selecting a plurality of input/output devices connected to the central processing unit.

In order to use another operating system on a computer that uses only a specific operating system (O8), add an expansion board equipped with another processor that runs another operating system to the computer system that has a - processor. There are cases where the computer system is made to be able to run other operating systems.

In such a case, the address of the input/output device of the computer system does not match the address specified by another operating system. When another operating system runs there and uses the input/output device of the computer system by executing a program, the address of the input/output device specified by the other operating system is transferred to the input/output device of the operating system used by the computer system. The select signal must be generated by converting the address into the address.

[Conventional technology]

Conventionally, the select signal generating device for the input/output device as described above is a circuit element on an expansion board that converts the address of the input/output device generated by another processor into the address of the input/output device of the computer system. It was supposed to be constructed and built as hardware.

(Problem to be Solved by the Invention) However, as described above, in order to configure the select signal generating device as hardware using circuit elements, the number of circuit elements required increases, and it takes time and effort to assemble them. . Also, when the address specifying an input/output device for any operating system is changed,
- There is a problem in that the circuit configuration of the select signal generating device must be changed, which is complicated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a select signal generating device that can configure a select signal generating device for an input/output device with a relatively simple circuit configuration, and can easily change conversion contents. do.

(Means for Solving the Problems) In the present invention, means for solving the above problems include a plurality of input/output devices 3-1+s connected to the central processing unit 1, as shown in FIG. -2+...3-n, the address signal from the central processing unit is decoded to select a predetermined input/output device 3-1t, 3-2+...

In a select signal generating device that generates a select signal of 3-n, the select signal generating device is accessed by an address signal generated by the central processing unit 1, and random access is performed to output a select signal of an input/output device stored in advance at the above address. This is because it consists of memory.

[Effect]

According to the present invention, since the select signal generating device is composed of one random access memory, its configuration is simple, and the conversion contents can be changed by simply changing the contents stored in the random access memory. is sufficient, and changes and corrections can be easily made.

〔Example〕

Embodiments of a select signal generator for an input/output device according to the present invention will be described below with reference to the drawings.

FIGS. 2 and 3 show an embodiment of a select signal generating device for an input/output device according to the present invention. In FIG. 2, 11 is a processor of the expansion board, 12 is a data bus connected to this processor, and 13 is an address bus. Further, 14 indicates a processor of the computer system to which the expansion board is attached, 15 indicates a data bus connected to this processor, and 16 indicates an address bus. In the figure, reference numeral 17 indicates a multiplexer that selects and controls the decode address from the processor 11 and the write address from the processor 14, and 19 indicates a transceiver that controls the write data from the processor 14.

In the same figure, 18 is a static random access memory (SRAM) which operates as a select signal generator for input/output devices in this embodiment, and its data is written by the processor 14 under the control of the multiplexer 11 and transceiver 19. At the same time, an input/output select signal is generated by accessing the decode address of the processor 11. Note that S by the processor 14
The contents of the RAM are rewritten before the device is used, depending on how each operating system specifies the address of the input/output device.

That is, when the processor 14 is expanded by connecting an expansion board including the processor 11, multiplexer 17, SRAM 18, and transceiver 19 with a connector, the microprogram for its operation is also changed.

At that time, the microprogram contains the Ilo I1 specified by the processor 11 mounted on the expansion board.
0 address information is included.

Therefore, during the initialization operation after the power is turned on, the processor 14 first sets a flag in the hard register for designating the extended processor 11 side to be in the reset state. The expansion processor 11 switches the multiplexer 17 to select the input from the processor 14 according to the contents of this hard register.

Next, the processor 14 stores this I10 address in the SRAM 1 based on the I10 address information of the processor 11.
8 and the corresponding information (data) of the device 10 to the SRAM 18 via the transceiver 19, thereby writing the device 10 data into the storage area of the SRAM 18 indicated by this device 10 address. By performing this process for each I10, for example, a disk, printer, display, etc., the SRAM 18 is rewritten. Then, the processor 14 enables the operation of the extended processor 11 by resetting the contents of the aforementioned hard register,
The expansion processor 11 immediately switches the multiplexer 17 to the expansion processor 11 side.

The select signals of these input/output devices are as shown in FIG. In this figure, the processor and static random access memory are given the same reference numerals as in FIG. 2. In the same figure, 20-0 and 20-1 are 0th and first programmable interactive controllers (PICO) that perform interrupt control.

PICI), 21 is a programmable timer (PITO)
, 22 is a multi-protocol serial controller (MPSC) that controls the line, 23 is a pseudo IO
It shows a register that stores a notification signal for software that is a request.

Then, according to a predetermined address designation from the processor 11, a processor 14 of a computer system (not shown)
Input/output device decode signals stored corresponding to each address according to the designation from , ie, PICOIC-bull signal, PICIIC-bull signal, PITO enable signal,
Generates an MPSC enable signal and a notification signal to software.

That is, during its own processing operation, the processor 14 accesses each of the above-mentioned I10 connected via the address bus 16 and data bus 15.

On the other hand, when the processor 11 needs to access Ilo while executing a process in response to an instruction from the processor 14 or the like, it outputs the I10 address of the desired Ilo and inputs it to the SRAM 18. SRAM18 is this I1
In response to the 0 address, interrupt information for the processor 14, which is an I10 select signal, and a status indicating the desired work/o are stored in the interrupt register and status register in the processor 14.

Further, the processor 11 sets necessary data in an address register and a data register for communication provided between the processor 14 and the processor 14 .

Therefore, the processor 14 reads the contents of the communication register according to the contents of the interrupt register and the status register, executes access to the corresponding Ilo, etc., and then outputs a completion notification to the processor 11. Stores the processing result from memory (in case of read, etc.).

The processor 11 then continues processing based on this.

Therefore, according to this embodiment, the static random access memory (SRA) does not operate as a select signal generator in advance.
M) Since the processor 14 writes the address of the input/output device of the computer system as data to the address that the processor 11 uses as the address of the input/output device, the computer The address of the input/output device of the system is accessed, and a select signal is issued to the input/output device of the computer system. At this time, only 91 static random access memory devices are required, and the circuit configuration is simple.Also, since the contents stored in this static random access memory can be rewritten as necessary, the input/output device It is possible to quickly respond to changes in addresses.

(Effects of the Invention) As explained above, according to the present invention, the select signal generator is accessed by an address signal generated by the central processing unit, and a random output device outputs a select signal of an input/output device stored in advance at the address. Since it is constructed from an access memory, it is possible to construct a select signal generating device for an input/output device with a relatively simple circuit configuration, and the conversion contents can be easily changed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, and FIGS. 2 and 3 are block diagrams showing an embodiment of a select signal generating device for an input/output device according to the present invention. 1...Central processing unit 2...Random access memory (select signal generator)

Claims (1)

[Claims] A plurality of input/output devices (3) connected to a central processing unit (1)
_-_1, 3_-_2, ..., 3_-_n), an input/output device select signal that decodes the address signal from the central processing unit (1) and generates a predetermined input/output device select signal In the generating device, the select signal generating device is accessed by the address signal generated by the central processing unit (1), and selects the input/output devices (3_-_1, 3_-_2, ..., 3_-_n) stored in advance at the above address. 1. A select signal generating device for an input/output device, comprising a random access memory (2) that outputs a signal.