JPH0224578A - Extracting method of net of layout wiring for integrated circuit - Google Patents

Abstract

PURPOSE:To make it unnecessary to divide a line by a grid, to shorten a processing time, and to conduct a net extracting processing at a high speed by making the node of lines correspond to the lines and by executing a processing in view of the node or the lines. CONSTITUTION:By executing a processing (4) repeatedly after the following processings (1) to (4) are executed sequentially, net distinction signals are determined for all lines. (1) All the nodes C1 to C16 of lines 1 to 10 which constitute a layout wiring of a straight line are determined. (2) The lines 1 to 10 having the nodes C1 to C16 as end points or intermediate points are made to correspond to these nodes C1 to C16. (3) The net distinction marks are attached to the lines 1 to 10 having terminals on one side thereof. (4) Regarding the nodes C1 to C16 to which the lies 1 to 10 given the net distinction marks belong, the same net distinction marks with the above are attached to other lines 1 to 10 belonging to the nodes C1 to C16. According to this method, a processing time is shortened and a net extracting processing is executed at a high speed.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 5.6) Problems to be solved by the invention Means for solving the problem (Figure 1.2) Working examples First Embodiment (Fig. 3.4) Second Embodiment Effects of the Invention [Summary] Regarding a net extraction method for obtaining nets for layout wiring of integrated circuits, especially LSI and VLSI, it is possible to extract nets in a shorter time. The purpose is to find all connection points of a line that is a straight layout wiring, and then associate the connection point with a line whose end point or intermediate point is the connection point, or make the line correspond to the line whose end point or intermediate point is the connection point. Correlate the connection point which is the intermediate point, then attach a net distinction symbol to the line with one terminal, and then attach the connection point to which the line with the net distinction symbol belongs to the contact point. Add the same net distinguishing mark as the net distinguishing mark to other lines that belong to it, or add the same net distinguishing mark as the net distinguishing mark to other lines that have the same connection point as the connection point belonging to the line to which the net distinguishing mark is attached. By attaching a net distinguishing mark and repeating this last process, the net distinguishing mark is obtained for all lines.

[Industrial Application Field] The present invention relates to a net extraction method for finding layout wiring nets for integrated circuits, particularly LSIs and VLSIs.

``Conventional technology 1: As LSIs become larger in scale, the processing time to verify whether the layout wiring of the actual wiring matches the wiring in the logical design becomes longer, and the processing time occupies most of the processing time. There is a demand for faster net extraction processing.

A conventional net extraction method will be explained based on FIGS. 5 and 6.

Hereinafter, an unbent straight line on the layout wiring will be referred to as a line, and in FIG. 5, a line in the horizontal direction (X direction) will be referred to as a horizontal line, and a line in the vertical direction (Y direction) will be referred to as a vertical line.

The layout wiring shown in FIG. 5 consists of 10 lines, and the start and end points of each line are indicated by Si, Ej (j-river to 10). St, S4, S8 on the left end and E on the right end
It is assumed that l, E2, E5, Ej, E8, and EIO are terminals.

The coordinates of the start and end points of each line are entered manually into the computer, and the computer extracts the net using the slit method based on the flowchart shown in FIG.

That is, (50) In order to sequentially process from the left side to the right side in FIG. 5, all lines are rearranged in ascending order of the X coordinate of the starting point Si. It is assumed that (X coordinate value of starting point Si)≦(X coordinate value of ending point E1).

(51) Next, set a grid G~G4 parallel to the Y axis that passes over the terminal or vertical line. The space between these grids is called a slit, and the processing will be performed in units of slits below. For this reason, the horizontal line is divided into grids Gl to G4. For example, the line between Sl and Ej divides this into lines 1.2 and 3. In FIG. 5, the X marks indicate dividing points.

(53) In order to start processing from grid G1 in the following processing loop, grid number i is initialized to 4:I.

(54) First, the lines having starting points in grid G1-H are rearranged in order of decreasing Y coordinate of the starting points. ,
In FIG. 5, they are rearranged in the order of Sl, S4, and S8.

(55) Initially i=1, (56) In FIG. 5, a net number is assigned to the line with the left terminal. Specifically, line l has n! ,
Assign net numbers n2 to line 7 and n3 to line 12.

(59) Next, the value of i is incremented.

(60) Since r<imeW4, the process returns to step 54, and (54) the above-mentioned rearrangement is performed for grid G2.

(55) Since i≠1, (57) Net numbers are attached to the vertical lines on grid G2 as follows.

That is, since the end point E4 of the horizontal line 7 exists on the vertical line 6, the same net number n2 as the horizontal line 7 is assigned to the vertical line 6. Further, since the end point of the horizontal line 12 exists at the starting point S9 of the vertical line 15, the same net number n3 as the horizontal line 12 is given to the vertical line I5.

(58) Next, a net number is attached to the right horizontal line of grid G2 as follows.

In other words, line at the start of line 2! Since there is an end point, line 2 is assigned the same net number nl as line I. Also, since the start point of line 6 exists at the start point of line 4, line 4 has the same net number n as line 6.
Add 2.

Thereafter, the same process as above is performed until i=4 in step 60.

In this way, by sequentially performing the processing in units of slits, it is possible to attach net numbers to all lines.

[Problems to be Solved by the Invention] However, in the above slit method, since the horizontal lines are divided into grids, it is necessary to process a large number of lines (in the above example, 10 lines before division and 17 lines after division). However, there was a problem in that the net extraction processing time took a long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for extracting nets from layout wiring for integrated circuits, which allows nets to be extracted in a shorter time.

[Means for Solving the Problems] 1) FIG. 1 is a flowchart showing the principle configuration of the first invention.

In the first invention, the following processes (1) to (4) are performed in order, and then process (4) is repeatedly executed to obtain net distinguishing symbols for all lines.

(1) Find all connection points of lines that are straight layout wiring.

(2) A line having the connection point as an end point or an intermediate point is made to correspond to the connection point.

(3) Add a net distinguishing symbol to the line that has one terminal.

(4) Regarding the connection point to which the line to which the net distinction mark is attached belongs, the same net distinction mark as the net distinction mark is attached to other lines belonging to the connection point.

2), FIG. 2 is a flowchart showing the principle configuration of the second invention.

In the second invention, the following processes (1), (2°), (3), (
4°) in order, and then repeating the process (4') to obtain net distinguishing symbols for all lines.

(1) Find all connection points of lines that are straight layout wiring.

(2°) The connection point, which is the end point or midpoint of the line, is made to correspond to the line.

(3) Add a net distinguishing symbol to the line that has one terminal.

(4°) The same net distinguishing mark as the net distinguishing mark is attached to other lines that have the same connection point as the connecting point belonging to the line to which the net distinguishing mark is attached.

[Operation] Since the connection points of the lines are made to correspond to the lines and processing is performed by focusing on the connection points or lines, there is no need to divide the lines into grids as in the conventional example.

Therefore, the processing time is shortened accordingly, and the net extraction process is performed at high speed.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

(1) First example FIG. 3 shows the same layout wiring as FIG. 5.

In the figure, S i , E i (+ = 1 to 10)
C shows the starting point and ending point of line 1, which is a straight line layout wiring.

Next, based on the flowchart shown in FIG.
The net extraction procedure in the embodiment will be explained.

(70) In order to sequentially process from the left side to the right side in FIG. 3, all lines are rearranged in ascending order of the X coordinate of the starting point Si. It is assumed that (X coordinate value of starting point Sj)≦(X coordinate value of ending point Ei).

(71) Next, find all connection points 01 to C, +6 of the rhino. In Fig. 3, ◇ indicates a connection point. Note that the terminals Sl, S4, S8, El, C2, C5, C7, C8, and .EIO are connection points with circuit elements or wiring (not shown). In FIG. 3, for example, starting point Sl of line 1 corresponds to connection point CI, starting point S2 of line 2 and starting point S3 of line 3 correspond to one connection point C4, and ending point E4 of line 4 and line 3 correspond to one connection point C4. The intermediate point corresponds to one connection point C5.

(72) Next, as shown in Table 1 below, each connection point is given a line number of the line whose end point or intermediate point is the connection point. For example, connection point C4 has line numbers 2 and 3.
to have.

(73) In the following processing loop, grid number i is initialized to 1 in order to start processing from grid Gl.

(74) First, the lines having their starting points on the grid Gl are changed in ascending order of the Y coordinate of the starting point. Third
In the figure, they are rearranged in the order of SI, 84, and S8.

(75) Initially i=1, (76) In FIG. 3, assign a net number to the line with the left terminal. Specifically, line l has nl,
Assign net numbers n2 to line 4 and n3 to line 8.

(79) Next, the value of i is incremented.

(80) Since i<+max=4, the process returns to step 74, and (74) the above-mentioned rearrangement is performed for grid G2.

(75) Since i≠1, (77) Next, the connection points on grid G2 with the left horizontal line of grid G2, connection points c5 and C7 in FIG.
, net numbers are assigned to other lines of these connection points as follows. In other words, Figure 1 and Table 1 below
In this case, since the line 4 belonging to the connection point c5 is assigned the net number n2, the same net number n2 is assigned to the line 3 as well.

In addition, line 8I belonging to connection point C7 has net number n3.
Therefore, line 9 is also given the same net number n3.

(78) Next, the grid G 2 has 4 vertical lines of h.
Wow, grid G 2. Regarding the connection points c4, C6 and C8 in FIG. 3, net numbers are assigned to other lines of these connection points as described above. That is, in FIG. 1 and Table 1 above, the net number n2 is attached to line 3 for connection points c4 and C6, so
The same net number n2 is given to line 2.5.

Also, for connection point 08, line 9 has net number n
3 is attached, so the same net number n3 is attached to line C2 as well.

(79) Next, set the value of i to 3.

(80) Since i < i, □, the process returns to step 74 and the above process is repeated.

As a result, for connection point c9, net number n2 is added to line G, and line 7 is attached to connection point CIO.
Add a net number +12 to .

In this way, all lines are given a net number h (
1" = l s a *, I-f' in S F-J 8G
I) Fsatl, net extraction procedure h<end.

(2) Second Embodiment In the first embodiment described above, the connection point has a line number, but in the present invention, it is sufficient to associate the connection point with the line number, and the line number has the connection point. The configuration may be such that the The correspondence of this configuration is shown in Table 2 below.

Net number n2 is assigned to Table 2, and net number n3 is assigned to line 8.

Next, since connection point C5 belongs to line 4 having net number n2, line 3 to which this connection point C5 belongs is also given net number n2. Next, since the connection point C7 belongs to the line 8 having the net number n3, the line 9 to which this connection point C7 belongs is also given the net number n3.

Next, since connection point C4 belongs to line 3 having net number n2, line 2 to which this connection point C4 belongs is also given net number n2. Similar processing is performed below.

In Table 2 above, as in the first embodiment, the net number n1 is first assigned to the line l, and the line 4 [Effects of the Invention] As explained above, the net extraction of the layout wiring for an integrated circuit according to the present invention is performed. According to this method, the connection points of lines are made to correspond to the lines, and the processing is performed by focusing on the connection points or in, so there is no need to divide the line with a grid as in the conventional method, and it is possible to Once determined, all data can be treated as points in the 71st step of determining the net, and the net can be determined without considering the concept of line length. Therefore, the processing time is shortened and the net extraction process is performed at high speed. It has the excellent effect of being able to perform various functions, and greatly contributes to shortening the development period for integrated circuits.

FIG. 6 is a flowchart showing the net extraction procedure for layout wiring for an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the principle structure of the first invention, and FIG. 2 is a flowchart showing the principle structure of the second invention. 3 and 4 relate to the first embodiment of the present invention, FIG. 3 is an explanatory diagram of a method for extracting a net for layout wiring for an integrated circuit, and FIG. 4 is a flowchart showing a procedure for extracting a net for layout wiring for an integrated circuit. It is. 5 and 6 relate to a conventional example, and FIG. 5 shows a net extraction method for layout wiring for an integrated circuit;
Explanatory diagram, flowchart showing the configuration of the first invention nl-+n3 Net extraction method for layout Innoshima for net S product circuit Third diagram
Figure 2 Flowchart showing the configuration of the invention Net extraction method for a layout circuit for integrated circuits 1 page Figure 4 n1 to n3 Diagram for explaining the net extraction method for a layout circuit for net integrated circuits (prior art example) Figure 5 Layout circuit for xi circuits Net extraction procedure (conventional example)
Figure 6

Claims (1)

[Claims] 1), after performing the following processes (1) to (4) in order, the process (
4) A net extraction method for layout wiring for an integrated circuit, characterized in that net distinguishing symbols are obtained for all lines by repeatedly executing step 4). (1) Find all connection points of lines that are straight layout wiring. (2) A line having the connection point as an end point or an intermediate point is made to correspond to the connection point. (3) Add a net distinguishing symbol to the line that has one terminal. (4) Regarding the connection point to which the line to which the net distinction mark is attached belongs, the same net distinction mark as the net distinction mark is attached to other lines belonging to the connection point. 2) After performing the following processes (1), (2'), (3), and (4') in order, calculate the net distinguishing symbol for all lines by repeatedly executing process (4'). A method for extracting nets from layout wiring for integrated circuits. (1) Find all connection points of lines that are straight layout wiring. (2') The connection point, which is the end point or intermediate point of the line, is made to correspond to the line. (3) Add a net distinguishing symbol to the line that has one terminal. (4') Add the same net distinguishing mark as the net distinguishing mark to other lines that have the same connection point as the connecting point belonging to the line to which the net distinguishing mark is attached.