JPH02244741A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a part between layers to be flattened and improve coverage even under strict designing specifications by forming a first interlayer insulation layer while etching the upper-edge angle part of a lower-layer wiring layer by argon gas, by forming a second interlayer insulation layer on the first interlayer insulation layer and on the lower-layer wiring layer, and by forming a third interlayer insulation layer while etching one part of the second interlayer insulation layer surface by using an insulation layer forming gas. CONSTITUTION:An Al wiring layer 12 is formed on a silicon substrate 11. Then, a CVD film 13a of SiO2 is formed by the plasma CVD method using SiH4, O3, and Ar mixture gas while sputter-etching the upper-edge square part of the Al wiring layer 12. When the square part becomes round, addition of Ar and application of power are suspended and then an SiO2 CVD film 13b is formed by the CVD method in SiH4 and O2 family. Then, by adding Ar again, the projecting part on the upper surface is flattened and an interlayer insulation film CVD film 13c consisting of SiO2 is formed on an Al wiring layer.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method of manufacturing a semiconductor device, particularly a method of growing an interlayer CVD film during the manufacture of a semiconductor device, which enables interlayer planarization and improves coverage even under conditions with strict design specifications. , the purpose of which is to provide a method for manufacturing a semiconductor device that can prevent short circuits between wiring layers, and when forming an interlayer insulating layer between two wiring layers formed on a semiconductor substrate, consisting of at least a lower layer and an upper layer, an argon gas forming a first interlayer insulating layer while etching the upper end corner of the lower wiring layer with the argon gas by an electron cyclotron resonance (ECR) plasma CVD method using an insulating layer forming gas containing as a reaction gas; When the upper end corner of the lower wiring layer becomes rounded, the argon gas supply is stopped, and then the plasma CVD method using the insulating layer forming gas is applied to the first interlayer insulating layer and the lower wiring layer. A second interlayer insulating layer is formed thereon, and then argon gas is supplied again to form a third interlayer insulating layer while etching a part of the surface of the second interlayer insulating layer using the insulating layer forming gas. The structure includes forming a flat interlayer insulating layer by forming layers.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for growing an interlayer CVD film during the manufacturing of a semiconductor device.

In recent semiconductor devices, as the degree of integration increases, the distance between layers (hereinafter referred to as L-L space) has become narrower, so better planarization of each layer and better shape of wiring such as ferb are required. ing.

[Conventional technology]

Conventionally, the manufacturing method for semiconductor devices generally consists of steps from FIG. 2A to FIG.
This is done by process flow shown in Figure C.

That is, as shown in FIG. 2A, an Al wiring layer 2 is formed on a valve layer 1 such as a silicon substrate, and an SPG film 3 is formed with a relationship between L and L<VD film. When the design specifications become stricter, cavities 4 are formed during the formation of the SPG film, and unevenness is also formed along the Al wiring layer 2. Next, as shown in FIG. 2B, in order to reduce the cavities and unevenness, an interlayer S
After forming an OG (silicon on glass) layer 5, etching is performed, and a PSG film 6 is further formed by CVD.
Although cavities and irregularities are reduced as shown in Figure 2C,
The side wall of the P section, which is the corner of the ffi wiring layer 2, becomes thinner (coverage deteriorates), resulting in a problem of a decrease in breakdown voltage and short circuit between the Al wiring layer 2 and the Al wiring layer 7 on the PSG film 6. did.

[Problem to be solved by the invention]

In this way, as the degree of integration of semiconductor devices increases, the design specifications become stricter, and when the distance between -L becomes narrower, the coverage between them deteriorates, causing poor coverage and short circuits between wiring layers, resulting in a decrease in the yield of semiconductor devices. It became.

An object of the present invention is to provide a method for manufacturing a semiconductor device that enables interlayer planarization, improves coverage, and prevents short circuits between interconnect layers even under strict design specifications.

[Means to solve the problem]

According to the present invention, when forming an interlayer insulating layer between two wiring layers consisting of at least a lower layer and an upper layer formed on a semiconductor substrate, the electron cyclotron uses an insulating layer forming gas containing argon gas as a reaction gas. Resonance (ECR) 7”
A first interlayer insulating layer is formed while etching the upper end corner of the lower wiring layer with the argon gas by the plasma CVD method, and the argon gas is supplied when the upper end corner of the lower wiring layer has a rounded shape. Next, a second interlayer insulating layer is formed on the first interlayer insulating layer and also on the lower wiring layer by the insulating layer forming gas≠intake plasma CVD method, and then the argon gas is used again to form a second interlayer insulating layer. forming a third interlayer insulating layer while etching a part of the surface of the second interlayer insulating layer using the insulating layer forming gas to form a flat interlayer insulating layer; The problem is solved by a method of manufacturing a semiconductor device characterized by the following.

[For production]

In the present invention, when an interlayer insulating layer is formed by supplying argon to the ECR plasma CVD apparatus, the insulating layer is deposited simultaneously with sputter etching using argon. Therefore, for example, the upper corner of the wiring layer such as A1 is rounded by etching, and other convex parts are flattened.

As the insulating layer forming gas, S10. S when forming
The iH,,02 system is preferred, and the 3iH4,Nz system is preferred for forming Si, N.

〔Example〕 Embodiments of the present invention will be described below based on the drawings.

1A to 1E are process cross-sectional views showing one embodiment of the present invention.

First, as shown in FIG. 1A, a film with a thickness of 2.
Pa's AI! The wiring layer 12 is formed by patterning after vapor deposition as usual. At this time, the upper end of the Al wiring layer 12 is formed to have an angular shape.

Next, as shown in Figure 1B, a CND (Chemical Vapor Deposition) film of SiO□ (1N3a was prepared using an ECR plasma CVD device and 3i) was mixed with 14.0z and Ar at a mixing ratio of 2:5. The upper end corners of the Al wiring layer 12 are formed by sputter etching (particularly using Ar) using a gas plasma CVD method.

The applied power density at this time is approximately 62Qn+W/caf.

When the corners became rounded, the addition of Ar and the application of power were stopped, and after that, a 5in4 and 02 type SiO, CVD film (nH3b) was formed by the CVD method, and a layer of about 0.3-cm above the Aβ wiring layer 12 was formed. thicken (Figure 1C).

Next, as in the case of forming the first CVD film 13a of 5102, while adding Ar and flattening the convex portion of the upper surface, an interlayer insulating film (CVD film of S10 1II) Form 13c) (FIG. 1D).

The applied power density at this time is about 1850 mW/caf.

Thereafter, a contact hole is made in the interlayer insulating film (Si(l□)) as in the conventional method, and A1 is vapor-deposited and patterned.
A wiring layer is formed (FIG. 1E). Note that it is also possible to make the SiO2 film more planar by etching it before forming the contact hole.

In each CVD method in this example, the pressure inside the reaction tube was set to about 10-3 torr.

〔Effect of the invention〕

As explained above, according to the present invention, when performing interlayer planarization, even if the design specifications are strict, for example, the distance between L and L is 0.5-, no cavity is generated in the insulating layer, and moreover, the wiring Since the upper corner of the layer can be rounded, coverage can be improved, and a decrease in breakdown voltage and short circuit between wiring layers can be prevented.

[Brief explanation of drawings]

1A to 1E are process sectional views showing one embodiment of the present invention, and FIGS. 2A to 2C are process sectional views for explaining the conventional technique. 1... Bulk layer, 2... Al wiring layer (first), 3...
6... PSG film, 4... Cavity, 5... SOG layer,
7...Al wiring layer (first ■), 11...Silicon substrate, 12...A1 wiring layer (first
), 13 a-・-5iO, CV D film (first), 1
3b...SiO□CVD film (No. ■) 13c...5i
n2CVD film (Part 2), 14...Al wiring layer. IIA Figure 1E procedural amendment (voluntary) July 1999 // Figure 2B Conventional example

Claims (1)

[Claims] 1. An electron cyclotron using an insulating layer forming gas containing argon gas as a reaction gas when forming an interlayer insulating layer between two wiring layers consisting of at least a lower layer and an upper layer formed on a semiconductor substrate. By resonance (ECR) plasma CVD method, a first interlayer insulating layer is formed while etching the upper end corner of the lower wiring layer with the argon gas, and when the upper end corner of the lower wiring layer has a rounded shape. The argon gas supply is stopped, and then a second interlayer insulating layer is formed on the first interlayer insulating layer and on the lower wiring layer by plasma CVD using the insulating layer forming gas, and then again. While supplying argon gas and etching a part of the surface of the second interlayer insulating layer using the insulating layer forming gas, the third interlayer insulating layer is etched.
1. A method of manufacturing a semiconductor device, comprising forming an interlayer insulating layer to form a flat interlayer insulating layer.