JPH02244640A - Insulated-gate field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To relax a field concentration at the end part of a drain contact region by a method wherein a drain region has a second conductivity type deeply diffused region under the drain contact region and a second conductivity type shallowly diffused region, which comes into contact with this deeply diffused region and is provided on the side of a source region. CONSTITUTION:A drain electrode is connected to the upper part of a P-type drain contact region 227 having an impurity diffused through the surface of an N-type silicon substrate 201 in a high concentration. A drain deep diffusion region 205 having comparatively low impurity concentration is provided under the region 227 and a drain shallow diffusion region 211 having a comparatively low impurity concentration is provided on the periphery of the region 205. In such a way, a field concentration at the end part of the region 227 can be relaxed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect transistor and a method for manufacturing the same, and particularly to a high breakdown voltage (approximately 100 V or higher).
-).

[Conventional technology]

As this type of field effect transistor (FET), the one shown in the vertical cross-sectional view of FIG. 3 is known.

In this figure, reference numeral 305 denotes a 1) type drain contact region with high impurity concentration diffused from the surface of the I] type silicon substrate 302, and is connected to a drain electrode (not shown) thereon. 304 is a p-type drain shallow diffusion region with a relatively low concentration, 307 is a p-type source contact region with a high impurity concentration, 308 is an n-type channel contact region with a high impurity concentration, 30 is a gate electrode, 31
1 is a gate oxide film.

Source contact region 307 and channel contact region 308 are connected to the -L source electrode (not shown).

The above configuration is installed symmetrically around the line 301, and when viewed from the top, the drain 305 is the center and the gate 03 and the source 30 are surrounded by the drain 305.
The 7th class is arranged in a ring or competition track shape.

[Problem to be solved by the invention]

In this FET, the small portion at line 3 ( ) 6 becomes the end of the depletion layer, and the shallow diffusion region 30 with a relatively low impurity concentration
4 alleviates drain electric field concentration,
Nevertheless, the end 30 of the drain contact region 305
Electric field concentration occurs at 9. In order to alleviate this problem, the low concentration drain length 310 may be increased, but this is not preferable because the device area increases.

In addition, electric field concentration also occurs at the drain end (channel-drain boundary) 312, which is an obstacle to increasing the breakdown voltage.

In view of the above points, the present invention improves the junction structure of the drain part, thereby achieving the following without increasing the element area.
The first purpose is to alleviate the electric field concentration at the edge of the drain contact region, and by changing the shape or mutual position of the gate electrode 1 gate oxide film and the channel/drain boundary, the electric field concentration at the channel/drain boundary is reduced. The second purpose is to alleviate the situation.

[Means to solve the problem]

In order to achieve the above-mentioned first objective, the present invention
A source and drain region of a second conductive layer provided on a conductive type semiconductor substrate, and the source and drain region m
] In an insulated gate field effect transistor comprising a channel region and a gate electrode provided between the source and drain regions with an insulating film interposed therebetween, the drain region has a drain contact region connected to the drain electrode. m'')' It is characterized by having a deep diffusion region of the z2 conductivity type and a shallow diffusion region of the second conductivity type provided in contact with this region on the source region side.

Further, in order to achieve the first and second objects, in addition to the above-mentioned means, the insulating film is made of a gate oxide film and an oxide film thicker than the gate oxide film, and the thick oxide film is formed in the deep diffusion region. The shallow diffusion region is preferably provided between the drain contact region connected to the upper drain electrode and the channel region, and the shallow diffusion region preferably extends 2 toward the channel region side beyond the thick oxide film. , an end of the gate electrode may be provided in the thick oxide m J=.

Furthermore, in order to achieve the first and second objects, in addition to the above-mentioned means, the drain region is provided in the center, and the channel region and the source region are provided surrounding it. good.

The method for manufacturing a transistor of the present invention that achieves the first and second objects described above includes selectively introducing impurities of a second conductivity type into the surface of a semiconductor substrate of a first conductivity type, and then diffusing the impurities. forming a deep diffusion region for the drain;
Introducing a second conductivity type impurity around the deep diffusion region, diffusing the impurity to form a shallow drain region, and selectively forming a thick oxide film on the surface of the 14 conductor substrate. a step of forming a gate electrode; a step of introducing impurities of a first conductivity type using the thick oxide film and the gate electrode as a mask to form a highly concentrated channel region; and forming a drain region using the thick oxide film as a mask. A second conductivity type impurity is introduced for a contact region, a second conductivity type impurity is introduced for a source contact region using the gate electrode and resist as a mask, and a second conductivity type impurity is introduced for a channel contact region using the thick oxide film and resist as a mask. The method is characterized by comprising a step of introducing an impurity of the first g$ type and then diffusing it.

[Effect]

Since the drain region is composed of a deep diffusion region under the drain contact region in addition to a shallow diffusion region, the curvature of the junction surface becomes large, and the device area can be improved without increasing the device area.
Electric field concentration at the end of the drain contact region is alleviated.

In addition, a thick oxide film is provided on the surface of the shallow drain diffusion region.
Since the shallow drain diffusion region 7 overlaps with the gate pole and extends beyond the edge of the thick oxide film, the channel and
Electric field concentration at the drain boundary is alleviated.

〔Example〕

FIG. 1(a) is a longitudinal cross-sectional view of a field effect transistor (FET) according to an embodiment of the present invention [n1], and 227 is a p-type drain contact with a high impurity concentration expanded from the surface of an n-type silicon substrate 201. The region is connected to its drain electrode (not shown). 205 is a deep drain diffusion region with a relatively low impurity concentration provided thereunder, 211 is a deep drain diffusion region with a relatively low impurity concentration provided around it, 210 is a thick oxide film, 212
213 is a gate oxide film, 213 is a boron silicon gate electrode, 2
22 is a p-type source contact region with high impurity concentration;
3 is an n-type channel contact region with high impurity concentration; 21
7 is an n-type high concentration channel region with a relatively high impurity concentration, and the source contact region 222 and the channel contact region are connected to the source electrode (not shown) thereon.

The above configuration is provided symmetrically about the line 101, and when viewed from the top, the drain contact region 227
A shallow drain diffusion region 21 is formed around it.
1. A gate 213, a source 222, etc. are provided in a ring shape or a competition track shape.

Here, when the potential of the polysilicon gate electrode 213 is lowered by VTII (L threshold voltage) than the potential of the source electrode (source contact region 222 and channel contact region 223), the channel region 114 becomes p-type,
Current (in this case, the correct card) flows through the source, channel, and drain, forming a conductive plate.

Next, FIGS. 2(a) to 2(j) are diagrams showing the manufacturing process of the FET shown in FIG. 1.

First, boron ion implantation 203 is performed using the oxide film 202 (or photoresist) as a mask, and impurities 204 are selectively doped (pre-doping IXIO"cm" energy 50KeV) (a,).

This impurity is diffused to form a deep diffusion region 205.

(Diffusion depth Xj = 9 μm 1 Surface impurity a degree C0 =
I X10160m-') (b).

Next, boron ions 207 are implanted again using the photoresist as a mask, and the impurities 208 are selectively implanted into the deep diffusion region 20.
Dope around 5 (I XIO"Cm-',
50KeV) (c),.

Furthermore, using the 5IJ4 film 209 as a mask, a thick oxide layer 11m3210 (film thickness 1.5 μm) is formed around the deep diffusion region 205 by thermal oxidation, and at the same time, the impurity 208 is diffused to form a shallow diffusion region 211 around the deep diffusion region 205. (Xj = 3 μm, Co = l xl
O16[:m-2)(d).

After removing the S+3L film 209, a gate oxide film is formed by thermal oxidation (thickness tox=1000) (C), and a polysilicon gate electrode 213 is formed so as to span the gate oxide film region and the thick oxide film region (f). ).

Here, a 7-layer photoresist 214 is formed in the drain active region (the part where the thick oxide film does not exist), and a polysilicon gate electrode 213. Phosphorus ions are implanted using the thick oxide film 210 and photoresist 214 as masks. At this time, ions penetrate through the gate oxide film region, and the Linnean blunt 21
6 ( 3 XIO” C0I-290KeV
) (powder.

This is diffused to form a high concentration channel region 217 (
hl (Xj = 3 μm, Co = 2 XI
O”cm-3).

Next, although omitted in the figure, source and drain contact ion implantation (boron) 218 was selectively performed using a mask process similar to the step (80(5)), and boron impurity 220 and channel contact ion implantation (phosphorus) were performed. ) 219 and introduce the Linnean blunt 221. Boron: 3.5 XIO"cm-' 33KeV, phosphorus: 3
45x IQ "cal-', 90KeV) (
i) A source contact region 222, a drain contact region 227, and a channel contact region 223 are formed by diffusion, all of which have Xj=1.2 μm;
Co=2X1 port 19CI11-3), and finally the interlayer insulation film 224. Source electrode 225 and drain electrode 2
Although not shown in the figure, a passivation film is further formed on the entire surface to complete the process (j).

In addition, the channel source part is DSΔ (self-aligned double diffusion method) using the edge of the polysilicon gate 213 as a mask.
is used to prevent breakdown voltage deterioration due to punch-through.

Furthermore, according to the prototype results, in FIG. 1, the length C3 of the thick oxide film region (approximately equal to the distance of the channel region drain contact region) is the reverse blocking breakdown voltage B of this device.
It is an important parameter that determines VDS, (lr3=
B VDS = 200 V at 12 um, 20 am
It is about 300v.

The relationship α4 between the position of the end of the thick oxide film 210 under the polysilicon gate electrode 213 and the end of the shallow drain diffusion region 211 is also important; if C4 is too small, the n-type channel part will be formed under the thick oxide film 210 as well. Therefore, VTH
(L, threshold voltage) increases. Furthermore, if C4 is too large, the effective channel length of the FET becomes short, and despite the DSA structure, bunch-through occurs and the withstand voltage deteriorates. Therefore, the optimum value of C4 is 2 μm to 3 m. At this time, the distance α1 between the end of the thick oxide #210 and the end of the polysilicon gate electrode 213 is 8 μm.

Even thicker oxide film 210 and polysilicon gate electrode 2
The overlap amount α2 of No. 13 also has an optimum value, which is about 2 μm.

This was also confirmed from the prototype results, as shown in Figure 1 (
The one shown in a) has improved breakdown voltage by about 20% compared to the one shown in FIG. For example, the conventional B VDS was 270 V, but this embodiment B Vos =300 V.

The reason for this will be explained below. In the conventional example shown in Fig. 3,
4″Drain except for the shallow drain diffusion region 304
Forming the drain region only with the contact region 30517
- Case: Since the diffusion depth is approximately 1.2 μm, the electric field is concentrated at the drain end 309 in the reverse blocking state, and its BVDS is approximately 50V.

Therefore, in the conventional technology, the drain shallow diffusion region 304
in an attempt to alleviate electric field concentration.

Drain shallow diffusion region 304 with constant drain voltage
When the impurity concentration of the drain shallow diffusion region 30 is changed,
When the concentration of 4 is low, the drain contact region end 30
The electric field is concentrated at 9, and as the concentration is increased further, the electric field is relaxed, and eventually the electric field is concentrated again at the channel/drain boundary 312. Therefore, it can be seen that the density of the region 304 has an optimum value. However, the boundary part 312
In the mode where electric field concentration occurs, the reverse blocking breakdown voltage is greatly reduced to about 70-80V. Therefore the end 309
Region 304 requires a relatively low impurity concentration within the range of the electric field concentration mode. Here, the reverse blocking breakdown voltage when the shallow drain diffusion region 304 does not exist is VA,
If the breakdown voltage improvement factor due to the change in the drain junction structure when the region 304 exists is αA, then the reverse flfl breakdown voltage of the conventional device is as follows.

B VDSA-α8・VA (
1) Next, in FIG. 1, first the drain shallow diffusion region 2
11 does not exist, the drain region is drain contact region 227 and drain deep diffusion region 2.
Since the region 205 has Xj = 9 μm, an electric field is concentrated at the drain end 112 in a reverse blocking state, and its BVDS is about 150V.

Here, if a shallow drain diffusion region 211 is added and the impurity concentration of the shallow drain diffusion region 211 is varied while keeping the drain voltage constant, the same result as described for the conventional method will be obtained. Here, if the reverse blocking voltage when the shallow drain diffusion region 211 does not exist is VB, and the breakdown voltage improvement factor due to the change in the drain junction structure is αB, then the reverse blocking voltage is B VDSB = αg −va
(2) becomes. Therefore, assuming that αA - αB, the magnitude of the reverse blocking breakdown voltage is determined by the magnitudes of VA and VB.

When comparing the conventional one and this embodiment, αA−α is not always the same.
It is not B, and it is considered that αA>αB, but VB is VA
Since it is larger, the withstand voltage is improved.

In addition, the polysilicon gate electrode 213 and the thick oxide film 21
Regarding the overlap of 0, the electric field strength distribution near the surface of the semiconductor substrate is as shown in Figure 1, etc.
A beak 115 exists at the pn junction between the channel region 114 and the shallow drain diffusion region 211, and a beak 116 also exists at the end of the polysilicon gate electrode 213.

The electric field distribution changes depending on the amount of overlap between the polysilicon gate electrode 213 and the thick oxide film 210, that is, the size of α2. For example, at α2-0, the two peaks almost overlap and the electric field strength increases, which is not preferable. Furthermore, as α2 is increased, the beater 11.6 moves toward the drain contact region 227, but the width of the peak becomes narrower and the electric field strength locally increases, leading to deterioration of the withstand voltage. Therefore, the value of α2 has an optimum value of 2 μm to 12 μm.
It is about m.

〔Effect of the invention〕

According to the present invention as described above, by improving the drain junction structure or the gate structure between the channel and drain, the electric field concentration that determines the withstand voltage in each part is alleviated, so that the area occupied is not increased. , the reverse blocking withstand voltage can be improved.

[Brief explanation of drawings]

FIG. 1(a) is a longitudinal cross-sectional view of one embodiment of the present invention, FIG. 1(b) is a diagram showing the electric field intensity distribution near the surface of the semiconductor substrate, and FIGS. FIG. 1 is a diagram showing the manufacturing process of the embodiment, and FIG. 3 is a longitudinal sectional view of the conventional example. 106 Depletion layer edge, 114 Channel region, 201
n-type silicon substrate, 205 deep diffusion region, 210 thick oxide film, 211 shallow diffusion region, 212 gate oxide film, 213 polysilicon gate electrode, 217 high concentration channel region, 222 source contact region,
223 channel contact region, 224 interlayer insulating film, 225 source electrode, 226 drain electrode, 227 drain contact region, 302 n-type silicon substrate, 303 polysilicon gate electrode, 304
Drain shallow diffusion region, 305 Drain contact region, 306 Depletion layer end, 307 Source contact region, 308 Channel contact region, 311 (
b) Figure 1 Figure 1

Claims (1)

[Claims] 1) A source and drain region of a second conductivity type provided on a semiconductor substrate of a first conductivity type, a channel region between the source and drain regions, and an insulating film between the source and drain regions. In the insulated gate field effect transistor, the drain region has a deep diffusion region of the second conductivity type under the drain contact region connected to the drain electrode, and a deep diffusion region of the second conductivity type that is in contact with this region. 1. An insulated gate field effect transistor comprising: a shallow diffusion region of a second conductivity type provided on a source region side; 2) In the transistor according to claim 1, the insulating film includes a gate oxide film and a thicker oxide film, and the thicker oxide film is a drain contact connected to the drain electrode on the deep diffusion region. An insulated gate field effect transistor, characterized in that it is provided between a region and the channel region. 3) An insulated gate field effect transistor according to claim 2, wherein the shallow diffusion region extends beyond the thick oxide film toward the channel region. 4) An insulated gate field effect transistor according to claim 3, wherein an end portion of the gate electrode is provided on the thick oxide film. 5) An insulated gate transistor according to any one of claims 1 to 4, characterized in that the drain region is provided in the center, and a channel region and a source region are provided surrounding it. field effect transistor. 6) A step of selectively introducing impurities of a second conductivity type into the surface of the semiconductor substrate of the first conductivity type and then diffusing them to form a deep diffusion region for a drain, and forming an impurity of the second conductivity type around the deep diffusion region. a step of introducing an impurity; a step of diffusing the impurity to form a shallow diffusion region for a drain; and a step of selectively forming a thick oxide film on the surface of the semiconductor substrate; and a step of forming a gate electrode. A step of introducing impurities of a first conductivity type using the thick oxide film and the gate electrode as a mask to form a highly concentrated channel region, and introducing an impurity of a second conductivity type for a drain contact region using the thick oxide film as a mask. Then, using the gate electrode and resist as a mask, a second conductivity type impurity is introduced for the source contact region, and using the thick oxide film and resist as a mask, a first conductivity type impurity is introduced for the channel contact region, and then diffused. A method for manufacturing an insulated gate field effect transistor, comprising the steps of: