JPS63275180A - Mos-type field effect transistor - Google Patents
Mos-type field effect transistorInfo
- Publication number
- JPS63275180A JPS63275180A JP62111811A JP11181187A JPS63275180A JP S63275180 A JPS63275180 A JP S63275180A JP 62111811 A JP62111811 A JP 62111811A JP 11181187 A JP11181187 A JP 11181187A JP S63275180 A JPS63275180 A JP S63275180A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type diffusion
- conductivity type
- layer
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯ８形電界効果トランジスタに関し、特に大
電流駆動且つ高耐圧のＭＯＳ形電界効果トランジスタに
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 field effect transistor, and particularly to a MOS field effect transistor that can drive a large current and has a high breakdown voltage.
近年、フラット・ディスプレレーパネル駆動用の高耐圧
・大電流のＩＣの要求が高まっている。In recent years, there has been an increasing demand for high voltage and large current ICs for driving flat display panels.
これらのＩＣでは１チツプに数十回路の高圧出力を有す
る場合が多く、小さな面積で大電流がとれるトランジス
ターが必要になってくる。バイポーラトランジスタはこ
の点において都合の良い素子であるが、熱暴走や消費電
流が増加する等の欠点があり、現在はＭＯ３形電界効果
トランジスタ（以下、ＭＯ’５−ＦＥＴと称す）を使う
ことが主流となっている。但し、このＭＯＳ−ＦＥＴは
単位面積当りの電流駆動能力が小さいため、二重拡散に
より短チャネルにすることなどにより電流の増加をはか
つている。These ICs often have several dozen high-voltage output circuits on a single chip, requiring transistors that can draw large currents in a small area. Bipolar transistors are convenient elements in this respect, but they have drawbacks such as thermal runaway and increased current consumption, and currently MO3 field effect transistors (hereinafter referred to as MO'5-FETs) cannot be used. It has become mainstream. However, since this MOS-FET has a small current driving capability per unit area, the current is increased by making the channel shorter by double diffusion.
第２図はかかる従来の二重拡散ＭＯ８−ＦＥＴの断面図
である。FIG. 2 is a cross-sectional view of such a conventional double-diffused MO8-FET.
第２図に示すように、このＭＯＳ−Ｆ’ＥＴはｐ型半導
体基板２１上に形成されたｎ＋＋埋込層２２と、エピタ
キシャル成長法を用いて前記埋込層２２上に形成された
ｎ−型エピタキシャル層２３と、前記ｎ−型エピタキシ
ャル層２３の表面から前記ｎ＋＋埋込層２２に接続して
低抵抗でドレインを表面に引き出すｎ＋型押込層２４と
、前記エピタキシャル層２３の表面絶縁層にあけられた
窓を通して形成されたｐ−型拡散層２７および前記窓を
通して形成されたｎ＋型型数散層２８、ｐ−型拡散層２
７とｎ＋型型数散層２８にまたがって形成されたソース
電極２９と、前記ｎ＋型扼込層２４上に形成されたドレ
イン電極３０とからなる。前記ゲート電極２６はｎ＋型
型数散層２８外側のｐ拡散層２７の表面に形成される。As shown in FIG. 2, this MOS-F'ET consists of an n++ buried layer 22 formed on a p-type semiconductor substrate 21 and an n-type buried layer 22 formed on the buried layer 22 using an epitaxial growth method. The epitaxial layer 23, the n+ type buried layer 24 which connects the surface of the n- type epitaxial layer 23 to the n++ buried layer 22 and brings out the drain to the surface with low resistance, and the surface insulating layer of the epitaxial layer 23 are formed. The p-type diffusion layer 27 formed through the window, the n+ type scattering layer 28 formed through the window, and the p-type diffusion layer 2
7 and the n+ type scattering layer 28, and a drain electrode 30 formed on the n+ type intrusion layer 24. The gate electrode 26 is formed on the surface of the p diffusion layer 27 outside the n+ type scattering layer 28.
なお、３１は表面保護用絶縁膜である。Note that 31 is an insulating film for surface protection.
かかる構造のＭＯＳ−ＦＥＴにおいて、チャネル長はｐ
−型拡散層２７とｎ＋型型数散層２８横方向の拡散長の
違いにより決定され、短いチャネル長が形成し得る。ま
た、高耐圧化については、ｎ−型エピタキシャル層２３
を厚くしなり比抵抗を高くすることにより実現すること
が可能である。In a MOS-FET with such a structure, the channel length is p
This is determined by the difference in the lateral diffusion lengths of the − type diffusion layer 27 and the n+ type diffusion layer 28, and a short channel length can be formed. In addition, for high breakdown voltage, the n-type epitaxial layer 23
This can be achieved by increasing the bending thickness and increasing the specific resistance.
しかしながら、かかる構造の二重拡散ＭＯ８−ＦＥＴは
半導体基板に埋込層の形成やエピタキシャル層の成長等
が必要であること、および工程が多く複雑であることな
どから歩留りが低く高価となる欠点があった。However, the double-diffused MO8-FET with this structure requires the formation of a buried layer in the semiconductor substrate, the growth of an epitaxial layer, etc., and has many complicated steps, resulting in a low yield and high cost. there were.
本発明の目的は、エピタキシャル層や埋込層等を必要と
せずに、基板上に直接素子を形成する工程を簡単で安価
に実施できるとともに、大電流且つ高耐圧が得られるＭ
ＯＳ−ＦＥＴを提供することにある。An object of the present invention is to enable a simple and inexpensive process of forming elements directly on a substrate without requiring an epitaxial layer or a buried layer, and to provide a M
Our goal is to provide OS-FETs.
本発明のＭＯＳ−ＦＥＴは、チャネル部を二重拡散構造
にすることにより大電流を取り出し、且つドレイン部を
オフセットゲート構造にすることにより電界強度を緩和
して高耐圧とするものである。The MOS-FET of the present invention has a double diffusion structure in the channel portion to extract a large current, and has an offset gate structure in the drain portion to reduce electric field strength and achieve a high breakdown voltage.
すなわち、本発明のＭＯＳ−ＦＥＴは、−導電型の半導
体基板上にゲート絶縁膜を介して形成されるゲート電極
と、前記半導体基板上に形成した表面絶縁層にあけられ
た窓を通してイオン注入により形成される第一の一導電
型拡散層と、この第一の一導電型拡散層内に形成される
高濃度な第二の一導電型拡散層および高濃度な第一の逆
導電型拡散層と、前記第二の一導電型拡散層と前記第一
の逆導電型拡散層とにまたがって形成されるソース電極
と、前記半導体基板の表面絶縁層にあけられた異なる窓
を通してイオン注入により形成される第二の逆導電型拡
散層と、この逆導電型拡散層内に形成される高濃度な第
三の逆導電型拡散層−５＝
と、前記第二および第三の逆導電型拡散層にまたがって
形成されるドレイン電極とを含み、前記ゲート電極は前
記第一の逆導電型拡散層の外側に残された前記第一の一
導電型拡散層の表面および前記第二の逆導電型拡散層の
表面とにまたがって形成されるように構成される。That is, the MOS-FET of the present invention has a gate electrode formed on a -conductivity type semiconductor substrate via a gate insulating film, and a window formed in a surface insulating layer formed on the semiconductor substrate by ion implantation. A first one-conductivity type diffusion layer to be formed, a second highly concentrated one-conductivity type diffusion layer formed within this first one-conductivity type diffusion layer, and a first highly concentrated opposite-conductivity type diffusion layer. and a source electrode formed across the second one conductivity type diffusion layer and the first opposite conductivity type diffusion layer, and a source electrode formed by ion implantation through different windows formed in the surface insulating layer of the semiconductor substrate. a second reverse conductivity type diffusion layer formed in this reverse conductivity type diffusion layer, a third high concentration reverse conductivity type diffusion layer -5= formed in this reverse conductivity type diffusion layer, and the second and third opposite conductivity type diffusion layers. a drain electrode formed across the layers, and the gate electrode includes a surface of the first one conductivity type diffusion layer left outside the first reverse conductivity type diffusion layer and the second reverse conductivity type diffusion layer. The mold diffusion layer is formed so as to span the surface of the mold diffusion layer.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するためのＭＯＳ−Ｆ
ＥＴの断面図である。FIG. 1 shows a MOS-F for explaining one embodiment of the present invention.
It is a sectional view of ET.
第１図に示すように、ｐ型半導体基板１上にシリコン酸
化膜などのゲート絶縁膜２を形成し、この上にゲート電
極３を形成する。しかる後、半導体基板１の表面絶縁膜
にあけられた窓を通してイオン注入法などによりｐ−型
拡散層４を形成する。次に、前記窓により小さいマスク
を用いてｐ”型拡散層５およびｎ＋型型数散層６それぞ
れイオン注入法などで形成する。ここでゲート電極３の
直下のｐ−型拡散層４とｎ＋型型数散層６横方向の拡が
りの差がチャネル７となる。このチャネル７の長さを調
整することにより電流値を変えることができる。また、
半導体基板１上で異なる部分の表面絶縁膜にあけられた
窓を通してイオン注入などによりｎ−型拡散層８を形成
し、続いて同じ窓より一回り小さいマスクを用いてイオ
ン注入などによりｎ“拡散層９を形成する。これがいわ
ゆるオフセットゲート構造であり、ゲート電極３の直下
の前記ｎ−型拡散層８の濃度および横方向の長さを調整
することにより耐圧を制御することができる。次に、ゲ
ート電［ｉ３以外の電極領域を除き、シリコン酸化膜な
どの絶縁膜１ｏを基板上に被覆し、しかる後ｐ＋型型数
散層とｎ＋型型数散層６またがってソース電極１１を形
成するとともに、ｎ−型拡散層８とｎ＋型型数散層９ま
たがってドレイン電極１２を形成する。更に、こ°こに
は図示してないがこれら電極上部から保護絶縁膜等を被
覆してＭＯＳ−ＦＥＴを完成させている。As shown in FIG. 1, a gate insulating film 2 such as a silicon oxide film is formed on a p-type semiconductor substrate 1, and a gate electrode 3 is formed thereon. Thereafter, a p-type diffusion layer 4 is formed by ion implantation or the like through a window made in the surface insulating film of the semiconductor substrate 1. Next, using a mask smaller than the window, a p" type diffusion layer 5 and an n+ type diffused layer 6 are formed by ion implantation or the like. Here, the p" type diffusion layer 4 directly under the gate electrode 3 and the n+ The difference in the lateral spread of the type scattering layer 6 becomes a channel 7. By adjusting the length of this channel 7, the current value can be changed.
An n-type diffusion layer 8 is formed by ion implantation or the like through windows made in the surface insulating film at different parts of the semiconductor substrate 1, and then an n-type diffusion layer 8 is formed by ion implantation or the like using a mask that is one size smaller than the same window. A layer 9 is formed. This is a so-called offset gate structure, and the withstand voltage can be controlled by adjusting the concentration and lateral length of the n-type diffusion layer 8 directly under the gate electrode 3.Next, , Gate electrode [Excluding electrode regions other than i3, an insulating film 1o such as a silicon oxide film is coated on the substrate, and then a source electrode 11 is formed across the p+ type scattering layer and the n+ type scattering layer 6. At the same time, a drain electrode 12 is formed across the n-type diffused layer 8 and the n+-type diffused layer 9.Furthermore, although not shown here, a protective insulating film or the like is coated from above these electrodes. Completed MOS-FET.
かかる構造をとることにより、所定の電流値および耐圧
値を得ることができる。By adopting such a structure, a predetermined current value and breakdown voltage value can be obtained.
尚、上記実施例はｐ型基板を一導電型の例として説明し
たが、逆導電型のｎ型基板を用いてもまったく逆の対応
とすることにより同様に本発明を実現できることは言う
までもない。Although the above embodiment has been described using the p-type substrate as an example of one conductivity type, it is needless to say that the present invention can be similarly realized even if an n-type substrate of the opposite conductivity type is used in the completely opposite manner.
以上説明した様に、本発明はゲート電極直下に形成する
チャネルの長さを可変することにより所望の電流値を得
ることができ、且つドレイン電極直下のｎ−型拡散層の
濃度および長さを可変することにより所望の耐圧値を得
ることができ、比較的簡単にＭＯＳ−ＰＥＴの特性値を
得られる効果がある。As explained above, the present invention makes it possible to obtain a desired current value by varying the length of the channel formed directly under the gate electrode, and also by changing the concentration and length of the n-type diffusion layer directly under the drain electrode. By varying it, a desired breakdown voltage value can be obtained, and the characteristic values of MOS-PET can be obtained relatively easily.
第１図は本発明の一実施例を説明するためのＭＯＳ−Ｆ
ＥＴの断面図、第２図は従来の一例を説明するためのＭ
ＯＳ−ＦＥＴの断面図である。
１・・・ｐ型半導体基板、２・・・ゲート絶縁膜、３・
・・ゲート電極、４・・・ｐ−型拡散層、５・・・ｐ＋
型型数散層６・・・ｎ＋型型数散層７・・・チャネル、
８・・・ｎ型拡散層、９・・・ｎ＋型型数散層１０・・
・絶縁膜、１１・・・ソース電極、１２・・・ドレイン
電極。FIG. 1 shows a MOS-F for explaining one embodiment of the present invention.
A cross-sectional view of ET, Figure 2 is an M for explaining a conventional example.
It is a sectional view of OS-FET. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2... gate insulating film, 3...
...gate electrode, 4...p- type diffusion layer, 5...p+
Type type scattered layer 6...n+ type type scattered layer 7...channel,
8...n-type diffusion layer, 9...n+ type scattering layer 10...
- Insulating film, 11...source electrode, 12...drain electrode.
Claims (1)
れるゲート電極と、前記半導体基板上に形成した表面絶
縁層にあけられた窓を通してイオン注入により形成され
る第一の一導電型拡散層と、この第一の一導電型拡散層
内に形成される高濃度な第二の一導電型拡散層および高
濃度な第一の逆導電型拡散層と、前記第二の一導電型拡
散層と前記第一の逆導電型拡散層とにまたがって形成さ
れるソース電極と、前記半導体基板の表面絶縁層にあけ
られた異なる窓を通してイオン注入により形成される第
二の逆導電型拡散層と、この逆導電型拡散層内に形成さ
れる高濃度な第三の逆導電型拡散層と、前記第二および
第三の逆導電型拡散層にまたがって形成されるドレイン
電極とを含み、前記ゲート電極は前記第一の逆導電型拡
散層の外側に残された前記第一の一導電型拡散層の表面
および前記第二の逆導電型拡散層の表面とにまたがって
形成されることを特徴とするＭＯＳ形電界効果トランジ
スタ。A gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, and a first diffusion of one conductivity type formed by ion implantation through a window made in a surface insulating layer formed on the semiconductor substrate. a highly concentrated second monoconductive type diffusion layer formed within the first monoconductive type diffusion layer, a highly concentrated first opposite conductivity type diffusion layer, and the second monoconductive type diffusion layer. a second reverse conductivity type diffusion layer formed by ion implantation through different windows formed in the surface insulating layer of the semiconductor substrate; and a highly concentrated third reverse conductivity type diffusion layer formed within the reverse conductivity type diffusion layer, and a drain electrode formed across the second and third opposite conductivity type diffusion layers, The gate electrode is formed to straddle the surface of the first one conductivity type diffusion layer left outside the first reverse conductivity type diffusion layer and the surface of the second reverse conductivity type diffusion layer. A MOS field effect transistor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111811A JPS63275180A (en) | 1987-05-07 | 1987-05-07 | Mos-type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62111811A JPS63275180A (en) | 1987-05-07 | 1987-05-07 | Mos-type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63275180A true JPS63275180A (en) | 1988-11-11 |
Family
ID=14570753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62111811A Pending JPS63275180A (en) | 1987-05-07 | 1987-05-07 | Mos-type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63275180A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02244640A (en) * | 1989-03-16 | 1990-09-28 | Fuji Electric Co Ltd | Insulated-gate field-effect transistor and manufacture thereof |
-
1987
- 1987-05-07 JP JP62111811A patent/JPS63275180A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02244640A (en) * | 1989-03-16 | 1990-09-28 | Fuji Electric Co Ltd | Insulated-gate field-effect transistor and manufacture thereof |
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