JPH02240746A - Collection system for control information on information controller - Google Patents

Abstract

PURPOSE:To surely obtain the effective data by instructing the stop of the working of a processor as long as a logic state is secured for a specific hardware signal. CONSTITUTION:A processor 21 decodes a received command and recognizes that the decoded command is the same as the one that controls a comparator 22 for hardware signal state. Thus the processor 21 transmits the instruction (comparison conditions) of the command to the circuit 22 via a control bus signal line 201. The circuit 22 receives the command and starts the comparison between the logic states of data on the hardware signal lines 204 - 207 and the given conditions. When the data on the lines 204 - 207 satisfy those given conditions, the interruption of working is instructed to a clock supply circuit 23 via a control signal line 202. Thus the control information or the working state, etc., of an information processor can be easily collected at a time point near the occurrence of a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to an improvement of an information processing device, and particularly relates to a control information collection method for troubleshooting.

(Prior Art) Conventionally, in this type of information processing device, in order to analyze a failure, a processor in the information processing device that controls the operation is stopped under certain conditions and the operation history or You may want to collect other control information. In such a case, the moment the execution address of the firmware matches the pre-specified address, the clock supply to the processor is interrupted, the processor operation is stopped, and the control information of the information processing device at that point is We were able to collect data for failure analysis.

FIG. 2 is a block diagram illustrating an example of a control information collection method for an information processing apparatus according to the prior art. In Figure 2,
10 is a diagnostic command input device, 20 is an information processing device, 2
1 is a processor, 23 is a clock supply circuit, 24 is a diagnostic command receiving circuit,! 6 is an execution address comparison circuit.

(Problems to be Solved by the Invention) In the conventional control information employing method described above, an instruction to suspend operation to a clock supply circuit is issued by an execution address comparison circuit of firmware.

For example, if you want to instruct the processor to stop using a change in the state of a specific hardware signal as a trigger, the process will be executed until the address of a microinstruction that clearly indicates that the change in the state of the hardware signal has been recognized by the firmware is executed. Unable to instruct processor to stop. As a result, there is a time delay between the time when the state of the hardware signal changes and the time when the processor actually stops, making it difficult to obtain accurate information, or the change in the hardware signal being processed by the firmware. Sometimes the hardware configuration becomes unrecognizable. In such a case, there is a drawback that the processor cannot be stopped using this as a trigger.

An object of the present invention is to provide a diagnostic command to a processor from the outside, compare the states of hardware signals within an information processing device based on instructions given via the diagnostic command from an operator, and supply a clock based on the comparison result. It is an object of the present invention to provide a method for collecting control information for an information processing device, which eliminates the above-mentioned drawbacks by instructing to stop the operation, and is configured to reliably stop the operation of the processor when necessary.

(Means for Solving the Problems) A control information collection method for an information processing device according to the present invention is configured to include a processor, a diagnostic command receiving circuit, a clock supply circuit, and a hardware signal state comparison circuit. It is.

The processor is controlled by firmware and is responsible for controlling information on the bus.

The diagnostic command receiving circuit is for receiving diagnostic commands given by the operator.

The clock supply circuit is for supplying an operating clock to the processor.

The hardware signal state comparison circuit sets the comparison conditions for the hardware signals using a diagnostic command and instructs the start of the comparison operation, and in accordance with the above instructions, compares the states of the plurality of hardware signals to be compared with the above comparison conditions. , to instruct the clock supply circuit to interrupt the clock supply operation based on the above comparison result, and to stop the processing of the processor.

(Implementation row) Next, the fifth invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one implementation of a control information collection method for an information processing apparatus according to the present invention.

In FIG. 1, 10 is a diagnostic command input device, 20 is an information processing device that adopts the control information collection method according to the present invention, and 2
1 is a processor, 22 is a hardware signal state comparison circuit,
26 is a clock supply circuit, and 24 is a diagnostic command receiving circuit.

In this process, the states of the four signals on the hardware signal lines 204 to 207 can be compared.

The detailed operation of this embodiment will be described below by listing cases in which the processor 21 is stopped when the data on the hardware signal lines 204 to 207 are in the logic (1010) state.

It is assumed that data is sent from the diagnostic command input device 10 to the information processing device 20 in operation via the command input bus signal line 101. This data is sent to logic (1010) on hardware signal lines 204-207! When this happens, a command to output a stop instruction to the clock supply circuit 23 is issued. Upon receiving the above command, the diagnostic command receiving circuit 24 in the information processing device [2G]
The command is transmitted to the processor 21 via a command bus signal 9208.

When the processor 21 decodes the received command and recognizes that this command is a command to control the hardware signal state comparison circuit 22, it sends the command to the hardware signal state comparison circuit 22 via the control bus signal a201. to transmit command instructions (comparison conditions). When the No. 1 hardware signal state comparison circuit 22 receives the command, it starts comparing the logical state of the data on the No. 1 hardware signal lines 204 to 207 with the conditions given by the command. When the data on the hardware signal lines 204 to 20T satisfy the above conditions, the clock supply circuit 23 is instructed to suspend operation via the control signal line 202. When the clock supply circuit 23 receives the above-mentioned interruption instruction, it stops the processing of the processor 21 by interrupting the output of the clock to the clock signal line 20S.

(Effects of the Invention) As explained above, the present invention makes it possible to instruct the processor to stop processing based on the logical state of a specific hardware signal, thereby providing information in the vicinity of the time of failure during failure detection. The control information or operating status of the processing device can be easily collected, and effective data can be obtained accurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a control information collection method for an information processing apparatus according to the present invention. FIG. 2 is a block diagram illustrating an example of a control information collection method for an information processing apparatus according to the prior art. 10 Fist @ Φ Diagnostic command input device 20 / Fist / Information processing device 21 ・ 22 ・ 23 ・ 24 ・ 25 ・ Processor hardware signal status comparison circuit Clock supply circuit Diagnostic command reception circuit Execution address comparison circuit 01~208,301~! 05--...Signal line

Claims (1)

[Claims] a processor controlled by firmware for controlling information on the bus; a diagnostic command receiving circuit for receiving diagnostic commands given from an operator; a clock supply circuit for supplying an operating clock to the processor; A diagnosis command sets comparison conditions for hardware signals and instructs the start of a comparison operation. According to the instruction, the states of a plurality of compared hardware signals are compared with the comparison conditions, and the comparison result determines the clock signal. Instructs the supply circuit to interrupt clock supply operation,
1. A control information collection method for an information processing device, comprising: a hardware signal state comparison circuit for stopping processing of the processor.