JPH02238631A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02238631A JPH02238631A JP5890289A JP5890289A JPH02238631A JP H02238631 A JPH02238631 A JP H02238631A JP 5890289 A JP5890289 A JP 5890289A JP 5890289 A JP5890289 A JP 5890289A JP H02238631 A JPH02238631 A JP H02238631A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- type
- base
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000463 material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 24
- 230000008569 process Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 4
- 230000003321 amplification Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 238000009776 industrial production Methods 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 229910004012 SiCx Inorganic materials 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 239000013078 crystal Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- -1 Cjr and Mo Chemical class 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、ワイドギャノプエミッタを有ずる高性能(高
速)な半樽体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high performance (high speed) half barrel device having a wide ganope emitter.
[従来の技術]
近年、分子線エビタキシー(MBE)法などにより、異
種半導体による接合、即ちヘテロ接合を利用した半導体
累子の開発が盛んに行われるようになった。ワイドギャ
ソブエミッタを持っヘテロ接合バイポーラトランジスタ
(以下、HBTと呼フ)ハ、エミッタ注入効率の高さや
、ベースの不純物濃度を通常よりも高《設定できること
からベース抵抗等の寄生素子が小さくなり高速な動作を
実現できる点などがらも、特に研究が活発であるHBT
において、ベース・エミッタ接合部においてバンドギャ
ップが階段状に変化している場合に形成されるスパイク
状の障壁は、エミッタからベースへの電子の注入を1且
害する。このようにしてエミッタの注入効率が低下する
とトランジスタ性能の低下を招いてしまうことから、ベ
ース・エミッタ接合部においてバンドギャップが連続的
に変化する方法が提案された。さらに、ベース領域での
キャリアの走行時間がトランジスタの高速化に太き《寄
与することから、ベース・エミッタ接合部のみでなく、
ベース領域においてもバンドギャップを連続的に変化さ
せ(傾斜させ)だ構芦を持つ高性能なHB’[’が提案
された。(第3図)第6図(a)はベース・エミソタ接
合部及びベース領域のバンドギャップを連続的に変化さ
せた構造のnpn型HBTの槻念図で、第3図(b)は
そのバンド図である。[Prior Art] In recent years, semiconductor junctions using heterojunctions, ie, junctions made of different semiconductors, have been actively developed using methods such as molecular beam epitaxy (MBE). Heterojunction bipolar transistors (hereinafter referred to as HBTs) with wide gas emitters have high emitter injection efficiency and can set the base impurity concentration higher than usual, which reduces parasitic elements such as base resistance and enables high speed operation. HBT, which is the subject of particularly active research, is capable of achieving
In this case, the spike-like barrier formed when the bandgap is stepped at the base-emitter junction impairs the injection of electrons from the emitter to the base. Since this reduction in emitter injection efficiency leads to a reduction in transistor performance, a method has been proposed in which the bandgap changes continuously at the base-emitter junction. Furthermore, since carrier transit time in the base region greatly contributes to speeding up the transistor,
A high-performance HB'[' has been proposed that has a structure in which the bandgap is continuously changed (tilted) even in the base region. (Fig. 3) Fig. 6 (a) is a conceptual diagram of an npn-type HBT with a structure in which the band gap of the base-emitter junction and the base region is continuously changed, and Fig. 3 (b) is a conceptual diagram of the band gap of the base-emitter junction and the base region. It is a diagram.
[発明が解決しようとする課題]
しかし、このように滑らかなバンドギャップの変化を実
現するためには、MBE法においては分子線のフランク
スを、MOCvD法ではガスの流量を精密に制御しなげ
ればならず、製造装置の制御は非常な困鍵を伴い、工業
生産性(量産性)に欠ける。[Problem to be solved by the invention] However, in order to achieve such a smooth band gap change, it is necessary to precisely control the flanks of the molecular beam in the MBE method and the gas flow rate in the MOCvD method. However, controlling manufacturing equipment is extremely difficult, and industrial productivity (mass production) is lacking.
[課題を解決するための手段]
本発明の半導体装置は、第1導電型を有する第1半導体
によるベース領域と、第2導電型を有し前記第1半導体
よりバンドギャソプの広い第2半導体によるエミッタ領
域を有し、かつ前記エミッタ領域から前記ベース領域の
コレクタ端に向かってバンドギャソプが順次階段状に小
さくなる複数の半導体物質層から成ることを特徴とする
。[Means for Solving the Problems] A semiconductor device of the present invention includes a base region made of a first semiconductor having a first conductivity type, and an emitter made of a second semiconductor having a second conductivity type and having a wider band gap than the first semiconductor. The semiconductor device is characterized in that it comprises a plurality of semiconductor material layers having a region and a band width gradually decreasing from the emitter region to the collector end of the base region.
[実施例] 以下にその実施例に従って本発明を説明する。[Example] The present invention will be explained below according to the examples.
第1図は本発明の半導体装置を応用したnpn型HB’
Tの実施例である。101ぱ低抵抗のn型単結晶Si基
板で、その上にMBE法を用いてn創の単結晶Si膜を
形成しコレクタ領域102とする。その上にMBK法を
用いてp型のSiOx膜を三層形成しベース103とす
る。さらに表面に減圧CvD法を用いてS102の絶縁
層105を形成し、エミッタ領域用の窓をフォトエッチ
ェ程によって形成した後、再びMBE法を用いてn型の
SiC!x膜を三層形成しフォトエッチ工程によりエミ
ソタ104を形成する。次にスパッタ法を用いてS10
2の絶縁層106を形成し、フォトエッチ工程によりベ
ース電極及びエミッタtl’M用の窓を形成した後、ス
パッタ法により表面にA7膜を形成し、フォトエッチ工
程によりベース電極108及びエミッタ電極109を形
成する。Figure 1 shows an npn type HB' to which the semiconductor device of the present invention is applied.
This is an example of T. 101 is a low-resistance n-type single-crystal Si substrate, and a collector region 102 is formed by forming an n-hole single-crystal Si film thereon using the MBE method. Three layers of p-type SiOx films are formed thereon using the MBK method to form a base 103. Furthermore, an insulating layer 105 of S102 is formed on the surface using the low pressure CvD method, and a window for the emitter region is formed using a photoetching process, and then an n-type SiC! Three layers of x films are formed, and an emitter 104 is formed by a photo-etching process. Next, using the sputtering method, S10
After forming the insulating layer 106 of No. 2 and forming a window for the base electrode and emitter tl'M by a photo-etching process, an A7 film is formed on the surface by a sputtering process, and a base electrode 108 and an emitter electrode 109 are formed by a photo-etching process. form.
最後に基板裏側にスパッタ法によりA7膜のコレクタ電
極107を形成する。Finally, a collector electrode 107 of A7 film is formed on the back side of the substrate by sputtering.
ベース層のp型S i− O xの組成の炭素含有比X
は、コレクタ側からx=o ,x,,x2に、エミッタ
層のn型SiOxにおいてはベース側から順にx=x3
, 4 ,r,とする。(第2図(b))ここでxi
( i=1〜5)は0〈x1〈x2〈x 3 ( x
4 < x H < 1という関係にある。第2図(α
)は第1図の実施例におけるバンド図であるバンド図か
らわかるように、階段状傾斜接合を用いると、各層の界
面には障壁が形成されるが、その高さは単に階段状接合
を形成した場より十分小さ《なっている。Carbon content ratio X of the composition of p-type Si-Ox in the base layer
are x=o, x, , x2 from the collector side, and x=x3 from the base side in the n-type SiOx emitter layer.
, 4, r. (Figure 2(b)) where xi
(i=1~5) is 0〈x1〈x2〈x3 (x
The relationship is 4 < x H < 1. Figure 2 (α
) is the band diagram for the embodiment shown in Figure 1. As can be seen from the band diagram, when a step-like inclined junction is used, a barrier is formed at the interface of each layer, but the height of the barrier is simply the same as the step-like junction. It is much smaller than the place where it was.
また、傾斜接合を複数の階段状接合(階段状傾斜接合)
で形成することは、HBTを作製する際のプロセスの負
担を大きく減らして《れる。物質組成を滑らかに変化さ
せようとすると半導体層形成時の成長条件を精密に制御
することが必要である上、成長速度を十分に小さくする
必要がある。In addition, it is possible to convert sloped joints into multiple stepped joints (stepped sloped joints).
Forming the HBT can greatly reduce the burden of the process when manufacturing the HBT. In order to smoothly change the material composition, it is necessary to precisely control the growth conditions during the formation of the semiconductor layer, and it is also necessary to keep the growth rate sufficiently low.
しかし、複数の階段状の組成変化で置き換える場合には
、はるかに制圀1が容易になり、成長速度を太き《する
ことができ、結果として生産のスルーブットが著し《向
上することとなる。However, when replacing it with multiple step-like compositional changes, it becomes much easier to control the area and increase the growth rate, resulting in a significant improvement in production throughput. .
ベース及びコレクタ層の層数は複数であれば良《、多い
ほど各層の界面でのバンドギャップの差を小さくできる
が、多過ぎては工程上不利になるので2〜10程度が最
適である。The number of layers of the base and collector layers may be plural. The larger the number, the smaller the difference in band gaps at the interfaces between the layers, but if there are too many, it will be disadvantageous in terms of the process, so the optimum number is about 2 to 10.
本発明は縦型のみならず横型バイボーラトランジスタに
も応用可能である。The present invention is applicable not only to vertical type bibolar transistors but also to horizontal type bibolar transistors.
本実施例においては、MBE法を用いて単結晶S1及び
SiC!x膜を形成しているが、減圧または常圧のOV
D法等の気相成長法を用いてもよ《、他にも液相成長や
、プラズマOVD法によって非単結晶膜を形成したのち
に固相成長させる等の方法も可能である。また、絶縁層
としてSin,,膜を用いているがSiNx等を用いて
も良《、成lm方法としても他にプラズマCvD法や光
OVD法等が可能である。電極としても、AI−の他に
Cjr,Mo等の金属やシリザイド等が可能であり、形
成方法も蒸着等を用いることが可能である。In this example, single crystal S1 and SiC! x film is formed, but OV at reduced pressure or normal pressure
A vapor phase growth method such as the D method may be used, and other methods such as liquid phase growth or solid phase growth after forming a non-single crystal film by a plasma OVD method are also possible. Further, although a Sin film is used as the insulating layer, SiNx or the like may also be used.Also, plasma CVD method, optical OVD method, etc. may be used as a method for forming the film. As for the electrode, other than AI-, metals such as Cjr and Mo, silicide, etc. can be used, and the forming method can be vapor deposition or the like.
第4図は本発明の半導体装置を用いてO M L l(
Current Mode Logic ) 回路を
作製した実施例である。本発明の半導体を用いることに
よって高速な論理素子を工業的に安定に供給することが
できる。デジタル回路ばかりではな《アナログ回路にお
いても同様である。FIG. 4 shows O M L l (
This is an example in which a Current Mode Logic (Current Mode Logic) circuit was created. By using the semiconductor of the present invention, high-speed logic elements can be stably supplied industrially. This applies not only to digital circuits, but also to analog circuits.
本発明の半導体装置とCMOS回路を組合わせることに
よって、高性能なBiOMOS (HBTCMOS)回
路を工業的に安定に供給することができる。By combining the semiconductor device of the present invention and a CMOS circuit, a high-performance BiOMOS (HBTCMOS) circuit can be stably supplied industrially.
本発明の半導体装置を絶縁基板もし《は絶縁層上に形成
することも可能である。この場合には第1図の実施例の
ようなエミッタトップ型ばかりでなくコレクタトソプ型
も可能になる。さらに素子分離が容易になり、また三次
元素子への応用も可能になることから、高速演算装置、
画像装置等幅広い分野における応用が可能となる。It is also possible to form the semiconductor device of the present invention on an insulating substrate or an insulating layer. In this case, not only the emitter top type as in the embodiment shown in FIG. 1 but also the collector top type are possible. Furthermore, element separation becomes easier and application to tertiary elements becomes possible, so high-speed arithmetic devices,
Application in a wide range of fields such as imaging devices becomes possible.
以上、半導体としてSiOxを用いた例について述べて
きたが、Si,Ge等の元素半導体を用いても良いし、
GaAs,InP等の化合物半導体を用いても良い。ま
た、非単結晶半導体を用いてバンドギャノブを変化させ
ても良い。またnpn型について述べてきたがpnp型
でも良い。Above, we have described an example using SiOx as a semiconductor, but elemental semiconductors such as Si and Ge may also be used.
Compound semiconductors such as GaAs and InP may also be used. Furthermore, the bandgain knob may be changed using a non-single crystal semiconductor. Further, although the npn type has been described, a pnp type may also be used.
[発明の効果]
以上述べてきたように、本発明の半導体装置を用いるこ
とによって、工業生産的に十分なスルーブットを保ちな
がら、高増幅率と良好な高周波特性を備えたHBTを形
成することが可能となる。[Effects of the Invention] As described above, by using the semiconductor device of the present invention, it is possible to form an HBT with a high amplification factor and good high frequency characteristics while maintaining sufficient throughput for industrial production. It becomes possible.
第1図は本発明の実施例に示した半導体装置のPNP型
トランジスタの断面図。
第2図(a),(b)は第1図の実施例のバンド図及び
炭素混入世の図。
第6図( +7. ), ( b ’Iは従来例の概念
図及びバンド図。
第4図は本発明の半導体装置を用いてOML回路を作製
した実施例の図。
101・・・・・・・・n型単結晶81基板102,2
03,303・・・・・・コレクタ103,202,3
02・・・・・・ベース104,201,401・・・
・・・エミッタ105,106 ・・・・・・
絶縁層107・・・・・・・・・コレクタ電極108・
・・・・・・・・ヘース電極
109・・・・・・・・・エミッタ電極604・・・・
・・・・・ベース・エミッタ傾斜接合605・・・・・
・・・・傾斜ヘース
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴木喜三郎(他1名)第1図
(a)
第2図
(b)
第2図
301エミヅタ
30)ベース
ノI3コレクタ
(a)
(b)
第3図FIG. 1 is a sectional view of a PNP type transistor of a semiconductor device shown in an embodiment of the present invention. FIGS. 2(a) and 2(b) are a band diagram and a carbon-mixed diagram of the embodiment shown in FIG. 1. Fig. 6 (+7.), (b'I is a conceptual diagram and band diagram of a conventional example. Fig. 4 is a diagram of an example in which an OML circuit is manufactured using the semiconductor device of the present invention. 101... ...N-type single crystal 81 substrate 102, 2
03,303...Collector 103,202,3
02... Base 104, 201, 401...
・・・Emitter 105, 106 ・・・・・・
Insulating layer 107...Collector electrode 108.
...Heath electrode 109 ...Emitter electrode 604 ...
...Base-emitter inclined junction 605...
...Grand Heas and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kisaburo Suzuki (and one other person) Figure 1 (a) Figure 2 (b) Figure 2 301 Ivy 30) Baseno I3 collector (a) ( b) Figure 3
Claims (1)
2導電型を有し前記第1半導体よりもバンドギャップの
広い第2半導体によるエミッタ領域を有し、かつ前記エ
ミッタ領域から前記ベース領域のコレクタ端に向かって
バンドギャップが順次階段状に小さくなる複数の半導体
物質層から成ることを特徴とする半導体装置。a base region made of a first semiconductor having a first conductivity type; and an emitter region made of a second semiconductor having a second conductivity type and having a wider bandgap than the first semiconductor; 1. A semiconductor device comprising a plurality of semiconductor material layers whose band gaps gradually decrease toward a collector end.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5890289A JPH02238631A (en) | 1989-03-10 | 1989-03-10 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5890289A JPH02238631A (en) | 1989-03-10 | 1989-03-10 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02238631A true JPH02238631A (en) | 1990-09-20 |
Family
ID=13097736
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5890289A Pending JPH02238631A (en) | 1989-03-10 | 1989-03-10 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02238631A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5739062A (en) * | 1994-03-04 | 1998-04-14 | Mitsubishi Denki Kabushiki Kaisha | Method of making bipolar transistor |
KR100332643B1 (en) * | 1999-09-20 | 2002-04-17 | 이택렬 | semiconductor device |
WO2002075814A1 (en) * | 2001-03-13 | 2002-09-26 | Nec Corporation | Bipolar transistor |
-
1989
- 1989-03-10 JP JP5890289A patent/JPH02238631A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5739062A (en) * | 1994-03-04 | 1998-04-14 | Mitsubishi Denki Kabushiki Kaisha | Method of making bipolar transistor |
KR100332643B1 (en) * | 1999-09-20 | 2002-04-17 | 이택렬 | semiconductor device |
WO2002075814A1 (en) * | 2001-03-13 | 2002-09-26 | Nec Corporation | Bipolar transistor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3299807B2 (en) | Heterojunction bipolar transistor | |
JP2002270615A (en) | Heterojunction bipolar transistor having improved emitter-base junction, and method for manufacturing the transistor | |
JPH04233736A (en) | Compound semiconductor device | |
JPH02238631A (en) | Semiconductor device | |
JP2002359249A (en) | Compound semiconductor device and manufacturing method therefor | |
JPH02219234A (en) | Semiconductor device | |
JPH0314240A (en) | Heterojunction bipolar transistor | |
JP2770583B2 (en) | Method of manufacturing collector-top heterojunction bipolar transistor | |
JP2557613B2 (en) | Heterojunction bipolar transistor | |
JPS61123178A (en) | Hetero-junction bipolar transistor | |
JP3183882B2 (en) | Heterojunction bipolar transistor | |
JPS61292365A (en) | Hetero-junction bipolar transistor | |
JPH05129322A (en) | Manufacture of semiconductor device | |
JPH0574796A (en) | Transistor and manufacture thereof | |
JPS6216569A (en) | Hetero-junction transistor and its manufacture | |
JPH05243253A (en) | Semiconductor device | |
JPS63127528A (en) | Semiconductor device and manufacture thereof | |
JPH03125476A (en) | Hetero junction bipolar transistor | |
JP2801646B2 (en) | Heterojunction bipolar transistor | |
JP2518347B2 (en) | Method for manufacturing bipolar transistor | |
JPS6225454A (en) | Semiconductor device | |
JPS63245958A (en) | Hetero junction bipolar transistor | |
JPS63250174A (en) | Hetero-junction type bipolar transistor | |
JPH08330240A (en) | Preparation of semiconductor epitaxial growth layer | |
JP2001028373A (en) | Heterojunction bipolar transistor |