JPH02238538A - Abnormality detecting system for multi-port memory - Google Patents

Abstract

PURPOSE:To prevent the malfunctions which are caused when the data are written and read and at the same time to attain plural retrying operations by inhibiting the transmission of data to other systems when a certain system has the abnormality of data. CONSTITUTION:When a parity checker 16 detects a parity error in a data writing state, the gate of a writing gate part 34 is closed so that no data is written into a multi-port memory 3. At the same time, an error latch part 18A latches the parity error and a microprocessor MPU 1 opens a gate 25 with an address signal AD to sense the generating state of the parity error and to retry a writing operation. When the contents of the memory 3 are read out, the gate of a reading gate part 41 is opened and the data are fetched by an MPU 2. At the same time, the gate of the part 41 is not opened as long as the data produced by a parity generator 4 and including a parity bit has a parity error. As a result, the malfunctions are prevented and many retrying operations are carried out.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 3) Means for solving the problems to be solved by the invention (Figure 1) Working examples (Figure 2) ) Effects of the invention [Summary] Regarding the abnormality detection method of multiple ball memory, when a data abnormality occurs in one system, the data is not transmitted to other systems to prevent malfunction, and the system can be tried several times. In a multi-port memory abnormality detection method in which data is transferred asynchronously by a system including multiple MPLJs, each system includes an MPU, a parity generator, and a parity checker. , a write control section consisting of an error latch section for latching a parity error, and a write gate section, and a read control section consisting of a parity checker, an error latch section for latching a parity error, and a read gate section. When writing, create a parity focus, perform a parity check, and check the parity error.
If so, check the error and close the gate to suppress data writing. When reading data, perform a parity check in the read control section. If there is a parity error, latch the error and close the gate to prevent data from being written to the microprocessor sensor. The configuration is configured to prevent data from being imported.

[Industrial application field]

The present invention relates to an abnormality detection method for multi-port memory, and more particularly, the present invention relates to an abnormality detection method for multi-port memory.
Therefore, in a multi-port memory where data is exchanged asynchronously between MPUs in a circuit that transfers data, if a data error occurs in one system, the data is not transmitted to other systems. This invention relates to an abnormality detection method for multi-port memory that prevents malfunctions and allows multiple attempts.

[Prior Art] FIG. 3 is a block diagram of a conventional example of a system in which a plurality of MPUs asynchronously exchange data with each other via a multi-port memory.

In the figure, 12 is an MPU (microprocessor);
3 is a multi-port memory, 4 and 5 are parity generators, 6 and 7 are parity checkers, and 8 and 9 are Frisobflop circuits for latching error information.

Further, 10 to 15 are tristate buffers (TR I-STATE BUFFER), respectively.
Opening and closing of the gate is controlled by address signal AD.

Now, when an attempt is made to write data from the MPU 1 to the multi-port memory 3, the gate of the tri-state sofa 10 is opened by the address signal AD, and the multi-port memory 3 is accessed.

This causes data from the MPUI to be written. Also, at the same time as the data writing, the parity generator
A variable value corresponding to the data at that time is written in the data controller 4, the gate of the tristate printer 11 is opened, and the data is written into the multiport memory 3 together with the data.

Next, when the MPU 2 attempts to read the data written to the multi-port memory 3 as described above, the multi-port memory 3 is accessed, the gate of the tri-state buffer 15 is opened, and the data is taken into the MPU 2. .

At the same time, the data including the parity bits generated by the parity generator 4 is checked and checked by the parity chain force 7.

As a result, when a parity error occurs, the error is latched in the flimp-flop circuit 9, and a HALT signal, which is a stop signal, is sent to the MPU 2, and the M P LJ
2 is stopped by hardware.

The above operation is the same when data is sent from MPU2 to MPU1.

The purpose is to make it possible to request a retry.

[Problem to be solved by the invention]

The above-mentioned conventional devices had the following drawbacks.

(1) In a circuit where multiple MPUs transfer data asynchronously via multi-port memory, even if an error occurs when data is written to the multi-port memory from one side, the abnormal data will not be written directly to the memory. It gets lost.

Therefore, if a parity error does not occur when data is read from another system, the MPU of the other system recognizes the data as normal data, executes erroneous processing, and malfunctions.

(2) If a parity error occurred even once, the MPU would stop, making it impossible to retry.

The present invention eliminates these conventional drawbacks, prevents malfunctions by not transmitting data to other systems when a data abnormality occurs in one system, and prevents malfunctions by preventing data from being transmitted to other systems. Means] In order to achieve the above object, the present invention is as follows.

FIG. 1 is a diagram showing the principle of an abnormality detection method for a multi-port memory according to the present invention.

In a circuit that transfers data between a plurality of microprocessors (MPUs) 1 and 2, two systems each having the same configuration are provided for a multi-port memory 3 that asynchronously transfers data between the MPUs.

Each system includes an MPU, a data write control section, a data read control section, and the like.

In the system 1, the data write control section 36 includes a parity generator 4, a parity checker 16, a write gate section 34, and an error latch section 18A, and the data read control section 38 includes a parity checker 6, an error latch section 8A, and a readout section 18A. It is composed of a gate section 40.

In system 2, the data write control section 37 is composed of a parity generator 5, a parity checker 17, an error latch section 19A, and a write gate section 35, and the data read control section 39 is composed of a parity checker 7, an error latch section 9A, and a write gate section 35. , a read gate section 4l.

Gates 24 to 31 are controlled by the address signal AD.

When writing data from the MPUI to the multi-port memory 3, the gate of the write gate section 34 is opened, the multi-port memory 3 is accessed, and data is written.

At the same time, a parity bit corresponding to the data at that time is generated by the parity generator 4 and written together with the data through the write gate section 34.

When writing this data, the parity checker 16 performs a parity check, and if there is a parity error, the gate of the write gate unit 34 is closed to prevent data from being written to the multi-port memory 3.

At this time, the parity error is latched in the error latch section 18A, and the MPUI outputs the gate 25 to the address signal A.
Open by D, sense the occurrence situation of parity era,
Execute a writing paste trial.

When reading the contents written in the multi-port memory 3, the gate of the read gate section 41 is opened and the data is taken into the MPU 2.

At the same time, the data including the parity bit generated by the parity generator 4 is checked for parity by the parity checker 7, and if there is a parity error, the gate of the read gate section 41 is prevented from opening.

Then, the MPU 2 receives data from the pull-up resistor of the bus. The MPU 2 reads this data, opens the gate 30, and senses the occurrence of a parity error in the error latch section 9A.

If there is a parity error, data reading is retried.

At this time, if a parity error occurs in system 1 and a parity error occurs when system 2 reads the same address, MPU 2 can detect this by opening gate 27 and sensing error latch section 18A. Sense and wait until normal data is written.

In the opposite case to the above, from MPU 2 to multiplex memory 3
When writing data to and reading the data using the MPUI, the system 2 uses the write control section 37 and the system 1 uses the read control section 38 in the same manner as above.

[Effect]

As mentioned above, in a multi-port memory in which data is transferred asynchronously between multiple microprocessors (MPUs) in a circuit that transfers data, when a data error occurs in one system, the other system I try not to pass the data to.

Therefore, it is possible to prevent malfunctions when writing or reading data, and it is also possible to make multiple attempts.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
The figure is a block diagram of an abnormality detection method for a multi-port memory, which is an embodiment of the present invention.

In the figure, ■, 2 is MPU, 3 is multi-port memory,
4, 5 are parity generators, 6, 7, 16, 17 are parity generators, 8, 9, 18, 19 are flip-flop 1 circuits (hereinafter simply referred to as FF), 10-15, 24-
31 is a tri-state buffer, 20-23 and 32-
33 is an AND circuit, and AD is an address signal.

When an attempt is made to write data to the multi-port memory 3 from the MPUI, the gate of the tri-state buffer 10 is opened, the multi-port memory 3 is accessed, and data is written.

At the same time, the parity generator 4 generates a parity bit corresponding to the data at that time, the gate of the tri-state buffer 11 is opened, and the parity bit is written into the multi-port memory 3 together with the data.

Here, the difference from the conventional example shown in FIG. 3 is that the parity checker 16 also checks the validity of the data including the parity bit, and if there is a parity error,
The outputs of AND circuits 20 and 22 are used to prevent the gates of tristate bathofas 10 and II from opening.

Then, data “FF” (1
A hexadecimal number) and a parity bit of “1°” are written.

At the time of the above error, a parity error is further latched in FF1B, and the MPUI
The gate is opened to sense the occurrence of a parity error, and a write attempt is performed.

l2 Next, the data written in the multi-port memory 3 is sent to the MPU
2 attempts to read, the multi-port memory 3 is accessed, the gate of the tri-state buffer 15 is opened,
Data is taken into MPU2.

At the same time, the data including the parity bit generated by the parity generator 4 is checked by the parity checker 7, and if there is a parity error, an AND circuit 33 is operated to prevent the gate of the tri-state buffer 15 from being opened. suppress.

Then, the MPU 2 takes in data "FF" (hexadecimal) by the pull-up resistor of the bus.

When the MPU 2 reads out the data "FF", it may be an error, so it opens the gate of the tri-state buffer 30 and removes the parity error of the frino-pflop circuit 9.
Seven sources of the occurrence situation.

If there is a parity error, try again to read the data.

At this time, if a parity error occurs in the circuit on the MPUI side and the same address is read on the MPU2 side and a parity error occurs, the MPU2 opens the gate of the tri-state buffer 27 and flips the flip-flop. This can be determined by sensing the circuit 18, so sense this and hold the M until normal data is written.
P U 2 will have to wait.

M P tJ 1 resets FFl8 when data can be written normally. This operation is the same when data is sent from the MPU2 to the MPUI.

In the above embodiment, an example in which two MPUs are used has been described, but the present invention is not limited to this, but can also be applied to, for example, a multi-port memory using three or more MPUs. be.

This prevents malfunctions.

(2) Even if a parity error occurs due to some factor even though there is no failure, the operation of the MPU can be prevented from stopping by performing a retry and confirming that it has returned to normal.

(3) Since the occurrence of parity errors can be sensed from either system, it is easy to find the failure location when an error occurs.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of an abnormality detection method for a multi-port memory according to the present invention, Fig. 2 is a block diagram of an abnormality detection method for a multi-port memory according to an embodiment of the present invention, and Fig. 3 is a block diagram of a conventional example. It is a diagram. [Effects of the Invention] As explained above, the present invention has the following effects. (1) Always receive normal data on one side 1, 2
- Microprocessor (MPU) 3 - Multi-port memory 36, 37 - Write control section 38, 39 - Read control section 4, 5 - Parity generator 6, 7, I6, 17 - Parity checker 34, 35 - Write gate section 8A , 9A, 18A, 1 9 A- error latch section 4
0, 41-read gate section

Claims (1)

[Claims] A system including a plurality of microprocessors (MPUs),
In an abnormality detection method for a multi-port memory (3) that asynchronously transfers data between MPUs, each system includes a microprocessor (1, 2), a parity generator (4, 5), and a parity checker. (
16, 17), error latch parts (18A, 19A) that latch parity errors, write gate parts (34, 3
5); a read controller consisting of a parity checker (6, 7); an error latch section (8A, 9A) that latches a parity error; and a read gate section (40, 41). Control unit (38, 39)
When writing data to the multi-port memory (3), the write control unit (36, 37) creates a parity bit for the write data, performs a parity check, and returns an error if there is a parity error. A parity error is latched in the latch section (18A, 19A), and the gate of the write gate section is closed to suppress data writing, and when reading data, a parity check is performed in the read control section (38, 39). If it is a parity error, the error latch section (
8A, 9A), and closes the gates of read gate sections (40, 41) to prevent data from being taken into the microprocessor.