JPH0223669A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0223669A JPH0223669A JP17412788A JP17412788A JPH0223669A JP H0223669 A JPH0223669 A JP H0223669A JP 17412788 A JP17412788 A JP 17412788A JP 17412788 A JP17412788 A JP 17412788A JP H0223669 A JPH0223669 A JP H0223669A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- concentration diffusion
- trench
- low concentration
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002784 hot electron Substances 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はトレンチ・ゲー）ＭＯＳ ＦｇＴの少くとも
ドレイン拡散層構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to at least a drain diffusion layer structure of a trench MOS FgT.
［従来の技術］
従来、トレンチ・ゲートＭＯ３
ＦＥＴの拡散
層構造は第２図に要部の断面図で示す如く、Ｓｉ基板１
１０表面に形成されたトレンチ部にはゲート酸化膜１２
及びゲート電極１６が形成されてゲート領域を形成して
成り、該ゲート領域に隣接した８１基板１１０表面から
ソース及びドレインの拡散層１４．１４’が形成されて
成るのが通例であった。[Prior Art] Conventionally, the diffusion layer structure of a trench gate MO3 FET is based on a Si substrate 1, as shown in a cross-sectional view of the main part in FIG.
A gate oxide film 12 is formed in the trench portion formed on the surface of 10.
and a gate electrode 16 are formed to form a gate region, and source and drain diffusion layers 14 and 14' are typically formed from the surface of the 81 substrate 110 adjacent to the gate region.
［発明が解決しようとする課題］
しかし、上記従来技術によると、トレンチ・ゲ−）ＭＯ
Ｓ ＦＥＴのドレイン拡散層からのホット・エレクト
ロンが多量に発生し、ゲート酸化膜に捕獲されて、しき
い値変動を起すと云う課題があった。[Problems to be Solved by the Invention] However, according to the above-mentioned prior art, trench gate) MO
There is a problem in that a large amount of hot electrons are generated from the drain diffusion layer of the SFET and are captured in the gate oxide film, causing a threshold voltage fluctuation.
本発明は、かかる従来技術の課題をなくシ、トレンチ・
ゲー）ＭＯＳ ＦＥＴに於て、ホット・エレクトロン
の発生の少ないドレイン拡散層構造を提供する事を目的
とする。The present invention eliminates the problems of the prior art and
The purpose of the present invention is to provide a drain diffusion layer structure in which fewer hot electrons are generated in a MOS FET.
［課題を解決するだめの手段］
上記課題を解決するために、本発明は半導体装置に関し
、トレンチ・ゲートＭＯ３ＰＥＴのトレンチ・ゲート部
に隣接する少くともドレイン拡散層には低濃度拡散層を
設け、該低濃度拡散層に隣接して高濃度拡散層を形成す
る手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a semiconductor device, and includes providing a low concentration diffusion layer at least in a drain diffusion layer adjacent to a trench gate portion of a trench gate MO3PET; Measures are taken to form a high concentration diffusion layer adjacent to the low concentration diffusion layer.
［実施例］ 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示すトレンチ・ゲートＭＯ
８ＰＥＴの要部の断面図である。すなわち、Ｓｉ基板１
の表面には、トレンチが形成され、該トレンチ内にゲー
ト酸化膜２、及びゲート電極３が形成されてトレンチ・
ゲート領域となし、該トレンチ・ゲート領域にはＳｉ基
板１０表面に於て隣接して低濃度拡散層５，５′をイオ
ン打込み等により形成し、該低濃度拡散層５，５′に隣
接して、高濃度のソース及びドレインとなる拡散層４，
４′を低濃度拡散層５，５′はマスクしてイオン打込み
等にて形成して成る。尚低濃度拡散層５，５′は、いず
れか一方をドレイン領域とすれば、ドレイン領域のみに
形成し、ソース領域には必ずしも必要なものではない。FIG. 1 shows a trench gate MO showing an embodiment of the present invention.
FIG. 8 is a cross-sectional view of the main parts of 8PET. That is, the Si substrate 1
A trench is formed on the surface of the trench, and a gate oxide film 2 and a gate electrode 3 are formed in the trench.
A gate region is formed, and low concentration diffusion layers 5 and 5' are formed adjacent to the trench gate region on the surface of the Si substrate 10 by ion implantation, and adjacent to the low concentration diffusion layers 5 and 5'. , a diffusion layer 4 which becomes a highly concentrated source and drain;
The low concentration diffusion layers 5 and 5' are formed by masking 4' and ion implantation. Note that if one of the low concentration diffusion layers 5, 5' is used as a drain region, it is formed only in the drain region, and is not necessarily required in the source region.
［発明の効果］
本発明によりトレンチ・ゲートＭＯＳＦＥＴのホット・
エレクトロン発生によるしきい値電圧の変動を押えるこ
とができる効果がある。[Effect of the invention] The present invention improves the hot-temperature of trench gate MOSFET.
This has the effect of suppressing fluctuations in threshold voltage due to electron generation.
第１図は本発明の一実施例を示すトレンチ・ゲ−）ＭＯ
Ｓ ＦＥＴの要部の断面図であり、第２図は従来技術
を示すトレンチ・グー）ＭＯＳ １１１Ｔの要部の断
面図である。
１．１１・・・・・・Ｓ１基板
２．１２・・・・・・ゲート酸化膜
３．１３・・・・・・ゲート電極
４＠４’ ｔ １４，１４’・・・・・・拡散層５．
５１・・・・・・低濃度拡散層Figure 1 shows an embodiment of the present invention.
FIG. 2 is a sectional view of a main part of an S FET, and FIG. 2 is a sectional view of a main part of a trench MOS 111T showing the prior art. 1.11...S1 substrate 2.12...Gate oxide film 3.13...Gate electrode 4@4' t 14,14'...Diffusion Layer 5.
51...Low concentration diffusion layer
Claims (1)
成されるに際し、該トレンチ・ゲートの前記半導体表面
に隣接して少くともドレイン拡散層を低濃度拡散層を設
け、該低濃度拡散層に隣接して高濃度拡散層を設けて成
る事を特徴とする半導体装置。When a trench gate MOSFET is formed on the surface of a semiconductor substrate, at least a drain diffusion layer and a low concentration diffusion layer are provided adjacent to the semiconductor surface of the trench gate, and a high concentration diffusion layer is provided adjacent to the low concentration diffusion layer. A semiconductor device comprising a concentration diffusion layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17412788A JPH0223669A (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
| KR1019890007221A KR0173111B1 (en) | 1988-06-02 | 1989-05-30 | Trench gate metal oxide semiconductor field effect transistor |
| US07/360,486 US5142640A (en) | 1988-06-02 | 1989-06-02 | Trench gate metal oxide semiconductor field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17412788A JPH0223669A (en) | 1988-07-12 | 1988-07-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223669A true JPH0223669A (en) | 1990-01-25 |
Family
ID=15973129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17412788A Pending JPH0223669A (en) | 1988-06-02 | 1988-07-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223669A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453635A (en) * | 1994-08-23 | 1995-09-26 | United Microelectronics Corp. | Lightly doped drain transistor device having the polysilicon sidewall spacers |
-
1988
- 1988-07-12 JP JP17412788A patent/JPH0223669A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453635A (en) * | 1994-08-23 | 1995-09-26 | United Microelectronics Corp. | Lightly doped drain transistor device having the polysilicon sidewall spacers |
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