JPH02234461A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a low threshold at a low temperature by a method wherein an n-type channel MOS is formed on an n-type well and a p-type channel MOS is formed on a p-type well to constitute a CMOS device and the n-type well and the p-type well are electrically isolated from each other. CONSTITUTION:A trench region 12 for isolating an n-type well and a p-type well from each other is made of polycrystalline silicon and an insulating film 13 covering the trench region 12 is provided. An n-type well 4 is formed by the ion implantation or thermal diffusion of phosphorus and a p-type well 3 is formed by the ion implantation or thermal diffusion of boron. Further, an n-type channel MOS-FET is formed on the surface region of the n-type well 4 by forming n-type high impurity concentration regions as a drain 7, a source 8, a gate oxide film 9 and a gate electrode layer 10 and a p-type channel MOS- FET is formed on the surface region of the p-type well 3 by forming p-type high impurity concentration regions as a drain 6, a source 5, a gate oxide film 9 and a gate electrode layer 11. With this constitution, the low threshold of a fine device which is so designed as to have high well concentrations can be realized at a low temperature not higher than 100 K can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS device, and particularly to a low temperature CMOS device structure suitable for low voltage operation. [Prior Art] In a conventional CMOS device, a channel MOS is formed in a p-well and a p-channel MOS is formed in an n-well, as shown in the cross-sectional view in FIG. At this time, both channels M
OS (7) threshold value (Vt) is V. N. Carr and J.
P. Mize's rMOS/LSID
As discussed on page 38 of the book entitled esign and Application J, it is expressed by the following equation. ...(1) ...(2) Here, ΦHa is the work function difference between the p-well or n-well and the gate electrode, Cox is the oxide film capacitance (F/a#), and Qs
s is the interface fixed charge (Goun/a#), Qs is the depletion layer charge (Cou Q/ffl), and φF is the Fermi potential, which is the difference between the intrinsic energy level and the Fermi energy. In the ideal case where there is no work function difference and no fixed charges at the interface, the equation is as follows. COχ Cox Here, the depletion layer charge QB is (4εs eastεoqNaφF)2
It is approximated as Further, εs1 is the relative permittivity of Si, to is the vacuum permittivity, q is the electron charge, and Na is the substrate impurity concentration. By the way, φF increases at low temperatures, so Equation (3), (
The Vt value as the theoretical limit given by 4) is also 0.3-0.
．． It increases by about 4V. (Problem to be Solved by the Invention) The increase in VT due to the increase in φF at low temperatures, which was observed in the conventional device, was an important problem when operating CMOS devices at low voltages at low temperatures. In order to prevent channel effects, the well impurity concentration (No.
), but this increase in Na also increases φF, which intensifies the increase in Vt at low temperatures.

The purpose of the present invention is to provide a CMOS device structure suitable for low-voltage operation that solves the above-mentioned problem of VT increase at low temperatures. This is achieved by forming a p-channel MOS in the p-well to form a CMOS device, and by electrically insulating and separating both the n+p wells.

[Effect]

The CMOS device of the present invention has an n-channel MOSFET in an n-well and a p-channel MOSFET as shown in FIG.
In an ideal case where the OSFET is fabricated in a p-well and there is no work function difference and no interface fixed charge density, the threshold at a low temperature of 100 K or less is given by the following equation. Here, the depletion M charge Qa is approximated as follows. Here, Eg is a bandgap value.

At low temperatures below 100 K, the Fermi potential φF value approaches Et/2, so the theoretical limit value of v given by equations (5) and (6) also decreases and approaches zero. In this way, the problem of increased V at low humidity in conventional devices can be solved. In addition, the structure of the present invention can maintain insulation between both wells at temperatures below 100K, where carrier freeze-out occurs, but in order to prevent short circuits between the two wells during room temperature test operation,
A SiOz layer was provided in the trench-type region for element isolation and below the well. Furthermore, when the gate voltage is zero, no current flows in both MOSs due to carrier freeze-out effects in both neP wells, and enhancement operation is realized. Furthermore, in conventional CMOS devices, it is necessary to increase the well concentration (N}I) in order to prevent short channels in fine devices, but this increase in NB also causes a problem in that low-temperature VT also increases. On the other hand, in the present invention, even if Na increases, the fuel potential φF increases, and in n-type Si, the fuel level approaches the conduction band edge, and in p-type Si, the fuel level approaches the valence electron 42 edge, resulting in equation (5) , (6) has the advantage that the threshold value (Vt) hardly changes.

In other words, the present invention is extremely effective as a low-temperature VT reduction method for fine devices designed with high well concentration. {Example} A first example of the present invention will be described below with reference to FIG.
In FIG. 1, 1 is an n-type Si substrate.

2 is a SiOi layer formed in the substrate, and oxygen ions 1
After implanting 80+ at a high energy of 100 KeV to 500 KeV in an amount of 5
It is formed by annealing at 50° C. for 2 hours. Under this condition, S
The thickness is 0 in the range from 1 μm to 5 μm below the i surface.
．． An 8102 layer 2 with a thickness of 2 μm to 0.4 μm can be formed. Reference numeral 12 denotes a groove-type region for separating both wells and is made of polysilicon. Reference numeral 13 denotes an insulating film that covers the groove-shaped region 12. 3 is a p-type well formed by boron ion implantation or thermal diffusion method, and 4 is an n-type well formed by phosphorus ion implantation or thermal diffusion method. The n-channel MOSFET uses n-type high concentration impurity regions 7 and 8 as the drain and source, respectively, in the surface region of the n-well 4. 9.10 is formed as a gate oxide film and a gate electrode layer. The p-channel MOSFET is formed in the surface region of the p-well 3 with p-type high concentration impurity regions of 6.5 mm as the drain and source, respectively, and 9 and 11 as the gate oxide film and gate electrode layer. 10 and 1
The CMOS inverter circuit of the present invention can be constructed by connecting 1 as a human power terminal, connecting 6 and 7 as an output terminal, 5 as a power supply terminal, and 8 as a ground terminal. 14 is a groove type region for element isolation, and 15 is an insulating film covering this. According to this embodiment, an nMOS transistor is placed in the n-type well surface region. Since the pMOS transistors are formed in the p-well surface region, each vT can be made smaller than that of the conventional type. In this example, n+ polysilicon is used for the gate of nMOS, and p+ polysilicon is used for the gate of pMOS, and the results of the IV characteristics at this time are shown in FIG. 3 in comparison with the conventional characteristics. The conventional type shown here also uses n+ polysilicon for the nMOs gate and p+ polysilicon for the pMOS gate. In addition, the present invention and the conventional type have the same specifications such as well impurity concentration, gate oxide film thickness, and drain/source diffusion layer depth, except that the conductivity type of the well in which each MOS transistor is formed is opposite. As is clear from the experimental results shown in FIG. 3, the absolute value of VT in the conventional type was about 0.5V, whereas in the present invention, the same value can be reduced to about 0.2V. As a result, low voltage operation with Vcc of about 0.5V was realized.

Additionally, an insulating isolation region is provided between both wells, which prevents short circuits between both wells during room temperature tests. Furthermore, in the first embodiment described above, the case was described in which the SiOz layer provided in the substrate was formed by high-energy implantation of oxygen ions, but in the present invention, the Si substrate is thermally oxidized and the SOI layer is grown on it by solid phase epitaxial growth. Of course, this can also be achieved by recrystallizing a poly-Si layer deposited on a thermally oxidized layer by laser beam irradiation. A second embodiment of the invention is shown in FIG. This embodiment differs from the first embodiment in that the Si2 layer 2 provided in the substrate is formed only below the p-well 3. Even in this structure, p
Well 3 and n-well 4 could be electrically isolated. The effects of this embodiment are the same as those of the first embodiment.

A third embodiment of the invention is shown in FIG. This embodiment differs from the first and second embodiments in that no SiOz layer is formed below the wells, except for the groove-type insulating regions between the n and p wells. Even with this structure, insulation between both nyP wells can be maintained at temperatures below 100K, where carrier freeze-out occurs in both nyP wells. Both wells will be short-circuited during room temperature testing, but the operating temperature should be limited to 100K or less. According to this embodiment, the structure of the present invention can be easily realized using the conventional device fabrication technology, and both MOSs can have low v at low temperatures.
We were able to make it into a T.

Although the above embodiment describes the case of a CMOS device using an n-substrate, the present invention can also be realized when using a p-substrate to create an n-MOS in the n-well and a PMOS in the p-well. Of course. [Effect of the invention] According to the present invention. nMOS to n well, pMOS to p
By forming it in the well, it is possible to achieve a low VT of 100 or less at low temperatures, IIVT≦0.2■, and Vcc≦
Low voltage operation of 0.5v is achieved.

When no voltage is applied to the gate, no current flows due to the freeze-out effect of both n+P wells, ensuring enhancement operation. Also, conventional micro CMOS
Devices are designed with a high well concentration to prevent short channel effects, but at this time the VT increase at low temperatures becomes large, which is a problem. In the present invention, even if the well concentration is high, low V-density can be achieved at low temperatures. Furthermore, electrical isolation between both the n+P wells can be achieved by the carrier freeze-out effect at a low temperature of 100 K or less without intervening an insulating layer between the two wells. In the present invention, an insulating layer is interposed between the wells in order to prevent short circuit between both wells during a room temperature test.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the first embodiment of the present invention, Fig. 2 is a diagram showing a conventional CMOS device structure, Fig. 3 is a diagram showing the effects (IV characteristics) of the present invention, and Fig. 4 is a diagram showing the present invention. FIG. 5 is a diagram showing a second embodiment of the invention, and FIG. 5 is a diagram showing a third embodiment of the invention. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...SiOz layer, 3...p well, 4...n well, 5...pMOs source, 6
...pMOS drain, 7...n MOS drain, 8...n MOS source, 9... gate oxide film, 10...n MOS gate electrode layer, 11
... PMOS gate electrode layer, 12 ... polysilicon, 13 ... insulating film, 14 ... polysilicon, 352 Yamuko JA / Broom 5 Figure No.

Claims (1)

[Claims] 1. In the surface region of the first conductivity type well of the semiconductor substrate, a first
It has a first MOS transistor whose source and drain are formed by conductivity type high concentration impurity regions, and a second MOS transistor.
A second M in which a source and a drain are formed by high concentration impurity regions of the second conductivity type in the surface region of the conductivity type well.
A semiconductor device comprising an OS transistor and operating in a temperature range of 100K or less. 2. An insulating isolation region is provided between the first conductivity type well and the second conductivity type well, and an insulating film is provided below at least one of the wells to electrically insulate and isolate the wells. A semiconductor device according to claim 1.