JPH02232956A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02232956A
JPH02232956A JP5430789A JP5430789A JPH02232956A JP H02232956 A JPH02232956 A JP H02232956A JP 5430789 A JP5430789 A JP 5430789A JP 5430789 A JP5430789 A JP 5430789A JP H02232956 A JPH02232956 A JP H02232956A
Authority
JP
Japan
Prior art keywords
fin
case
intermediary
close contact
insulating board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5430789A
Other languages
Japanese (ja)
Inventor
Yoshihiro Yamauchi
山内 義博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5430789A priority Critical patent/JPH02232956A/en
Publication of JPH02232956A publication Critical patent/JPH02232956A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make an upper element large enough in heat dissipating property to enable a current to flow through both the upper and the lower element at the same time by a method wherein flat semiconductor elements stacked in two or more stages are housed inside a case-shaped heat dissipating fin, and a bus bar in close contact with the upper element is brought into contact with the inner wall inside the fin through the intermediary of an insulating board. CONSTITUTION:A heat dissipating fin 4 is composed of case 8 provided with a side wall 4a which protrudes upward so as to surround semiconductor elements 1a and 1b inside it. The flat type semiconductor elements 1a and 1b are stacked in two stages on the inner base of the case 8 through the intermediary of insulating boards 2a and 2b and bus bars 3a-3c. The ends of the bus bars 3a and 3b brought into close contact with the electrodes of the upper element 1a are brought into close contact with the inner face of the side wall 4a of the fin 4 through the intermediary of an insulating board 2c. A spring 7 is fastened tight with bolts 5 and nuts 6 so as to press down the upside of the element 1a through the intermediary of the insulating board 2a, and the case 8 makes an electrically conductive part insulated from the outside excluding the ends of the bus bars. By this setup, heat released from the element 1a is rapidly conducted to the fin 4a through the bars 3a and 3b and the insulating board 2c.

Description

【発明の詳細な説明】 (産業上の利用分野〕 この発明は、平形午導体素子を外部絶縁するとともに、
放熱も十分満足する半導体装置の組立て構造に関するも
のである。
[Detailed Description of the Invention] (Industrial Application Field) This invention provides external insulation of a flat meridian conductor element, and
The present invention relates to an assembly structure of a semiconductor device that satisfies heat dissipation.

(従来の技術〕 平形半導体素子を使用した半導体装置において、外部絶
縁すると・ともに、平杉半導体素子からの発生熱を効果
的に放熱して冷却を図るためには、普通・平杉半導体素
子の電極に近い個所で絶縁機能を付与し、かつ放熱フィ
ン等を設けるタイプが多いO 第2図は従来のこの柚の半導体装置を示す一例であり、
図において、lB..lbは絶縁板2&2b曲に2段檀
みした半導体素子、孤3h,3cはそれらの間に介装し
た電極取り出し用のブスバ・4は放熱用の7イン、5は
このフィンの上に立設されたボルト、6はこのボルトに
螺合されたナット、7はボルト間に架設されたばねであ
り、圧接機構をなしている。
(Prior art) In a semiconductor device using a flat semiconductor element, in order to provide external insulation and to effectively dissipate heat generated from the Hirasugi semiconductor element for cooling, it is necessary to use the conventional Hirasugi semiconductor element. There are many types that provide an insulating function near the electrodes and have heat dissipation fins, etc. Figure 2 is an example of a conventional semiconductor device of this type.
In the figure, lB. .. lb is a semiconductor element mounted in two stages on the curve of insulating plates 2 and 2b, sockets 3h and 3c are busbars for taking out the electrodes inserted between them, 4 is a 7 inch for heat radiation, and 5 is installed on top of this fin. 6 is a nut screwed onto the bolt, and 7 is a spring installed between the bolts, forming a pressure welding mechanism.

8はケースであり、外部からの絶縁を保っている。8 is a case, which maintains insulation from the outside.

なお図では、内部をわかり易くするためにケースの一部
を取り除いて示している。
Note that in the figure, a part of the case is removed to make the interior easier to understand.

次に動作について説明する0平形半導体素子1a1tb
は晋通圧接されて使用されるか、こ\では剛体である放
熱7イン4とばね7の間に挾み、ボルト6とナット6に
より締め付けることにょり圧接機構が構成されている。
Next, the operation of the 0-plane semiconductor element 1a1tb will be explained.
In this case, it is sandwiched between a rigid heat dissipating 7-in-4 and a spring 7 and tightened with bolts 6 and nuts 6 to form a pressure welding mechanism.

又、平形午導体素子に奄気を流すために″a極取り出し
用のプスバか該素子の#′IIL極に密接して設けられ
るのが普通で′あり、これらの導電邪分を外部と絶縁す
るために上下に絶縁板2&s2bが配置されている。
In addition, in order to flow air into the flat conductor element, a pass bar for taking out the "a" pole is usually provided in close proximity to the #'IIL pole of the element, and these conductive elements are insulated from the outside. Insulating plates 2 & s2b are arranged above and below for this purpose.

およそ平形半導体素子は通電時大量の熱を発生するが、
この熱を効率よく放熱しないと、温度上昇のため該素子
は破壊されることになる。このため絶縁板2&2bは熱
伝導性のよい物質(例えばセラミック)で作られており
、放熱7イン4へ途やかに熱を伝え、この放熱7イン4
から外気中へ放熱されるようになっている。またケース
8は電極接続用のプスバ以外の導IE部分を外部と遮断
して、外部絶縁形半導体装置としている。
Approximately flat semiconductor elements generate a large amount of heat when energized,
If this heat is not dissipated efficiently, the element will be destroyed due to the temperature rise. For this reason, the insulating plates 2 & 2b are made of a material with good thermal conductivity (ceramic, for example), and quickly transfer heat to the heat dissipating 7-in-4.
The heat is radiated from the inside to the outside air. Further, the case 8 isolates the conductive IE portions other than the pass bar for electrode connection from the outside, thereby forming an externally insulated semiconductor device.

〔発明が解決しようとする課朧〕[The problem that the invention attempts to solve]

従来の平形半導体素子便用の外部絶縁形午導体装置は以
上のように構成されていたが、2段に槓層した素子のう
ち上部の素子11においては、直接放熱フィンに接して
いないことから、放熱が十分行なえず、満足な通電を行
なえないという問題点があった〇 この発明は上記のような問題点を解消するためになされ
たもので、積層された上側の平形半導体素子からも十分
な熱の放散を可能ならしめ、該素子に十分な通電が可能
となるような半導体装置を得ることを目的としている。
The conventional externally insulated conductor device for flat semiconductor devices was constructed as described above, but since the upper element 11 of the two-layered elements is not in direct contact with the heat dissipation fins. However, there was a problem in that heat dissipation was not sufficient and sufficient current could not be passed. This invention was made to solve the above problems, and the upper layered flat semiconductor element also It is an object of the present invention to provide a semiconductor device that enables sufficient heat dissipation and allows sufficient current to flow through the element.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、ケース状に構晟した放熱
フィンの中に、複数段に積層した平形午導体素子を収納
する七ともに、その上側の素子からの電極収り出し用の
プスバの形状を、組み上げた時に絶縁板を介して上記放
熱フィンの内部側壁に密着するようにしたものである。
The semiconductor device according to the present invention has a case-shaped heat dissipation fin that houses planar conductor elements laminated in multiple stages, and a shape of a pass bar for taking out electrodes from the upper element. When assembled, the fins are brought into close contact with the inner side walls of the radiation fins via an insulating plate.

〔作用〕[Effect]

この発明におけるブスバと放熱フィンの構成により、上
側の平形半導体素子からの発生熱は、熱伝導のよいプス
バから絶縁板を通って放熱フィンに伝わり、十分空気中
へ放熱されるようになる。
Due to the structure of the bus bar and heat dissipation fin in this invention, the heat generated from the upper flat semiconductor element is transmitted from the bus bar with good thermal conductivity to the heat dissipation fin through the insulating plate, and is sufficiently radiated into the air.

〔実施例〕〔Example〕

以下、この発明の一実施例を第1図について説明する。 An embodiment of the present invention will be described below with reference to FIG.

4は内部の牛導体素子1m,lbを取り囲むように上部
へ突出側壁4aを設けたケース状の放熱7インであり、
その内部の底面に絶縁板2a.2bとブスバ3亀3飄3
oを介して平形半導体素子1a,比が積層されて2段檀
みとなっている。そして上側の素子1&の両電極に密着
しているプスバ3a,3bの端部は放熱フイン4の側壁
内面に別の絶縁′板2oを介して密接するように形成さ
れている。なお、ばね7は絶縁物2aを介して素子の上
部を押え付け゜るようにボルト6とナット6で締め付け
られ、圧接機構を構成するようになっている。また、ケ
ース8はプスバの一端を除いて導電邪分を外部より遮断
するようにしている。
4 is a case-shaped heat dissipating 7-inch with a side wall 4a protruding from the top so as to surround the internal conductor element 1m, lb;
Insulating plate 2a on the inside bottom surface. 2b and Busuba 3 Turtle 3 Sword 3
The flat semiconductor elements 1a and 1a are stacked with each other in a two-tier structure. The end portions of the push bars 3a, 3b that are in close contact with both electrodes of the upper element 1& are formed in close contact with the inner surface of the side wall of the heat radiation fin 4 via another insulating plate 2o. The spring 7 is tightened with a bolt 6 and a nut 6 so as to press down the upper part of the element through the insulator 2a, thereby forming a press-contact mechanism. Further, the case 8 is designed to block conductive elements from the outside except for one end of the push bar.

次に上記構成における作用について説明する。Next, the operation of the above configuration will be explained.

上部の平形半導体素子1aの電極面には、例えば銅など
の熱伝導性のよいプスバ3a,3bが密着しており、そ
して、このプスバのyI1部は絶縁板2oを介して放熱
フィン4部の内部側壁に接しているので、上部の素子1
aから発生する熱は、速やかに該プスバ菖、あを通って
絶縁板2cから放熱7イン4aへ伝わり、最後は外気中
へ放熱される。なお、下側の素子1bも同様の経路で放
熱が行なわれ、従って、2個の素子は同等レベルの放熱
がなされるようになり、全体として通電能力が大巾にア
ツプされることとなる〇 なお上記実施例では、放熱フイン4として、ヒダが複数
あって、それ自体で放熱の働きがあるものを示したが、
ただの板状のものとして、これを他の放熱フイ゜ンに取
付ける構造としてもよい。
Push bars 3a and 3b having good thermal conductivity, such as copper, are in close contact with the electrode surface of the upper flat semiconductor element 1a, and the yI1 portion of this push bar is connected to the heat dissipating fin 4 through an insulating plate 2o. Since it is in contact with the internal side wall, the upper element 1
The heat generated from a is quickly transmitted from the insulating plate 2c to the heat radiating 7-in-4a through the iris and a, and finally is radiated into the outside air. Note that the lower element 1b also radiates heat through a similar path, so that the two elements radiate heat at the same level, and the current carrying capacity as a whole is greatly increased. In the above embodiment, the heat dissipation fin 4 has a plurality of pleats and has a heat dissipation function by itself.
It may be a simple plate-like structure that is attached to another heat dissipation fin.

また上記実施例では、素子を2段に檀階したものを示し
たが、8段以上にI/li層した塚合にも適用し得るこ
とはいうまでもない。
Further, in the above embodiment, the elements are arranged in two stages, but it goes without saying that the present invention can also be applied to a structure in which the I/li layers are arranged in eight or more stages.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、ケース状の放熱フィン
の内部に複数段檀層された平形半導体素子を収納し、そ
の上側の素子に密着したプスバを放熱フィン内Sa壁に
絶縁板を介して接触するように構成したので、上側・素
子からも十分な放熱ができ、従って、下側の素子と同様
の通電が可能となり、全体として大巾に通電能力を向上
し得る効果がある。
As described above, according to the present invention, a plurality of layers of flat semiconductor elements are housed inside a case-like heat dissipation fin, and a pass bar that is in close contact with the upper element is attached to the Sa wall inside the heat dissipation fin via an insulating plate. Since the structure is configured so that the two elements are in contact with each other, sufficient heat can be dissipated from the upper side of the element, and therefore, it is possible to conduct electricity in the same way as the element on the lower side, which has the effect of greatly improving the current carrying capacity as a whole.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による午簿体装置を示す一
部切欠の正面図、第2囮は従来の午導体装置を示す図で
ある。 図中、1転比は午導体素子、2aqZbJoは絶縁板、
為、&3aはプスバ、4は冷却フィン、4aは冷却フィ
ンの側壁、5はボルト、6はナット、7はばね、8はケ
ースである。 なお図中同一符号は同一または相当部分を示す。
FIG. 1 is a partially cutaway front view showing a meridian device according to an embodiment of the present invention, and a second decoy is a diagram showing a conventional meridian device. In the figure, 1 rotation ratio is a conductor element, 2aqZbJo is an insulating plate,
Therefore, &3a is a push bar, 4 is a cooling fin, 4a is a side wall of the cooling fin, 5 is a bolt, 6 is a nut, 7 is a spring, and 8 is a case. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 平形半導体素子を放熱フィン上に絶縁板とブスバを介し
て複数段積層し、これらを上方から絶縁板を介して圧接
機構で締め付けるようにした半導体装置において、上記
放熱フィンをケース状に構成して、その内部に上記複数
段の半導体素子を収納し、その上側の素子に密着したブ
スバの端部を放熱フィン内部側壁に絶縁板を介して接触
するようにしてなる半導体装置。
In a semiconductor device in which a plurality of flat semiconductor elements are stacked on a heat dissipation fin via an insulating plate and a bus bar, and these are clamped from above by a pressure welding mechanism via an insulating plate, the heat dissipation fin is configured in a case shape. , a semiconductor device in which the plurality of stages of semiconductor elements are housed therein, and an end of a bus bar that is in close contact with the upper element is in contact with an inner side wall of a heat dissipation fin via an insulating plate.
JP5430789A 1989-03-07 1989-03-07 Semiconductor device Pending JPH02232956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5430789A JPH02232956A (en) 1989-03-07 1989-03-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5430789A JPH02232956A (en) 1989-03-07 1989-03-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02232956A true JPH02232956A (en) 1990-09-14

Family

ID=12966915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5430789A Pending JPH02232956A (en) 1989-03-07 1989-03-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02232956A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999040625A1 (en) * 1998-02-06 1999-08-12 Intel Corporation Thermal bus bar design for an electronic cartridge

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999040625A1 (en) * 1998-02-06 1999-08-12 Intel Corporation Thermal bus bar design for an electronic cartridge
US5990549A (en) * 1998-02-06 1999-11-23 Intel Corporation Thermal bus bar design for an electronic cartridge

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