JPH02232946A - Junction structure of solder bump with pad - Google Patents
Junction structure of solder bump with padInfo
- Publication number
- JPH02232946A JPH02232946A JP1053294A JP5329489A JPH02232946A JP H02232946 A JPH02232946 A JP H02232946A JP 1053294 A JP1053294 A JP 1053294A JP 5329489 A JP5329489 A JP 5329489A JP H02232946 A JPH02232946 A JP H02232946A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- chip
- film
- substrate
- solder bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 abstract description 18
- 239000000758 substrate Substances 0.000 abstract description 18
- 229920001721 polyimide Polymers 0.000 abstract description 8
- 239000004642 Polyimide Substances 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 4
- 230000004907 flux Effects 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000009713 electroplating Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 239000003960 organic solvent Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、フリフプチップ実装法により接合されたハン
ダバンプとパッドとの接合構造に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a bonding structure between a solder bump and a pad bonded by a flip-flop chip mounting method.
く従来の技術〉
ＩＣチップの基板への実装方法としては、ＩＣチップの
各電極にあらかじめハンダパンプを形成しておき、この
チップをフエイスダウンにより基板上に仮止めした後、
ハンダバンプのリフローを行うことによって、ＩＣチッ
プの電極と基板のパッドとを電気的に接続する、いわゆ
るフリップチフブ実装法がある。Conventional technology> As a method for mounting an IC chip on a board, solder pumps are formed in advance on each electrode of the IC chip, and after the chip is temporarily fixed on the board by face-down,
There is a so-called flip chip mounting method in which electrodes of an IC chip and pads of a substrate are electrically connected by reflowing solder bumps.
く発明が解決しようとする課題〉
従来、ＩＣチップの基板への仮止めには、フランクス等
の接着剤が用いられている。Problems to be Solved by the Invention> Conventionally, an adhesive such as Franks has been used to temporarily fix an IC chip to a substrate.
ここで、ＩＣチップが基板に仮止めされた時点では、ハ
ンダバンプとパッドとの接触は、球面と平面との接触と
なっており、ハンダバンプとパッド間にフラックスが存
在する。このため、ハンダバンプを加熱して融解しても
、ハンダバンプがパッドに充分に濡れず、接合不良が生
じる場合がある。Here, when the IC chip is temporarily fixed to the substrate, the contact between the solder bump and the pad is between a spherical surface and a flat surface, and flux exists between the solder bump and the pad. Therefore, even if the solder bumps are heated and melted, the solder bumps may not wet the pads sufficiently, resulting in poor bonding.
本発明の目的は、接続の信頬性が高いハンダバンプとパ
ッドとの接合構造を提供することにある。An object of the present invention is to provide a bonding structure between a solder bump and a pad that has high connection reliability.
く課題を解決するための手段〉
本発明の接合構造は、実施例に対応する第１図に示すよ
うに、基板のパフド１ａに植設された金属製支柱４がＩ
Ｃチップのハンダバンプ３内部に埋め込まれていること
によって特徴づけられる。Means for Solving the Problems> In the joining structure of the present invention, as shown in FIG.
It is characterized by being embedded inside the solder bump 3 of the C chip.
く作用〉
本発明の接合構造は、基板のパッド上に金属製支柱を形
成しておき、この支柱にＩＣチップのハンダバンプの中
心部を合わせた状態でＩＣチップを基板に向かって押圧
することにより、ハンダバンプ中に支柱を押し込み、こ
の状態でハンダバンプのリフローを行うことによって得
ることができる。従って、ＩＣチップの基板への仮止め
時にフランクス等の接着荊が不要になり、パッドとハン
ダバンプとの接合がより確実になる。Function> The bonding structure of the present invention is achieved by forming a metal support on the pad of the substrate, and pressing the IC chip toward the substrate with the center of the solder bump of the IC chip aligned with the support. , can be obtained by pushing a support into a solder bump and reflowing the solder bump in this state. Therefore, when temporarily fixing the IC chip to the substrate, there is no need for adhesives such as Franks, and the bonding between the pads and the solder bumps becomes more reliable.
〈実施例〉 第１図は本発明実施例の縦断面図である。<Example> FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
基板１上にＩＣチップ２が実装されており、基板のバッ
ド１ａとＩＣチップの電極２ａとはハンダバンプ３によ
って電気的に接続されている。また、ハンダバンプ３の
内部に、パッド１ａ上に植設された円柱形状のＣｕ製支
柱４が埋め込まれている。An IC chip 2 is mounted on a substrate 1, and a pad 1a of the substrate and an electrode 2a of the IC chip are electrically connected by solder bumps 3. Furthermore, a cylindrical column-shaped support column 4 made of Cu is embedded inside the solder bump 3 and is planted on the pad 1a.
以上の構造の製造手順を第２図に示す。The manufacturing procedure for the above structure is shown in FIG.
まず、第２図（ａ）に示すように、基板１の表面を、パ
ソド１ａの支柱形成部が露呈するように被覆した後、Ａ
Ｉ製薄膜６を一様に形成し、そのＡＩ！！！薄膜６の表
面上を、支柱形成部に相応する部分を除いてポリイミド
製厚膜５により被覆しておく。このポリイミド製厚膜５
の膜厚は７０μｍ程度とする。また、ポリイミド製厚膜
５は、後の工程において除去する必要があるので、１０
０℃程度のソフトベークのみを施しておく。First, as shown in FIG. 2(a), the surface of the substrate 1 is coated so that the pillar forming portions of the pads 1a are exposed, and then A
A thin film 6 made of AI is uniformly formed, and the AI! ! ! The surface of the thin film 6 is covered with a polyimide thick film 5 except for the portions corresponding to the pillar forming portions. This polyimide thick film 5
The film thickness is approximately 70 μm. In addition, since the polyimide thick film 5 needs to be removed in a later process,
Only perform a soft bake at around 0°C.
次に、Ｃｕメッキ浴中でポリイミド製厚膜５をマスクと
して、ＡＩ製薄膜６を電流通路とする電解メッキにより
、パッド１ａ上に高さ５０〜７０ｌＪｍ程度のＣｕ製支
柱４を形成した後（第２図〔ｂ〕）、ポリイミド製厚膜
５を有機溶媒により除去し、次いで、Ａｌ製薄膜６およ
びガラス膜７をエッチングにより除去する（第２図〔Ｃ
〕）。なお、ＡＩ製薄膜６エッチャントとしてはリン酸
系の溶液、また、ガラス膜７のエッチャントとしてはＢ
ＨＦ（バッファードフッ酸）を用いる。Next, a Cu support column 4 with a height of about 50 to 70 lJm is formed on the pad 1a by electroplating in a Cu plating bath using the polyimide thick film 5 as a mask and the AI thin film 6 as a current path. (Fig. 2 [b]), the polyimide thick film 5 is removed using an organic solvent, and then the Al thin film 6 and glass film 7 are removed by etching (Fig. 2 [C]
]). The etchant for the AI thin film 6 was a phosphoric acid solution, and the etchant for the glass film 7 was B.
Use HF (buffered hydrofluoric acid).
一方、ＩＣチップ２の電極２ａに公知の方法によりハン
ダバンプを形成しておく。このＩＣチップ２を、第２図
（ｄ）に示すように、ハンダバンプ３の中心がパッド１
ａ上の支柱４の中心に一致するように位置合わせを行っ
た後、ＩＣチップ２を基板１に向かって押圧し、ハンダ
バンプ３内部に支柱４を押し込むことによってＩＣチフ
プ２を基板１上に仮止めする（第２図〔ｅ〕）。この状
態で、ハンダバンプ３のリフローを行うことによって、
第１図に示すような接合構造を得る．ここで、ハンダバ
ンプ３の表面には、その製造上の都合により酸化膜が存
在するが、ハンダバンプ３に支柱４を押し込むことによ
り、その個所の酸化膜は破壊される。この破壊部は、リ
フロ一時にハンダバンプ３が表面張力により球形になろ
うとする力によって広がり、ハンダバンプ３のパフド１
ａに濡れるべき部分には純粋なハンダ露呈することにな
る。従って、ハンダバンプ３とパッド１ａとの接合の確
実性を高めることができる。また、メッキ時のマスク材
料としてポリイミドを用いることにより、Ｃｕ製支柱４
を、直径２０μｍ、高さ．５０〜７０μｍ程度の形状寸
法に形成できるので、ハンダバンプの直径が例えば１０
０μｍ程度とすれば充分に挿入できる。Meanwhile, solder bumps are formed on the electrodes 2a of the IC chip 2 by a known method. As shown in FIG. 2(d), this IC chip 2 is connected so that the center of the solder bump 3 is at the pad 1.
After aligning the center of the pillar 4 on the top a, press the IC chip 2 toward the board 1 and push the pillar 4 into the solder bump 3 to temporarily place the IC chip 2 on the board 1. Stop (Figure 2 [e]). In this state, by reflowing the solder bump 3,
A bonded structure as shown in Figure 1 is obtained. Here, an oxide film exists on the surface of the solder bump 3 due to manufacturing reasons, but by pushing the pillar 4 into the solder bump 3, the oxide film at that location is destroyed. This broken part spreads due to the force of the solder bump 3 trying to become spherical due to surface tension during reflow, and the puffed part 1 of the solder bump 3 spreads.
Pure solder will be exposed in areas that should be wetted by a. Therefore, the reliability of bonding between the solder bump 3 and the pad 1a can be increased. In addition, by using polyimide as a mask material during plating, the Cu pillars 4
is 20 μm in diameter and 20 μm in height. Since the solder bump can be formed into a shape and size of about 50 to 70 μm, the diameter of the solder bump is, for example, 10 μm.
If the thickness is approximately 0 μm, sufficient insertion can be achieved.
なお、支柱４の断面形状は、ポリイミド製厚膜のパター
ンニングの容易さから、円形が一般的であるが、例えば
矩形であってもよいし、あるいは、ＩＣチップの位置合
わせを行う際に、その画像処理が容易な形状、例えば十
字形等であってもよい。Note that the cross-sectional shape of the support column 4 is generally circular for ease of patterning a thick polyimide film, but it may also be rectangular, for example, or when aligning the IC chip, The shape may be a shape that facilitates image processing, such as a cross shape.
また、支柱４の材料としては、メッキ法により基板のパ
ッド上に形成できる金属であれば、何ら限定を受けない
が、接続の確実性をより高めるという点から、例えばＣ
ｕ ＳＮ ｉ等、ハンダとの゛接合性が高い金属が好
ましい。The material for the pillar 4 is not limited to any metal as long as it can be formed on the pad of the board by plating, but from the point of view of increasing the reliability of the connection, for example, C.
A metal that has high bondability with solder, such as uSNi, is preferable.
〈発明の効果〉
本発明によれば、基板のパッドに植設した金属製支柱に
よって、Ｉ Ｃ’チップの基板への仮止めが行えるので
、従来、接合不良の原因となっていたフラックス等の仮
止め剤が不要になり、ＩＣチップと基板との確実に接続
できる。これによって製品の信頬性およひその歩留まり
が向上する。<Effects of the Invention> According to the present invention, since the IC' chip can be temporarily fixed to the substrate using metal supports embedded in the pads of the substrate, flux, etc., which conventionally caused bonding failures, can be removed. No temporary adhesive is required, and the IC chip and board can be reliably connected. This improves product reliability and yield.
第１図は本発明実施例の縦断面図、 第２図はその製造手順の説明図である。 １ ・ １ ａ ・ ２ ・ ２ａ ・ ３ ・ ４ ・ ・基板 ・パッド ・ＩＣチップ ・電極 ●ハンダバンプ ・金属製の支柱 FIG. 1 is a longitudinal sectional view of an embodiment of the present invention; FIG. 2 is an explanatory diagram of the manufacturing procedure. 1・ １ a ・ 2・ 2a・ 3・ 4・ ·substrate ·pad ・IC chip ·electrode ●Solder bump ・Metal support
Claims (1)
プとパッドとの接合構造であって、上記パッドに植設さ
れた金属製支柱が上記ハンダバンプ内部に埋め込まれて
いることを特徴とする、ハンダバンプとパッドとの接合
構造。A bonding structure of a solder bump and a pad bonded by a flip-chip mounting method or the like, characterized in that a metal support installed in the pad is embedded inside the solder bump. Joint structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1053294A JPH02232946A (en) | 1989-03-06 | 1989-03-06 | Junction structure of solder bump with pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1053294A JPH02232946A (en) | 1989-03-06 | 1989-03-06 | Junction structure of solder bump with pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02232946A true JPH02232946A (en) | 1990-09-14 |
Family
ID=12938707
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1053294A Pending JPH02232946A (en) | 1989-03-06 | 1989-03-06 | Junction structure of solder bump with pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02232946A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523697A (en) * | 1993-09-03 | 1996-06-04 | Micron Technology, Inc. | Testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof |
| US5585282A (en) * | 1991-06-04 | 1996-12-17 | Micron Technology, Inc. | Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor |
| US5849633A (en) * | 1994-03-07 | 1998-12-15 | Micron Technology, Inc. | Electrically conductive projections and semiconductor processing method of forming same |
| US6121062A (en) * | 1993-08-13 | 2000-09-19 | Fujitsu Limited | Process of fabricating semiconductor unit employing bumps to bond two components |
| US7476564B2 (en) * | 2005-09-08 | 2009-01-13 | Advanced Semiconductor Engineering Inc. | Flip-chip packaging process using copper pillar as bump structure |
-
1989
- 1989-03-06 JP JP1053294A patent/JPH02232946A/en active Pending
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585282A (en) * | 1991-06-04 | 1996-12-17 | Micron Technology, Inc. | Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor |
| US6121062A (en) * | 1993-08-13 | 2000-09-19 | Fujitsu Limited | Process of fabricating semiconductor unit employing bumps to bond two components |
| US6686758B1 (en) | 1993-09-03 | 2004-02-03 | Micron Technology, Inc. | Engagement probe and apparatuses configured to engage a conductive pad |
| US7098475B2 (en) | 1993-09-03 | 2006-08-29 | Micron Technology, Inc. | Apparatuses configured to engage a conductive pad |
| US6462571B1 (en) | 1993-09-03 | 2002-10-08 | Micron Technology, Inc. | Engagement probes |
| US7330036B2 (en) | 1993-09-03 | 2008-02-12 | Micron Technology, Inc. | Engagement Probes |
| US6124721A (en) * | 1993-09-03 | 2000-09-26 | Micron Technology, Inc. | Method of engaging electrically conductive test pads on a semiconductor substrate |
| US6127195A (en) * | 1993-09-03 | 2000-10-03 | Micron Technology, Inc. | Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus |
| US7116118B2 (en) | 1993-09-03 | 2006-10-03 | Micron Technology, Inc. | Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
| US5523697A (en) * | 1993-09-03 | 1996-06-04 | Micron Technology, Inc. | Testing apparatus for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof |
| US6380754B1 (en) | 1993-09-03 | 2002-04-30 | Micron Technology, Inc. | Removable electrical interconnect apparatuses including an engagement proble |
| US6573740B2 (en) | 1993-09-03 | 2003-06-03 | Micron Technology, Inc. | Method of forming an apparatus configured to engage an electrically conductive pad on a semiconductive substrate and a method of engaging electrically conductive pads on a semiconductive substrate |
| US7026835B2 (en) | 1993-09-03 | 2006-04-11 | Micron Technology, Inc. | Engagement probe having a grouping of projecting apexes for engaging a conductive pad |
| US6833727B2 (en) | 1993-09-03 | 2004-12-21 | Micron Technology, Inc. | Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability |
| US6392426B2 (en) | 1993-09-03 | 2002-05-21 | Micron Technology, Inc. | Methods of forming apparatuses and a method of engaging electrically conductive test pads on a semiconductor substrate |
| US6614249B1 (en) | 1993-09-03 | 2003-09-02 | Micron Technology, Inc. | Methods of forming apparatuses and a method of engaging electrically conductive test pads on a semiconductor substrate |
| US6657450B2 (en) | 1993-09-03 | 2003-12-02 | Micron Technology, Inc. | Methods of engaging electrically conductive test pads on a semiconductor substrate removable electrical interconnect apparatuses, engagement probes and removable engagement probes |
| US6670819B2 (en) | 1993-09-03 | 2003-12-30 | Micron Technology, Inc. | Methods of engaging electrically conductive pads on a semiconductor substrate |
| US6248962B1 (en) | 1994-03-07 | 2001-06-19 | Micron Technology, Inc. | Electrically conductive projections of the same material as their substrate |
| US6093643A (en) * | 1994-03-07 | 2000-07-25 | Micron Technology, Inc. | Electrically conductive projections and semiconductor processing method of forming same |
| US6255213B1 (en) | 1994-03-07 | 2001-07-03 | Micron Technology, Inc. | Method of forming a structure upon a semiconductive substrate |
| US5869787A (en) * | 1994-03-07 | 1999-02-09 | Micron Technology, Inc. | Electrically conductive projections |
| US5849633A (en) * | 1994-03-07 | 1998-12-15 | Micron Technology, Inc. | Electrically conductive projections and semiconductor processing method of forming same |
| US6441320B2 (en) | 1994-03-07 | 2002-08-27 | Micron Technology, Inc. | Electrically conductive projections having conductive coverings |
| US7476564B2 (en) * | 2005-09-08 | 2009-01-13 | Advanced Semiconductor Engineering Inc. | Flip-chip packaging process using copper pillar as bump structure |
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