JPH02230726A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPH02230726A JPH02230726A JP5145389A JP5145389A JPH02230726A JP H02230726 A JPH02230726 A JP H02230726A JP 5145389 A JP5145389 A JP 5145389A JP 5145389 A JP5145389 A JP 5145389A JP H02230726 A JPH02230726 A JP H02230726A
- Authority
- JP
- Japan
- Prior art keywords
- group
- implanted
- ions
- substrate
- arsenic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 33
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 229910021478 group 5 element Inorganic materials 0.000 claims abstract description 8
- 229910021480 group 4 element Inorganic materials 0.000 claims abstract 3
- 239000013078 crystal Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 abstract description 26
- 229910052785 arsenic Inorganic materials 0.000 abstract description 20
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 20
- 238000005468 ion implantation Methods 0.000 abstract description 20
- 230000004913 activation Effects 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 10
- 239000011574 phosphorus Substances 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 230000003213 activating effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 239000000370 acceptor Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、素子（ＦＥＴ）間の電気的分離が安定に実現
できる化合物半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a compound semiconductor device that can stably realize electrical isolation between elements (FETs).
一ｉに、ガリウム砒素（ＧａＡｓ）結晶を利用したＦＥ
Ｔは、高抵抗結晶基板表面にドナー元素をイオン注入す
ることにより、ｎ形活性層を形成して製造している。従
って、
（１）基板が十分高抵抗で素子間の分離が安定に実現で
きること。First, FE using gallium arsenide (GaAs) crystal
T is manufactured by forming an n-type active layer by ion-implanting a donor element into the surface of a high-resistance crystal substrate. Therefore, (1) The substrate must have a sufficiently high resistance to stably achieve isolation between elements.
（２）ドナーとアクセプター濃度の差であるキャリア濃
度と注入量の比が高いこと。即ち、ｎ形活性層の電気特
性を支配する活性化率が高いこと。(2) The ratio between the carrier concentration, which is the difference between donor and acceptor concentrations, and the injection amount is high. That is, the activation rate that governs the electrical characteristics of the n-type active layer is high.
などの条件が高性能集積回路を実現する場合に極めて重
要である。Conditions such as these are extremely important when realizing high-performance integrated circuits.
現在、高抵抗ＧａＡｓ結晶は、結晶中の主残留不純物で
ある炭素によって形成されるアクセブターを砒素（Ａｓ
）がガリウム（Ｇａ）格子位置に置換された点欠陥ＡＳ
Ｇ．を基本構成要素に持つドナーによって補償して実現
している。このドナーはＥＬ２と呼ばれ、結晶が砒素（
Ａｓ）過剰な状態で形成される。Currently, high-resistance GaAs crystals are manufactured using arsenic (As) as the acceptor formed by carbon, which is the main residual impurity in the crystal.
) is substituted at the gallium (Ga) lattice position AS
G. This is achieved through compensation by donors who have these as basic components. This donor is called EL2, and the crystal is arsenic (
As) formed in excess.
一方、ガリウム砒素のｎ形活性層の形成には、注入元素
としてシリコン（Ｓｉ）が最も一般的に用いられている
。シリコンは■族元素であるため、ｍ−ｖ族化合物半導
体であるＧａＡｓ結晶中では両性元素として作用し、■
族元素であるガリウム（Ｇａ）の格子位置に置換されて
ドナーとなるだけでなく、■族元素である砒素（Ａｓ）
の格子位置にも置換されてアクセプターとなる。そこで
、シリコンが砒素格子位置に置換されることを抑えて活
性化率を上昇させるため、現状では砒素過剰な状態の結
晶基板を用いているのが一般的である。On the other hand, silicon (Si) is most commonly used as the implanted element to form an n-type active layer of gallium arsenide. Silicon is a group element, so it acts as an amphoteric element in GaAs crystal, which is an m-v group compound semiconductor, and
Not only is it substituted at the lattice position of gallium (Ga), a group element, to become a donor, but also arsenic (As, a group element)
It is also substituted at the lattice position of and becomes an acceptor. Therefore, in order to increase the activation rate by suppressing the substitution of silicon at arsenic lattice positions, it is common practice at present to use a crystal substrate with an excess of arsenic.
しかしながら上記説明のように活性化率は、砒素過剰度
を増大させることにより上昇させることができるが、同
時にＥＬ２の濃度が増加するため、結晶基板が低抵抗化
するという欠点があった。However, as explained above, although the activation rate can be increased by increasing the arsenic excess, the concentration of EL2 increases at the same time, which has the disadvantage that the resistance of the crystal substrate becomes low.
また、第４図は基板抵抗と活性化率の関係を示した特性
図である。この図から明らかなように現状技術では、高
性能集積回路実現に必要な基板高抵抗化と注入シリコン
における活性化率の向上とを同時に満たすことは不可能
である。Moreover, FIG. 4 is a characteristic diagram showing the relationship between substrate resistance and activation rate. As is clear from this figure, with the current technology, it is impossible to simultaneously increase the resistance of the substrate and improve the activation rate of implanted silicon, both of which are necessary to realize a high-performance integrated circuit.
このため、一般には上記２つの要求のバランスをとって
、抵抗が１０７Ω−ｃｍ程度の基板を用いていた。この
場合、炭素アクセプター、ＥＬ２ドナーの濃度はそれぞ
れ１０”／ ｃ ｍ’ ， ｌＱ１６／ ｃ ｍ３程度
で、基板はＥＬ２ドナー過剰な状態となっていた。For this reason, in general, a substrate having a resistance of about 10<7 >[Omega]-cm is used to balance the above two requirements. In this case, the concentrations of the carbon acceptor and EL2 donor were about 10"/cm' and 1Q16/cm3, respectively, and the substrate was in a state where the EL2 donor was in excess.
本発明は上記の欠点を解消するためになされたもので、
ガリウム砒素結晶からなる基板に■族元素及びＶ族元素
をイオン注入して活性層を形成する工程と、イオン注入
した基板を熱処理する工程とを有している。The present invention has been made to solve the above-mentioned drawbacks.
The method includes a step of forming an active layer by ion-implanting group (I) elements and group V elements into a substrate made of gallium arsenide crystal, and a step of heat-treating the ion-implanted substrate.
ガリウム砒素基板に■族元素イオンと■族元素イオンと
を注入して活性層を形成する。An active layer is formed by implanting group (1) group element ions and (2) group element ions into a gallium arsenide substrate.
以下、本発明の実施例を図に従って説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明に係る一実施例を示した
化合物半導体装置の製造方法の断面図である。FIGS. 1A to 1C are cross-sectional views of a method for manufacturing a compound semiconductor device showing an embodiment of the present invention.
まず、同図（ａ）に示すようにＧａＡｓ基板１の主面上
にＲ （ｐ）又は砒素（Ａｓ）等の■族元素イオン２を
注入する。これにより、注入層３ａを形成する。First, as shown in FIG. 2A, ions 2 of group II elements such as R (p) or arsenic (As) are implanted onto the main surface of a GaAs substrate 1. This forms the injection layer 3a.
次に、注入層３ａ内にシリコン（Ｓｉ）等の■族元素イ
オン４を注入し、注入層３を形成する（同図（ｂ））。Next, group II element ions 4 such as silicon (Si) are implanted into the implantation layer 3a to form the implantation layer 3 (FIG. 3(b)).
そして、上記イオン注入が完了した後、ＳｉＮ等からな
る熱処理保護膜を例えば１５００人の膜厚に堆積させる
（同図（Ｃ））。その後、図示していないが、電気炉等
において温度８００℃で１０〜２０分程度の熱処理を行
なう。After the ion implantation is completed, a heat-treated protective film made of SiN or the like is deposited to a thickness of, for example, 1,500 mm (FIG. 4(C)). Thereafter, although not shown, heat treatment is performed in an electric furnace or the like at a temperature of 800° C. for about 10 to 20 minutes.
次に゛、第２図は■族元素イオン注入濃度と■族元素注
入領域の基板抵抗の関係を示した特性図である。ここで
は、ＧａＡｓ基板に■族元素のみのイオン注入を行ない
、基板表面から深さ０．１５μｍまでの濃度が均一とな
るように異なるエネルギーで複数回行なった結果を示し
ている。なお、記号ａはｇ（Ｐ）イオンを注入した場合
の特性、記号ｂは砒素（Ａｓ）イオンを注入した場合の
特性を示している。Next, FIG. 2 is a characteristic diagram showing the relationship between the ion implantation concentration of the group (II) element and the substrate resistance of the region where the group (II) element is implanted. Here, the results are shown in which ion implantation of only group (1) elements into a GaAs substrate was performed multiple times at different energies so that the concentration was uniform from the substrate surface to a depth of 0.15 μm. Note that the symbol a indicates the characteristics when g(P) ions are implanted, and the symbol b indicates the characteristics when arsenic (As) ions are implanted.
同図より明らかなように、燐、砒素いずれにおいても、
■族元素のイオン注入濃度が５ ＸＩＯ”／ｃｍ３を越
えると高抵抗化に対し有効となることが判る。また、Ｗ
（Ｐ）イオン注入は砒素（Ａｓ）イオン注入よりも高
抵抗化に対し有効であり、イオン注入濃度が１０′８／
Ｃｍ３で基板抵抗は最高となる。As is clear from the figure, both phosphorus and arsenic
It can be seen that when the ion implantation concentration of the group ■ element exceeds 5XIO"/cm3, it becomes effective for increasing the resistance.
(P) ion implantation is more effective than arsenic (As) ion implantation for increasing resistance, and the ion implantation concentration is 10'8/
The substrate resistance is highest at Cm3.
これらの特性は、次のように説明することができる。即
ち、ＧａＡｓ基板にイオン注入を行なうと注入層内には
高濃度の砒素（Ａｓ）空孔とガリウム（Ｇａ）空孔とが
形成されることが知られている（Ｌ．Ｒ．Ｃｈｒｉｓｔ
ｅｌ，Ｊ．Ｆ．Ｇｉｂｂｏｎｓ Ｊｏｕｎａｌ ｏｆ八
ｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ，Ｖｏｌｕｍｅ ５
２，ｐ．５０５０ 〔１９８１） ） 。These characteristics can be explained as follows. That is, it is known that when ions are implanted into a GaAs substrate, highly concentrated arsenic (As) vacancies and gallium (Ga) vacancies are formed in the implanted layer (L.R. Christ
el, J. F. Gibbons Journal of 8 pplied Physics, Volume 5
2, p. 5050 [1981)).
従って、注入したイオンが■族元素の場合、注入後の熱
処理工程で■族元素である砒素の空孔が選択的に注入し
た■族元素によって埋められ、この結果高濃度のガリウ
ム空孔が残される。そして、ガリウム空孔はＧａＡＳ結
晶内ではアクセプターとして作用する。このガリウム空
孔がＧａＡｓ基板内に過剰に存在していたＥＬ２ドナー
を補償するため、■族元素注入を行なうと基板抵抗は第
２図に示すように高抵抗化することになる。Therefore, when the implanted ions are group III elements, the vacancies of arsenic, which is a group III element, are selectively filled by the implanted group III elements in the heat treatment process after implantation, and as a result, a high concentration of gallium vacancies are left behind. It will be done. The gallium vacancies act as acceptors within the GaAS crystal. In order to compensate for the EL2 donors existing in excess in the GaAs substrate, the gallium vacancies cause the substrate resistance to become high, as shown in FIG. 2, when group Ⅰ elements are implanted.
一方、砒素（Ａｓ）は燐（Ｐ）よりも質量数が大きいた
め、砒素イオン注入の場合、イオン注入による格子の乱
れが大きく、温度８００℃の熱処理では格子が完全に回
復することができない。このため、■族元素の砒素空孔
を効果的に埋めきれず、砒素イオン注入では高抵抗化の
効率が低下することになる。On the other hand, since arsenic (As) has a larger mass number than phosphorus (P), in the case of arsenic ion implantation, the lattice is largely disturbed by the ion implantation, and the lattice cannot be completely recovered by heat treatment at a temperature of 800°C. For this reason, the arsenic vacancies of the group Ⅰ element cannot be filled effectively, and the efficiency of increasing the resistance in arsenic ion implantation is reduced.
また、第３図はＶ族元素イオン注入濃度と注入シリコン
の活性率との関係を示した特性図である。Further, FIG. 3 is a characteristic diagram showing the relationship between the implanted group V element ion concentration and the activation rate of implanted silicon.
ここで、Ｖ族元素のイオン注入条件は第２図と同一で、
■族元素にあたるシリコン（Ｓｉ）はエネルギー５Ｑｋ
ｅＶで面積密度５ Ｘ １０′２／ ｃ ｍ２で注入し
ている。なお、記号ａは燐（Ｐ）イオンを注入した場合
の特性、記号ｂは砒素（Ａｓ）イオンを注入した場合の
特性を示している。Here, the ion implantation conditions for group V elements are the same as in Figure 2,
■Silicon (Si), which is a group element, has an energy of 5Qk
It is implanted at eV with an areal density of 5 x 10'2/cm2. Note that the symbol a indicates the characteristics when phosphorus (P) ions are implanted, and the symbol b indicates the characteristics when arsenic (As) ions are implanted.
さて、同図より明らかなように、燐（ｐ），砒素（Ａｓ
）いずれも■族元素のイオン注入濃度が５ＸＩＯ”／ｃ
ｍ３を越えると高活性化率化に対して有効であることが
判る。Now, as is clear from the same figure, phosphorus (p), arsenic (As
) In both cases, the ion implantation concentration of group ■ elements is 5XIO"/c
It can be seen that exceeding m3 is effective for increasing the activation rate.
これは、Ｖ族元素のイオン注入によって形成さたＧａＡ
ｓ空孔をシリコンが選択的に埋めてドナーとなるためで
ある。This is GaA formed by ion implantation of group V elements.
This is because silicon selectively fills the s-vacancies and becomes a donor.
また、燐イオン注入は砒素イオン注入より孔活性化に対
して有効であり、イオン注入濃度が１０′８７ｃｍ’で
活性化率は最高となることも判る。It is also seen that phosphorus ion implantation is more effective for pore activation than arsenic ion implantation, and that the activation rate is highest when the ion implantation concentration is 10'87 cm'.
これは、砒素（Ａｓ）が燐（Ｐ）に比べて質量数が大き
いため、砒素注入の場合イオン注入による格子の・乱れ
が大きく、温度８００℃の熱処理では格子が完全に回復
せず、シリコン（Ｓｉ）が電気的に活性し難くなるため
である。また、これと同じ原因で、燐イオン注入の場合
も燐の濃度が１０１８７ｃｍ３を越えると活性化率は低
下傾向を示している。This is because arsenic (As) has a larger mass number than phosphorus (P), so in the case of arsenic implantation, the lattice disorder caused by ion implantation is large, and the lattice is not completely recovered by heat treatment at a temperature of 800°C, and silicon This is because (Si) becomes difficult to be electrically activated. Furthermore, for the same reason, in the case of phosphorus ion implantation, the activation rate tends to decrease when the phosphorus concentration exceeds 10187 cm3.
このように本実施例における化合物半導体装置の製造方
法は、■族元素イオン（燐，砒素等）と■族元素イオン
（シリコン等）とをＧａＡｓ基板に注入することにより
、ＧａＡｓ基板の高抵抗化と活性化率の向上とを同時に
実施することができる。As described above, the method for manufacturing a compound semiconductor device in this example is to increase the resistance of the GaAs substrate by implanting group Ⅰ element ions (phosphorus, arsenic, etc.) and group Ⅰ element ions (silicon, etc.) into the GaAs substrate. and improvement of the activation rate can be implemented simultaneously.
なお、上記実施例では、■族元素イオンをＧａＡＳ基板
に注入した後、■族元素イオンを注入したが、■族元素
イオンを■族元素イオンよりも先に注入してもよい。Incidentally, in the above embodiment, the group (II) element ions were implanted after the group (II) element ions were implanted into the GaAS substrate, but the group (II) element ions may be implanted before the group (II) element ions.
また、上記実施例では、熱処理保護膜にＳｉＮ膜を用い
て説明したが、Ｓ ｉＯ ｚ膜或いはＡＩ！Ｎを用いて
もよい。さらに、熱処理保護膜を用いなくてもよい。Furthermore, in the above embodiments, a SiN film was used as the heat treatment protective film, but a SiOz film or an AI! N may also be used. Furthermore, it is not necessary to use a heat-treated protective film.
また、上記実施例では、熱処理として電気炉を使用した
が、赤外線或いはレーザ光を用いてもよい。Furthermore, in the above embodiments, an electric furnace was used for the heat treatment, but infrared rays or laser light may also be used.
以上説明したように本発明は、■族元素イオンと■族元
素イオンとをガリウム砒素基板に注入することにより、
ガリウム砒素基板の高抵抗化と活性化率の向上とを同時
に実施することができる。As explained above, in the present invention, by implanting group Ⅰ element ions and group Ⅰ element ions into a gallium arsenide substrate,
It is possible to simultaneously increase the resistance of the gallium arsenide substrate and improve the activation rate.
第１図（ａ）〜（Ｃ）は本発明に係る一実施例を示した
化合物半導体基板の製造方法の断面図、第２図はＶ族元
素イオン注入濃度と■族元素注入領域の基板抵抗の関係
を示した特性図、第３図は■族元素イオン注入濃度と注
入シリコンの活性率との関係を示した特性図、第４図は
基仮抵抗と活性化率の関係を示した特性図である。
■・・・ＧａＡｓ基板、２・・・■族元素イオン、３，
３ａ・・・注入層、４・・・■族元素イオン、５・・・
熱保処理護膜。
特許出願人 日本電信電話株式会社
代 理 人 山川政樹
第
図
ー−−メー一−コ
／／／／
笥
！
茶扱ギヘ琉
（ｎ−ｃｍ）
報４，Ｘ：＝−負，＼（票幣９←とFIGS. 1(a) to (C) are cross-sectional views of a method for manufacturing a compound semiconductor substrate showing an embodiment of the present invention, and FIG. 2 is a graph showing the group V element ion implantation concentration and the substrate resistance of the group II element implanted region. Figure 3 is a characteristic diagram showing the relationship between the implanted concentration of group III element ions and the activation rate of implanted silicon, and Figure 4 is a characteristic diagram showing the relationship between the basic resistance and activation rate. It is a diagram. ■...GaAs substrate, 2...group ■ element ions, 3,
3a... Injection layer, 4... Group ■ element ion, 5...
Heat protection treatment film. Patent Applicant: Nippon Telegraph and Telephone Corporation Agent: Masaki Yamakawa - Maeichi-ko//// 笥! Tea handling Gihe Ryu (n-cm) Report 4,
Claims (1)
をイオン注入して活性層を形成する工程と、 前記イオン注入した基板を熱処理する工程とを有するこ
とを特徴とする化合物半導体装置の製造方法。[Claims] The method is characterized by comprising a step of ion-implanting group IV elements and group V elements into a substrate made of gallium arsenide crystal to form an active layer, and a step of heat-treating the ion-implanted substrate. A method for manufacturing a compound semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5145389A JPH02230726A (en) | 1989-03-03 | 1989-03-03 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5145389A JPH02230726A (en) | 1989-03-03 | 1989-03-03 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02230726A true JPH02230726A (en) | 1990-09-13 |
Family
ID=12887349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5145389A Pending JPH02230726A (en) | 1989-03-03 | 1989-03-03 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02230726A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6247121A (en) * | 1985-08-26 | 1987-02-28 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62243323A (en) * | 1986-04-15 | 1987-10-23 | Matsushita Electric Ind Co Ltd | Formation of active layer of iii-v compound semiconductor |
| JPS63102226A (en) * | 1986-10-17 | 1988-05-07 | Nippon Telegr & Teleph Corp <Ntt> | Formation of n-type active semiconductor layer to iii-v compound semiconductor substrate |
-
1989
- 1989-03-03 JP JP5145389A patent/JPH02230726A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6247121A (en) * | 1985-08-26 | 1987-02-28 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62243323A (en) * | 1986-04-15 | 1987-10-23 | Matsushita Electric Ind Co Ltd | Formation of active layer of iii-v compound semiconductor |
| JPS63102226A (en) * | 1986-10-17 | 1988-05-07 | Nippon Telegr & Teleph Corp <Ntt> | Formation of n-type active semiconductor layer to iii-v compound semiconductor substrate |
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