JPS6194321A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6194321A JPS6194321A JP21664784A JP21664784A JPS6194321A JP S6194321 A JPS6194321 A JP S6194321A JP 21664784 A JP21664784 A JP 21664784A JP 21664784 A JP21664784 A JP 21664784A JP S6194321 A JPS6194321 A JP S6194321A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- annealing
- substrate
- implanted
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関するものであり、特
に半導体基板にイオン注入された不純物を山、気的に活
性化するためのアニール方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an annealing method for vaporically activating impurities ion-implanted into a semiconductor substrate. be.
従来例の構成とその問題点
半導体基板に不純物を＋４人する方法としてイオン注入
法が用いられている。イオン注入法は半導体装置の活性
層の厚さや注入原子プロファイルの再現性や制御性が非
常によく、また注入不純物種を自由に選択できるという
特徴がある。しかし、イオン注入により半導体基板に不
純物を導入する場合、不純物を電気的に活性化するため
、また圧入１てより発生した格子欠陥を除去するための
アニールが必要となる。Conventional Structure and Problems Ion implantation is used as a method for adding impurities to a semiconductor substrate. The ion implantation method is characterized by very good reproducibility and controllability of the thickness of the active layer of a semiconductor device and the profile of implanted atoms, and the type of implanted impurity can be freely selected. However, when introducing impurities into a semiconductor substrate by ion implantation, annealing is required to electrically activate the impurities and to remove lattice defects generated during press-fitting.
従来、例えばＧａＡｓ結晶のイオン注入後のアニールは
、７００’Ｃ〜９００°Ｃで行なわれている。Conventionally, for example, annealing after ion implantation of a GaAs crystal is performed at 700'C to 900C.
しかし高温によるアニールのため、蒸気圧の高いＡｓ
が解離し半導体装置の特性が劣化する。このためにＧａ
Ａｓ結晶基板１上に保護膜３（！−衣表面被着して基板
１に形成されたイオン注入／ｆｉ１４’ｔ ７二−ルす
ることが試みられている（第１図）。このＮ Ｍｉ’ｒ
ｍ ３ （！： ｔ、 テｌ’！ ”” ０２ ｙ
５ｉ３Ｎ４ｒ ＡＩ！Ｎ Ａｌ２Ｏ３１（！：が用いら
れているが、ピンホールの存在やストレスｌｆこより注
入されたイオンの活性化や欠陥の回復が充分なされない
ことがあり、１だ半導体基板１に直接絶縁ｉｔ、Ｔ ３
を形成することから製造工程が填雑になる。However, due to high temperature annealing, As has a high vapor pressure.
is dissociated and the characteristics of the semiconductor device deteriorate. For this purpose, Ga
Attempts have been made to implant a protective film 3 on the As crystal substrate 1 (Fig. 1). 'r
m 3 (!: t, tel'! ”” 02 y
5i3N4r AI! NAl2O31 (!:) is used, but due to the presence of pinholes and stress lf, the activation of implanted ions and the recovery of defects may not be sufficient. 3
The manufacturing process becomes complicated.
−また、新しいアニール方法として保獲膜３を用いない
でアニールする方法がある。これは、アル′ ミン（
Ａ ｓ Ｈ３）の雰囲気中でＡｓの圧力をかけることに
よりＡｓ の解離を防いでいる。しかし現在のところ充
分確立された技術とはなっていない。- Also, as a new annealing method, there is a method of annealing without using the retention film 3. This is aluminum (
Dissociation of As is prevented by applying pressure of As in an atmosphere of As H3). However, it is not a sufficiently established technology at present.
発明の目的
本発明は従来の欠点を非算に簡単な方法で克服し、信頼
性の高い半導体装置の製造方法、特にアニール方法を提
供するものである。OBJECTS OF THE INVENTION The present invention overcomes the conventional drawbacks in an extremely simple manner and provides a highly reliable method for manufacturing a semiconductor device, particularly an annealing method.
発明の構成
本発明の半導体装置の製造方法は不純物イオンが注入さ
れた第１の半導体基＋ｆｉをアニールする工程において
、アニールされる第１の半導体基板とは別の第２の半導
体基板を用意し、第２の半導体基板に絶縁膜層を形成し
、前記絶縁膜層と第１の半導体基板の不純物がイオン圧
入された面を密着させてアニールするも：）であろう
実畢例の説明
以下（（本発明の−−ノミ・殉例を１〕１而住；、、；
１ｌｊｊ ｌ−て１．）乱ｊに説明する。第２図は不
−ｊ！施辺Ｉを行明するだめの図面である。例えば半絶
縁性ＧａＡｓ ）Ｆ：仮１シて不純物としてｓｉ” ｆ
１２０ ＫｅＶで５ ｘ １ｏ１２ｃｍ−２ｉｆ 人
してイオ／ｌ主入層とを１杉成した試料のアニール；二
ついて説明する。一方、第２の半導体↓（仮としてＳｉ
基板２を用い、同基板２表面にばＳ １３ｅａ；’
；’： ３がＣＶＤ法により約２０００人形成されてい
る。Structure of the Invention In the method for manufacturing a semiconductor device of the present invention, in the step of annealing the first semiconductor substrate +fi into which impurity ions have been implanted, a second semiconductor substrate different from the first semiconductor substrate to be annealed is prepared. , an insulating film layer is formed on a second semiconductor substrate, and the insulating film layer and the surface of the first semiconductor substrate into which impurities have been ion-injected are brought into close contact and annealed. ((The present invention--flea and martyrdom 1) 1.
1ljj l-te1. ) Explain to Ranj. Figure 2 is F-j! This is a diagram showing the location of the construction site I. For example, semi-insulating GaAs)
Annealing of a sample with a main input layer of 5 x 1012cm-2if and a main input layer of 120 KeV; two explanations will be given below. On the other hand, the second semiconductor ↓ (temporarily Si
Using the substrate 2, if the surface of the substrate 2 is S13ea;'
;': Approximately 2,000 3 are formed using the CVD method.
前記第２の半導体基板Ｓｉ２上の５１３Ｎ４膜３と前記
不純物Ｓｉ＋が注入された第１の半導体装ｔ１２ＧａＡ
＋＋１の注入面を密着させて、−気炉中へ挿入しアニー
ルを行なう。例えばアニール温度として１−ｉ８５０°
Ｃ１アニ一ル時間としては３０分間である。本発明によ
るアニール方法によれば、従来のイオン圧入された半導
体基板に直接絶縁膜を形成しアニールする方法に較べて
、アニール特性がビンホール等の絶縁膜の膜質に影響さ
れることがない。513N4 film 3 on the second semiconductor substrate Si2 and the first semiconductor device t12GaA into which the impurity Si+ is implanted.
The injection surfaces of ++1 are brought into close contact with each other, and the sample is inserted into a -air furnace and annealed. For example, the annealing temperature is 1-i850°
The C1 annealing time is 30 minutes. According to the annealing method according to the present invention, the annealing characteristics are not affected by the film quality of the insulating film such as via holes, compared to the conventional method of directly forming an insulating film on a semiconductor substrate into which ions are implanted and then annealing it.
また、この方法によれば絶縁膜を用いないでアニールす
る方法に較べて、ア“ルミン（Ａｓ Ｈ３） 等の有毒
ガスを使用することなく簡便な装置でアニールすること
ができる。Further, according to this method, compared to a method of annealing without using an insulating film, annealing can be performed using a simple device without using toxic gas such as aluminum (As H3).
このようにしてアニールした場合、注入不純物の活性化
率およびアニールによる基板面内での活性化率のバラツ
キは従来の方法と同等あるいはそれ以上であった。When annealing was performed in this manner, the activation rate of the implanted impurity and the variation in the activation rate within the substrate surface due to annealing were equal to or higher than those of the conventional method.
以上の実施例の説明では第１の半導体基板としてＧａＡ
ｓを第２の半導体基板としてＳｔ を用いて説明した
が他の組み合せでも可能であるし、また絶縁膜として５
１３Ｎ４膜を用いたが他のＡｇ２Ｏ３やＡｌＮなどの絶
縁膜を用いてもよい。また、アニールされる基板を絶縁
膜のついた半導体基板ではさみ込んでアニールしてもよ
い。また実施例では電気炉アニールで説明を行なったが
フラッ／ユランプアニールなどの他のアニール方法でも
可能である。In the above description of the embodiment, GaA is used as the first semiconductor substrate.
Although the explanation has been made using St as the second semiconductor substrate, other combinations are also possible, and St as the insulating film.
Although the 13N4 film is used, other insulating films such as Ag2O3 and AlN may also be used. Alternatively, the substrate to be annealed may be sandwiched between semiconductor substrates having an insulating film and annealed. In addition, although electric furnace annealing has been described in the embodiment, other annealing methods such as flash/uramp annealing are also possible.
発明の効果
以上実施例で説明したようにして本発明の方法を用いて
アニールすれば、アニールされるべき半導体基板に直接
絶縁膜を形成する必要がなく半導体装置の製造工程が簡
略化され、従来と遜色のないアニール特性が得られる。Effects of the Invention If annealing is performed using the method of the present invention as explained in the embodiments, there is no need to directly form an insulating film on the semiconductor substrate to be annealed, simplifying the manufacturing process of semiconductor devices, and simplifying the manufacturing process of semiconductor devices. It provides annealing characteristics comparable to those of
１だ絶ζり）１４′！の１［構成された半導体基板は繰
返し使用可能である。1 daze ζri) 14'! (1) The constructed semiconductor substrate can be used repeatedly.
第１図は従来のアニール方法を説明する図、第２図は本
発明の一実癩例を説明するための図である。
１・・・・・第１の半導体基板、２・・・−第２の半導
イ４・基板、３・・・・・・絶縁膜、４・・・ 注入層
。FIG. 1 is a diagram for explaining a conventional annealing method, and FIG. 2 is a diagram for explaining an example of the present invention. DESCRIPTION OF SYMBOLS 1...First semiconductor substrate, 2...-Second semiconductor substrate 4, 3...Insulating film, 4... Injection layer.
Claims (2)
ニールする工程において前記第１の半導体基板とは別の
表面に絶縁膜層が形成された第２の半導体基板を用い、
前記第１の半導体基板の不純物がイオン注入された面と
前記第２の半導体基板上の絶縁膜層を密着させてアニー
ルすることを特徴とする半導体装置の製造方法。(1) In the step of annealing the first semiconductor substrate into which impurities have been ion-implanted, a second semiconductor substrate on which an insulating film layer is formed on a surface different from the first semiconductor substrate is used,
A method of manufacturing a semiconductor device, comprising: annealing a surface of the first semiconductor substrate into which impurity ions have been implanted and an insulating film layer on the second semiconductor substrate in close contact with each other;
第２の半導体基板の間に置きアニールすることを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor substrate is placed between two second semiconductor substrates whose insulating film layers face each other and is annealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21664784A JPS6194321A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21664784A JPS6194321A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6194321A true JPS6194321A (en) | 1986-05-13 |
Family
ID=16691715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21664784A Pending JPS6194321A (en) | 1984-10-16 | 1984-10-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6194321A (en) |
-
1984
- 1984-10-16 JP JP21664784A patent/JPS6194321A/en active Pending
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