JPH01137624A - Manufacture of gaas semiconductor device - Google Patents
Manufacture of gaas semiconductor deviceInfo
- Publication number
- JPH01137624A JPH01137624A JP29537287A JP29537287A JPH01137624A JP H01137624 A JPH01137624 A JP H01137624A JP 29537287 A JP29537287 A JP 29537287A JP 29537287 A JP29537287 A JP 29537287A JP H01137624 A JPH01137624 A JP H01137624A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- substrate
- ion implantation
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract 1
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野ン
この発明はＧａＡｓ半導体装置の製造方法に係シ、特に
イオン注入層のアニール方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method of manufacturing a GaAs semiconductor device, and more particularly to a method of annealing an ion-implanted layer.
（従来の技術）
プレーナ法を用いたＱａＡｓ Ｉ Ｃの高性能化、扁歩
留シ化には、イオン注入層の最適化されたアニール技術
の確立が必須である。(Prior Art) In order to improve the performance and reduce the yield of QaAs IC using the planar method, it is essential to establish an optimized annealing technique for the ion-implanted layer.
ところで、ＧａＡｓ結晶基板はＧａとＡｓの蒸気圧の違
いによシ高温でＡ８の解離が問題となる。そこで、上記
アニールを安定に行うために、基板表面を保護膜でキャ
ップする方法が用いられてきた。By the way, GaAs crystal substrates have a problem of dissociation of A8 at high temperatures due to the difference in vapor pressure between Ga and As. Therefore, in order to stably perform the above-mentioned annealing, a method has been used in which the surface of the substrate is capped with a protective film.
この保Ｆａ膜で基板表面をキャップしてアニールを行う
時、保護膜中へのＧａの拡散量の最適化が必要である。When capping the substrate surface with this anti-Fa film and performing annealing, it is necessary to optimize the amount of Ga diffused into the protective film.
そこで、例えば月刊セミコンダクターワールド１９８７
年６月号Ｐ９４〜１００に開示されるように、Ｇａの拡
散しやすい５ｔＣｈ膜と、逆に拡散しにくいＳｉＮ膜と
の中間の性質をもつ５ｉＯＮ膜を保ｉｌ！膜として用い
ることが提案きれている。For example, Monthly Semiconductor World 1987
As disclosed in pages 94 to 100 of the June issue, 5iON films with properties intermediate between 5tCh films, in which Ga easily diffuses, and SiN films, in which Ga is difficult to diffuse, can be maintained! It has been proposed to use it as a membrane.
（発明が解決しようとする問題点）
しかしながら’、３ｉＯＮ膜のＩＩｋ−賀制御は難しく
、したがって５ｉＯＮ膜を保護膜に用いてのアニールの
安定化は困難であった。また、保護膜の応力の最適化も
デバイスの藁性能化には必要であるが、５ｉＯＮ膜で、
Ｇａに対し最適な拡散係数と最適な応力の２つを同時に
実現するのは困難であった。(Problems to be Solved by the Invention) However, it is difficult to control the IIk-temperature of a 3iON film, and therefore it is difficult to stabilize annealing using a 5iON film as a protective film. In addition, optimization of the stress of the protective film is necessary to improve the performance of the device, but with the 5iON film,
It has been difficult to simultaneously achieve an optimal diffusion coefficient and an optimal stress for Ga.
この廠明は、ＧａＡＢ半導体装置のイオン注入層のアニ
ール工程において、保護膜中へのＧａの拡散量の最適化
、および保Ｈ１膜よシ基板に与える応力の最適化を図る
ことができ、かつＡｓの飛散を防止できるＧａＡｓ半導
体装置の製造方法を提供することを目的とする。This technology makes it possible to optimize the amount of Ga diffusion into the protective film and the stress applied to the H1 film and substrate in the annealing process of the ion-implanted layer of a GaAB semiconductor device. It is an object of the present invention to provide a method for manufacturing a GaAs semiconductor device that can prevent scattering of As.
（問題点を解決するための手段）
この発明では、下層の５ｔｏ２膜と、上層のＳｉＮ膜か
らなる２層膜を保護膜として、ＧａＡｓ半導体装置のイ
オン注入／１のアニールを実施する。(Means for Solving the Problems) In the present invention, ion implantation/1 annealing of a GaAs semiconductor device is performed using a two-layer film consisting of a lower 5to2 film and an upper SiN film as a protective film.
（作 用）
上記のような方法によれば、ＧａＡｓ基板表面に接する
下層の５ｉＯ１膜の膜厚によシ、保護膜に対するＧａの
拡散量をコントロールでき、最適化を図れる。また、上
層のＳｉＮ膜の膜厚によシ、保護膜よシ基板に与える応
力をコントロールでき、ｋ適ｆヒを図れる。σらに、Ｓ
ｉＮ膜によシ、基板よシのＡｓの飛散が防止される。(Function) According to the above method, the amount of Ga diffused into the protective film can be controlled and optimized depending on the thickness of the lower 5iO1 film in contact with the GaAs substrate surface. In addition, the thickness of the upper SiN film can be controlled, and the stress applied to the protective film and substrate can be controlled, and the optimum temperature can be achieved. σ et al., S.
This prevents As from scattering on the iN film and on the substrate.
（実施例） 以下この発明の一実施例を第１図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
まず第１図（ａｌに示すように、ＧａＡｓ基板１の表面
上にホトレソストパターン２２通常のホトリソ法で形成
し、そのホトシソストパターン２ｔ−マスクとしてＳｔ
のイオン注入を行うことによシ、前記ＧａＡｓ基板１中
に適訳的にｎ型またはｎ増のイオン注入層３ｔ−形成す
る。First, as shown in FIG.
By performing the ion implantation, an n-type or n-type ion implantation layer 3t is formed in the GaAs substrate 1.
次に、ホトレノスト・ンターン２を除去した後、基板ｌ
の全表面にアニール保護膜の下層部分として、Ｍｒ図（
ｂ）に示すようにＳｉ０ｇ膜４を形成する。Next, after removing the photorenost turn 2, the substrate l
The Mr diagram (
As shown in b), a Si0g film 4 is formed.
この５ｉＯｉ膜４は減圧ＣＶＤ法で形成され、膜厚は１
００〜１０００［Ａ）とする。なお、この５ｉＣｈ膜４
の形成法としては、減圧ＣＶＤ法以外に、常圧ＣＶＤ法
あるいはスパッタ法も適用可能である。This 5iOi film 4 is formed by low pressure CVD method, and the film thickness is 1
00 to 1000 [A]. Note that this 5iCh film 4
In addition to the low pressure CVD method, a normal pressure CVD method or a sputtering method can also be applied as a forming method.
次に、そのＳｉｇｈ膜４上に、アニール保護膜の上層部
分として第１図（ｃ）に示すようにＳｉＮ膜５を形成す
る。このＳｉＮ 膜５はプラズマＣＶＤ法にて５００〜
２０００ＣＡ］の膜厚に形成される。Next, a SiN film 5 is formed on the Sigh film 4 as an upper layer of the annealing protection film as shown in FIG. 1(c). This SiN film 5 has a film thickness of 500~ by plasma CVD method.
2000 CA].
そして、このようにしてＳｉＯ２膜４とＳｉＮ膜５から
なる２層構造のアニール保護膜を形成した状態で第１図
（ｄｌに示すようにイオン注入層３のアニールを行う。Then, with the two-layer annealing protective film formed of the SiO2 film 4 and the SiN film 5 formed in this manner, the ion implantation layer 3 is annealed as shown in FIG. 1 (dl).
このアニールは、イオン注入層３のＳｔ イオンを活性
化はぜるためのもので、電気炉を使用し、水素、アルゴ
ン、窒素雰囲気中にて７５０〜９００ ［’Ｃ：］の温
度で５分から３０分行われる。This annealing is to activate the St ions in the ion-implanted layer 3, and is performed for 5 to 30 minutes in an electric furnace at a temperature of 750 to 900 ['C:] in a hydrogen, argon, or nitrogen atmosphere. be exposed.
そして、このようなアニール工程を終了したら第１図（
ｅ）に示すように、アニール保護膜としてのＳｉＮ膜５
とＳｉ０ｇ膜４を７ツ酸あるいはドライエツチングで除
去し、その後イオン注入層３の上に図示しないが電＆を
配することによ、９ＦＥＴや抵抗といった素子を形成す
る。After completing this annealing process, the image shown in Figure 1 (
As shown in e), the SiN film 5 as an annealing protective film is
and the Si0g film 4 are removed by dichloromethane or dry etching, and then a conductor (not shown) is placed on the ion implantation layer 3 to form elements such as a 9FET and a resistor.
（発明の効果ン
以上説明したようにこの発明の製造方法によれば、Ｇａ
Ａｓ半導体装置のイオン注入層のアニール工程において
、５ｉ０２膜（下層）とＳｉＮ 膜（上層）の２層膜を
保護膜としたので、
■ 保護膜に対するＧａの拡散ｉｔを、下層のＳｉ０ｇ
膜の膜厚でコントロールすることができ、最適化を図る
ことができる
■ 上層のＳｉＮ 膜の膜厚によシ、保護膜よシ基板に
与える応力をコントロールでき、最適化を図ることがで
きる
ようになり、ざらに
■ ＳｉＮ 膜によシ、基板よシのＡｓの飛散を防止で
きる。(Effects of the invention) As explained above, according to the manufacturing method of the present invention, Ga
In the annealing process of the ion-implanted layer of the As semiconductor device, the two-layer film of 5i02 film (lower layer) and SiN film (upper layer) was used as the protective film.
The thickness of the upper SiN film can be controlled and the stress applied to the substrate can be controlled and optimized. This can prevent As from scattering on the SiN film and substrate.
そして、これらによシ優れた活性化率のイオン注入層を
安定に得ることが’５Ｊ能となシ、ＧａＡ ｓ半導体装
置の高集積化、高歩留フ化、高性能化が可能となる。It is essential to stably obtain an ion-implanted layer with an excellent activation rate using these methods, which will enable higher integration, higher yield, and higher performance of GaAs semiconductor devices. .
第１図はこの発明のＧａＡｓ＃ｉ体装置の製造方法の一
実施例を示す工程断面図である。
１・・・ＧａＡｓ基板、３・・・イオン注入層、４・・
・５ｔ（ｈ膜、５・・・ＳｉＮ膜。
特許出願人 沖電気工業株式会社FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a GaAs#i body device of the present invention. 1... GaAs substrate, 3... ion implantation layer, 4...
・5t (h film, 5...SiN film. Patent applicant Oki Electric Industry Co., Ltd.
Claims (1)
入層を形成する工程と、 （ｂ）そのＧａＡｓ基板の表面に保護膜の一部としてＳ
ｉＯ＿２膜を形成する工程と、 （ｃ）そのＳｉＯ＿２膜上に同じく保護膜の一部として
ＳｉＮ膜を形成する。 （ｄ）そのＳｉＮ膜と前記ＳｉＯ＿２膜を保護膜として
前記イオン注入層のアニールを行う工程とを具備してな
るＧａＡｓ半導体装置の製造方法。[Claims] (a) A step of ion-implanting impurities into a GaAs substrate to form an ion-implanted layer; (b) forming an ion-implanted layer on the surface of the GaAs substrate as part of a protective film;
Steps of forming an iO_2 film; and (c) forming an SiN film as part of the protective film on the SiO_2 film. (d) A method for manufacturing a GaAs semiconductor device, comprising the step of annealing the ion implantation layer using the SiN film and the SiO_2 film as a protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29537287A JPH01137624A (en) | 1987-11-25 | 1987-11-25 | Manufacture of gaas semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29537287A JPH01137624A (en) | 1987-11-25 | 1987-11-25 | Manufacture of gaas semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01137624A true JPH01137624A (en) | 1989-05-30 |
Family
ID=17819774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29537287A Pending JPH01137624A (en) | 1987-11-25 | 1987-11-25 | Manufacture of gaas semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01137624A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02111019A (en) * | 1988-10-20 | 1990-04-24 | Sanyo Electric Co Ltd | Heat treatment |
| JP2012212701A (en) * | 2011-03-30 | 2012-11-01 | Asahi Kasei Electronics Co Ltd | Semiconductor device manufacturing method |
-
1987
- 1987-11-25 JP JP29537287A patent/JPH01137624A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02111019A (en) * | 1988-10-20 | 1990-04-24 | Sanyo Electric Co Ltd | Heat treatment |
| JP2012212701A (en) * | 2011-03-30 | 2012-11-01 | Asahi Kasei Electronics Co Ltd | Semiconductor device manufacturing method |
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