JPH022298A - High speed time division selector switch circuit - Google Patents

Abstract

PURPOSE:To attain exchange of a broad band signal (150Mb/s) and to extend input highways without attending to the propagation delay by using a selector without using an ultrahigh speed memory. CONSTITUTION:A serial/parallel expansion means 1 fetches a multiplex data of the input highway synchronously with the clock and expands it into a parallel signal. The correction means 3 correcting drive timing of a switch selector means 4 based on the phase of the extended input data consists of a phase control circuit 31 and a selector control circuit 32. The phase control circuit 31 controls the absorption of the parallel expansion processing time of the phase absorbing means 2 based on the clock and reference the extended clock to output a control signal controlling the drive timing of the switch selector means 4 to match the phase with that of the extended input data. The selector control circuit 32 based on the control signal generates a signal controlling a switch selector means 4 and a selector means 5. The selector means 5 selects any of the extended input data from the data outputted from the selector means 4 and outputs it.

Description

[Detailed Description of the Invention] [Summary 1] This invention relates to a high-speed time-division selector switch circuit using a time-division selector method that makes it possible to easily increase the number of input highways in a switch for exchanging wideband signals in a digital exchange. The purpose is to be able to expand the number of switches up to a certain size without any problems by using the existing switch, and we have developed a serial/parallel expansion means that parallelizes the serial data from the input highway, and an output of the serial/parallel expansion means. A phase absorbing means for changing the phase of data, a selector switch means for selectively selecting and outputting the output of the phase absorbing means, and a timing for driving the selector switch means based on the phase of the additional input data. Data output from the correction means to be corrected and the selector switch means. and additional input data, and a plurality of such selector switch circuits are connected to make it possible to increase the switch size.

[Field of application in FC industry 1 The present invention is applicable to wideband signals in digital switching equipment.
The present invention relates to a high-speed time-division selector switch circuit using a time-division selector method that allows the number of input highways to be easily increased in a %m switch.

[Prior art 1] Recently, digital exchanges have been using broadband (No. 8 (150 Mb)
/s) exchange wide? i) Acid exchangers have become essential. When this wideband signal is time-division exchanged using Memo 1, even if ultra-high-speed memory is used, there is no addition of 4 (sufficient access time), and the switch size is several 4 channels. It ended up being a small-scale configuration called the X number channel. Therefore, in order to increase the switch size, a configuration in which this small-sized switch is modularized and expanded is considered.

An example of a switch circuit having an 11-stage configuration is shown in FIG. 5 using the same module, and FIG. 10 shows a case where the incoming highway and the outgoing highway each have four trees. Each switch module (SW1 to SW4) has r】
A channel multiplexed signal is input. The output of each switch module is entered into the elastic memory [S,
Here, the phase is adjusted to adjust the phase variation between the highways), and the output thereof is appropriately selected and outputted by the selector SEL.

[Problems to be Solved by the Invention] However, in this case, not only a module for concentrating each module is required, but also adjustment of the propagation delay of each module is required. The partitioning method has difficult problems to implement.

The first object of the present invention was made in view of this problem, and by using a switch that uses a high-speed selector with the same switch size, the above problem is not noticed until the switch size reaches a certain level. An object of the present invention is to provide a high-speed time-division selector switch circuit that can be expanded.

Means for Solving Problem 1 FIG. 1 is a diagram showing the principle configuration of a high-speed time division selector switch circuit according to the present invention. In the figure, reference numeral 1 denotes a serial/parallel expansion means for converting serial data from an input highway into parallel l1m, 2 a phase absorption means for varying the phase of the output data of the serial/parallel expansion means, and 4 an output of the phase absorption means 2. A switch selector means for selectively selecting and outputting; 3 a correction means for correcting the driving timing of the switch selector means 3 based on the phase of additional input data; 5 a data output from the switch selector means 4 or This is selector means for selecting and outputting either one of the additional input data.

[Function] In such a configuration, the propagation delay of the data (extension input data) exchanged by the previous switch is reduced by using the exchange time from parallel expansion by the serial/parallel expansion means 1 to selection by the switch selector means 4. Based on this, the input time to the selector means 5 is adjusted to match the input time of the additional input data.

Since the additional input data is also data exchanged using the same configuration as the selector switch circuit, there is a time delay. The delay regarding this additional input data includes a logical (switching process) delay and a transmission delay (transmission from the switch output section of the preceding circuit to the switch input section of the circuit).

However, in the selector switch circuit, the logic part of these delays can be corrected at the switching stage where the output of the switch selector means 4 is controlled by the switching speed.
Here, it is sufficient to correct only the delay due to transmission. In this circuit, by skillfully utilizing the conversion time of the parallel expansion and correcting the delay due to the transmission by the correction means 3, it is possible to successfully match the phase with the augmented 5Q input data in the selector means 5 manual section.

Therefore, as long as the total transmission time does not exceed the parallel development time, the selector switch circuits of the present invention can be connected in series and added.

If the parallel expansion σ exceeds one hour, it is possible to increase the number by delaying the input highway from the selector switch circuit by the time of the parallel expansion exchange JT.

[Example] Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram of main parts showing an embodiment of the present invention. In the figure, the same parts as in FIG. 1 are indicated by the same reference numerals. The serial/parallel expansion means 1 takes in the multiplexed data on the input highway in synchronization with a clock and performs parallel expansion.

The correction means 3 which corrects the driving timing of the switch selector means 4 based on the phase of the additional input data is composed of a phase control circuit 31 and a selector control circuit 32. Controls the absorption of parallel expansion processing time in the phase absorption means 2, and outputs a control signal that refers to the expansion clock and controls the timing of driving the switch selector means 4 so that the phase matches the expansion input data. . Selector control circuit 32
generates a signal for controlling the switch selector means 4 and the selector means 5 based on this control signal.

FIG. 3 is a configuration diagram when a plurality (m) of selector switch circuits having the same configuration as this J: Una configuration are connected in series. In each circuit, the exchange data (parallel data) of the previous stage is inserted into the collector 5, and the selector means outputs either the data of the circuit concerned or the inserted data. The output is parallel data.

The operation in this configuration will be explained next.

The m-th selector switch circuit is the main one, and the (
The m-1)th to first selector switch circuits are added. The m-th selector switch circuit will be explained.

Input highway data taken in in synchronization with a clock is expanded in parallel by a serial/parallel expansion means 1. The expanded parallel data is input to the phase absorbing means 2, where the phase is absorbed.

The switch selector means 4 selectively selects and outputs the output of the phase absorption means 2 based on the 1Ilstill signal from the selector control circuit 32.

Note that the phase control circuit 31 adjusts the driving timing of the switch selector means 4 so that the output of the switch selector means 4 and the output transmitted from the previous stage circuit are in phase with each other by referring to the expansion clock.

The output of the selector switch circuit of the present invention is used as an input of a 1 selector (a selector that selects and outputs one out of K inputs) 41 as shown in FIG.

The selector 41 receives a control signal (
(given by the exchange rate Nb/s), and outputs an exchange signal of Nb/s.

The logical delay is corrected by this selector 41.

It is possible to increase the number of switches gQ in the manner described above. However, it is not possible to increase the number of stages without limit, and there is a limit to the number of stages that can be expanded. If the phase absorption time is taken and the transmission delay time between the selector switch circuits is d, then the number of stages that can be expanded is up to D/d.

[Effect of the Invention 1] As explained above, according to the present invention, wideband signals (150 Mb/s) can be exchanged by using a selector without using an ultra-high-speed memory.

At the same time, input highways can be added without being concerned about propagation delays, and therefore there is no need to add a bar dow f7.

Further, although conventional memory systems require a serial-to-parallel conversion LSI, the circuit of the present invention has this function built-in, so such an LSI is no longer necessary.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the present invention; Fig. 2 is a diagram showing the configuration of an embodiment of the invention; Fig. 3 is a diagram showing an expanded state of a brush rectifier switch circuit; Fig. 4 is a diagram showing a mode of use of the present invention. , FIG. 5 is a diagram showing an 11-stage switch configuration using memory modules. In Figures 1 and 2, 1...Serial/parallel exhibition 17'J means, 2...
Phase absorption means; 3. Correction means; 4. Switch selector means; 5. Selector means; 31. Phase control circuit; 32. Select tie control circuit.

Claims (1)

[Claims] A switch for exchanging wideband signals in a digital exchange, comprising serial/parallel expansion means (1) for parallel expansion of serial data from an input highway;
A phase absorbing means (2) for varying the phase of the output data of the parallel expansion means (1), and a selector switch means (4) for selectively selecting and outputting the output of the phase absorbing means (2).
), and a correction means (3) for correcting the drive timing of the switch selector means (4) based on the phase of the additional input data.
), and selector means (5) for selecting and outputting either the data output from the switch selector means (4) or the additional input data. .