JP2536401B2 - Switching without interruption - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-instantaneous switching system for switching transmission signals passing through a transmission line between devices connected by a plurality of digital transmission lines without interruption.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a transmission path route between two devices. The device A100 and the device B101 are the transmission path A200.
And transmission line B201. In this case, since the transmission path A200 has a longer distance than the transmission path B201, even if data is transmitted from the device A100 to the transmission path A200 and the transmission path B201 at the same time, the data on the transmission path B201 is transmitted earlier to the device B101. When the data arrives, the data on the transmission path A200 is delayed in proportion to the transmission distance difference.

FIG. 3 is a diagram showing a conventional hitless switching system. The signals on the transmission path A200 and the transmission path B201 are input to the multi-frame delay buffer A500 and the multi-frame delay buffer B501, respectively, after multi-frame synchronization is established and delayed, and also from the multi-frame delay buffers A500 and B501. Delay data A 505, delay data B in the detection circuit 503
506 is passed, and the write signal A 508 and the write signal B 5 are set so as to match the multi-frame phase with a large delay.
Adjust 09. Multi-frame delay buffer A500
Since the data output from the multi-frame delay buffer B501 and the multi-frame phase match each other, when one of the input signals is selected by the selection signal 305 input to the transmission path selection circuit 303, the selected output 202 has the same phase. It becomes data, and switching can be executed without instantaneous interruption. The selection signal 305 is output in multi-frame units. This non-interruption switching method combines multiframes in which the delay time of the transmission path is predicted in advance, and notifies the opposite station of a signal for identifying the start position of the multiframe by using the surplus bits in the transmission path,
Switching without interruption is performed by adjusting the multi-frame phase. Such a non-instantaneous interruption switching system is disclosed in Japanese Patent Laid-Open No. 64-506.
No. 27 publication.

[0004]

As described above, in the conventional hitless switching system, a multiframe in which the delay time of the transmission line is predicted is assembled and a signal for identifying the start position of the multiframe is transmitted in the transmission line. Notifying the opposite station using the surplus bit and performing non-instantaneous switching by adjusting the multiframe phase, the multiframe length cannot be determined unless the transmission path length is estimated in advance, and more than the specified multiframe When the delay occurs, there is a drawback that it is not possible to switch without interruption.

[0005]

According to the present invention, a transmission signal having a multi-frame structure is transmitted to a plurality of digital transmission lines, and a receiving side device of a device opposed to each other through the plurality of digital transmission lines. , provided luma Le <br/> Chi frame delay buffer to absorb the delay difference of the transmission signal due to the difference of the plurality of digital transmission path of a path corresponding to each of the plurality of digital transmission path, the receiving device Then, when performing transmission signal switching , both of the multi-frame delay buffers are
In a method of switching from one of the output signals to the other without interruption, a predetermined number of at least one bit of each multi-frame is repeated by a plurality of multi-frames from a transmission side device to the plurality of digital transmission lines. The bit pattern sequence of
It is sent at the same timing, and the plurality of the
The above-mentioned circle provided corresponding to each of the digital transmission lines.
As a multi-frame delay buffer.
Multi-frame delay that can store transmission signals equivalent to
Using the buffer, by using the bit pattern sequence extracted from each transmission signal by the receiving device, wherein the delay difference of the transmission path constant because, in a multi-frame timing delay is greater side of said plurality of digital transmission path A non-instantaneous interruption switching method is provided which is characterized in that both write controls of the multi-frame delay buffer are controlled and one of both output signals of the multi-frame delay buffer is switched to the other without interruption.

Further, according to the present invention, a transmission signal having a multi-frame structure is transmitted to a plurality of digital transmission lines, and the receiving side device of the device facing each other through the plurality of digital transmission lines is provided with the plurality of digital signals. the difference luma Ruchi frame delay buffer to absorb the delay difference of the transmission signal according to the path of the transmission line provided corresponding to each of the plurality of digital transmission path, it said at the receiving side apparatus, when the transmission signal switching execution
One of both output signals of the multi-frame delay buffer
In the method of switching without interruption to the other from the side, the transmission side instrumentation
Said plurality of digital transmission path from the location, the predetermined bit pattern sequences are repeated a plurality multiframe predetermined bits of at least one bit of each multiframe, and sent at the same timing, the plurality of digital Den to the receiving device
The multi-frame delay provided corresponding to each of the transmission paths
It corresponds to the above-mentioned multiple multi-frames as an extended buffer.
Uses a multi-frame delay buffer that can store transmission signals
There, by using the bit pattern sequence extracted from each transmission signal by the receiving device, the multi-frame the delay difference of the transmission path constant because, in a multi-frame timing delay is greater side of said plurality of digital transmission path There is provided an uninterruptible switching method characterized by performing both readout control of the delay buffers and switching from one of the output signals of both the multi-frame delay buffers to the other without interruption.

[0007]

According to the present invention, the repetition interval of the bi Ttopatan is set sufficiently longer than the multi-frame timing can also be detected delay difference or multiframe timing.

[0008]

1 is a diagram showing a non-instantaneous interruption switching system according to an embodiment of the present invention.

The signals on the transmission path A200 and the transmission path B201 are respectively input to a multi-frame delay buffer A300 and a multi-frame delay buffer B301 each having a buffer size equal to or larger than multi-frame, multi-frame synchronization is established and delayed, and multi-frame synchronization is performed. The delay buffers A300 and B301 are specific bits 306 and 30 that are defined by the transmission path A delay detection circuit 400 and the transmission path B delay detection circuit 401 as only one bit in a multiframe in the transmission path.
Pass 7. This specific bit is a bit pattern that repeats in several multiframes, and the transmission side A200
And the same bit pattern is inserted into the transmission path B201 at the same timing. Transmission line A delay detection circuit 400 and transmission line B
The delay detection circuit 401 detects the specific bit transmitted by one bit in the multiframe, and the multiframe delay data A402 and the multiframe delay data B403 are passed to the phase control circuit 304, and the phase control circuit 30
4 adjusts the multi-frame write signal A308 and the multi-frame write signal B309 so as to match the multi-frame phase with the large delay amount. This adjustment method
There are various ways to realize
From transmission line B201 to multi-frame delay buffer A30
0 and written to the multi-frame delay buffer 301
Transmit the data write address and write timing.
The delay difference between the transmission path A200 and the transmission path B201 is absorbed.
You just need to adjust it. Transmission line A200 and transmission line B20
The data written from 1 to the multi-frame delay buffer A300 and the multi-frame delay buffer 301 is adjusted by the multi-frame write signals 308 and 309 even if the delay difference between the transmission path A200 and the transmission path B201 is more than the multi-frame. Therefore, the multi-frame delay buffer A300 and the multi-frame delay buffer B301
The multi-frame phase of the data output from is matched, and when one of the input signals is selected by the selection signal 305 input to the transmission path selection circuit 303, the selected output 202 becomes the data of the same phase, and switching is performed without interruption. it can.

The selection signal 305 is output in multi-frame units.

Further, according to the above configuration, the delay difference of the transmission path is absorbed by matching the read signal phases of the multi-frame delay buffer A300 and the multi-frame delay buffer B301, and similarly, the non-instantaneous interruption switching is executed. good.

[0012]

As described above, according to the present invention, a predetermined bit pattern sequence that repeats in a plurality of multi-frames is sent from a transmitting side to at least one predetermined bit of each multi-frame at the same timing. Even if the delay difference of the transmission paths is larger than that of the multi-frame, the non-instantaneous interruption switching can be executed.

[Brief description of drawings]

FIG. 1 is a diagram showing a hitless switching system according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a transmission path route between two devices.

FIG. 3 is a diagram showing a conventional hitless switching method.

[Explanation of symbols]

 100 device A 101 device B 200 transmission line A 201 transmission line B 202 selection output 300 multi-frame delay buffer A 301 multi-frame delay buffer B 303 transmission line selection circuit 304 phase control circuit 305 selection signal 308 multi-frame write signal A 309 multi-frame Write signal B 400 Transmission line A delay detection circuit 401 Transmission line B delay detection circuit 500 Multi-frame delay buffer A 501 Multi-frame delay buffer B 503 Multi-frame delay detection circuit 506 Delay data A 508 Write signal A 509 Write signal B

Claims (2)

(57) [Claims] 1. A multi-frame structure transmission signal is sent to a plurality of digital transmission lines, and a receiving side device of a device facing each other through the plurality of digital transmission lines is provided with a path of the plurality of digital transmission lines. luma Ruchi frame delay buffer to absorb the delay difference of the transmission signal due to a difference provided corresponding to each of the plurality of digital transmission path, the received
In the side device, when the transmission signal switching is executed, the multi-frame
In the method of switching from one output signal of both delay buffers to the other without interruption, a predetermined number of at least one bit of each multi-frame is repeated in a plurality of multi-frames from a transmission side device to the plurality of digital transmission lines. of the bit pattern sequence, sent at the same timing, the receiving
Correspond to each of the plurality of digital transmission lines
As the multi-frame delay buffer provided as
Can store the transmission signals corresponding to the multiple multi-frames
That using a multi-frame delay buffer, by using the bit pattern sequence extracted from each transmission signal at the receiving side apparatus <br/>, the transmission path constant because the delay difference, a delay of the plurality of digital transmission path Write control of both of the multi-frame delay buffers is performed at a larger multi-frame timing, and one of the output signals of both of the multi-frame delay buffers is switched to the other without interruption. Instantaneous interruption switching method . 2. A multi-frame structure transmission signal is sent to a plurality of digital transmission lines, and a receiving side device of a device facing each other through the plurality of digital transmission lines is provided with a path of the plurality of digital transmission lines. luma Ruchi frame delay buffer to absorb the delay difference of the transmission signal due to a difference provided corresponding to each of the plurality of digital transmission path, the received
In the side device, when the transmission signal switching is executed, the multi-frame
In the method of switching from one output signal of both delay buffers to the other without interruption, a predetermined number of at least one bit of each multi-frame is repeated in a plurality of multi-frames from a transmission side device to the plurality of digital transmission lines. of the bit pattern sequence, sent at the same timing, the receiving
Correspond to each of the plurality of digital transmission lines
As the multi-frame delay buffer provided as
Can store the transmission signals corresponding to the multiple multi-frames
That using a multi-frame delay buffer, by using the bit pattern sequence extracted from each transmission signal at the receiving side apparatus <br/>, the transmission path constant because the delay difference, a delay of the plurality of digital transmission path perform larger side said both read control multi-frame delay buffers in a multi-frame timing, hitless switching method characterized by switching without interruption from one to the other of both the output signal of the multi-frame delay buffer .