JPH02229442A - Mounting structure of semiconductor device - Google Patents
Mounting structure of semiconductor deviceInfo
- Publication number
- JPH02229442A JPH02229442A JP1050793A JP5079389A JPH02229442A JP H02229442 A JPH02229442 A JP H02229442A JP 1050793 A JP1050793 A JP 1050793A JP 5079389 A JP5079389 A JP 5079389A JP H02229442 A JPH02229442 A JP H02229442A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- insulating film
- film
- semiconductor device
- connection lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 10
- 229920005989 resin Polymers 0.000 abstract description 10
- 239000011347 resin Substances 0.000 abstract description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 150000002739 metals Chemical class 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910017052 cobalt Inorganic materials 0.000 abstract description 2
- 239000010941 cobalt Substances 0.000 abstract description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 239000004332 silver Substances 0.000 abstract description 2
- 239000004840 adhesive resin Substances 0.000 description 4
- 229920006223 adhesive resin Polymers 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229920000122 acrylonitrile butadiene styrene Polymers 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920005668 polycarbonate resin Polymers 0.000 description 1
- 239000004431 polycarbonate resin Substances 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920013716 polyethylene resin Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920005990 polystyrene resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
く産業上の利用分野〉
本発明は半導体装置の実装構造に関し、詳しくはフィル
ムキャリアと外部基板との接続を容易に、且つ信顛性良
く最小面積で実装する構造に関するものである.
く従来の技術〉
従来から、パッケージ基板やケースなどの外部基板にフ
ィルムキャリアを用いた半導体装置を接続(アウターリ
ードボンディング)するには、半導体装置のフィルムキ
ャリア上に銅などの導電性金属を線状に形成した接続リ
ードが利用されている.例えば、第5図に示すように、
フィルムキャリア3上に形成した接続リード4と半導体
素子1を、バンプ2を介して接続した半導体装置の外部
基板5への実装は、外部基板5の表面に形成した金属配
線(ランド部)6とフィルムキャリア3上の接続リード
4が利用されている.
しかし、このような実装方法では接続リード4に切断や
折り曲げ加工を施こす必要があり、作業性が悪く、接続
も容易に行なえないものである.さらに、接続リード4
はフィルムキャリア゛から突出した構造であるので機械
的強度に乏しく、作業性に難点を有するものである。ま
た、接続リード4とランド部6との接続には、通常、半
田リフロ一法などの熱的接合方式が採られており、例え
ば液晶パネルの如き金属酸化物透明電極上への実装には
、予め上記透明電極上を半田付け可能なようにメタライ
ズしておく必要がある。[Detailed description of the invention] Industrial application field> The present invention relates to a mounting structure for a semiconductor device, and more particularly to a structure for mounting a film carrier and an external board easily and reliably in a minimum area. It is something. Conventional technology> Conventionally, in order to connect a semiconductor device using a film carrier to an external substrate such as a package board or case (outer lead bonding), a conductive metal such as copper is wired onto the film carrier of the semiconductor device. A connection lead formed into a shape is used. For example, as shown in Figure 5,
The semiconductor device, in which the connection leads 4 formed on the film carrier 3 and the semiconductor element 1 are connected via the bumps 2, is mounted on the external substrate 5 by connecting the metal wiring (land portion) 6 formed on the surface of the external substrate 5. The connection lead 4 on the film carrier 3 is used. However, such a mounting method requires cutting and bending the connection leads 4, resulting in poor workability and difficulty in connection. Furthermore, connection lead 4
Since it has a structure that protrudes from the film carrier, it has poor mechanical strength and is difficult to work with. Further, a thermal bonding method such as a solder reflow method is usually used to connect the connection lead 4 and the land portion 6. For example, when mounting on a metal oxide transparent electrode such as a liquid crystal panel, It is necessary to metalize the transparent electrode in advance so that it can be soldered.
近年、異方導電性の膜や塗料を用いてフィルムキャリア
と外部基板とを接合する方法も提案されているが、何れ
の方法も接続部の位置合わせを高精度に行なう必要があ
り、また経済的にもコスト高となるものである.
く発明が解決しようとする課題〉
本発明は上記従来の技術が有する欠点を解決するために
なされたものであって、半導体装置を外部基板に実装(
アウターリードボンディング)するにあたり、接続リー
ドと外部基板との接合を高精度な位置決めを行なわすと
も容易に行なえ、かつ電気的接続信頼性が向上する実装
構造を提供することを目的とするものである.
く諜題を解決するための手段〉
本発明者らは鋭意検討を重ねた結果、表裏面に導通する
貫通孔を設けた絶縁性フィルムをフィルムキャリアに用
い、該貫通孔内に金属物質を充填し、さらにバンプ状突
出物を形成す名ことによって、該貫通孔に接する接続リ
ードと外部基板上のランド部とが粗位置決めだけで信顧
性良く、容易に接続できることを見い出し、本発明を完
成するに至った.
即ち、本発明の半導体装置の実装構造は、片面に接続リ
ードを形成した絶縁性フィルムよりなるフィルムキャリ
アに半導体素子を接合した半導体装置と外部基板との実
装構造において、外部基板上のランド部と接する前記絶
縁性フィルムのボンディング領域内または該領域内とそ
の近傍領域に、少なくとも1個の微細貫通孔が厚み方向
に設けられ、かつボンディング領域内に設けられた貫通
孔内が金属物質にて充填されていると共にバンプ状突出
物が形成され、このバンプ状突出物を介して前記接続リ
ードが外部基板上のランド部と接続されてなる構造を有
するものである.
〈実施例〉
以下に、本発明の実施例を図面を用いて説明する.
第1図は本発明の半導体装置の実装構造を示す断面図で
あり、片面に接続リード4が形成されている絶縁性フィ
ルムからなるフィルムキャリア3には、半導体素子lが
実装されており、金属物質を貫通孔内に充填しバンプ状
突出物(図示省略、バンプ状突出物は絶縁性フィルム3
の下面に位置する)を設けた絶縁性フィルム3が、外部
基板5上の金属配線(ランド部)6とバンプ状突出物を
介して接続されている。In recent years, methods have been proposed for bonding the film carrier and external substrate using anisotropically conductive films or paints, but both methods require highly accurate positioning of the connection parts and are not economical. This also results in high costs. Problems to be Solved by the Invention The present invention has been made in order to solve the drawbacks of the above-mentioned conventional techniques.
The purpose of this invention is to provide a mounting structure in which the connection lead and the external board can be easily bonded with high precision positioning when performing outer lead bonding (outer lead bonding), and which improves electrical connection reliability. .. Means for Solving the Problem> As a result of extensive studies, the present inventors used an insulating film with conductive through holes on the front and back sides as a film carrier, and filled the through holes with a metal substance. Furthermore, they discovered that by forming a bump-like protrusion, the connection lead in contact with the through-hole and the land portion on the external board could be easily connected with good reliability just by rough positioning, and the present invention was completed. I ended up doing it. That is, in the mounting structure of a semiconductor device of the present invention, in a mounting structure of an external substrate and a semiconductor device in which a semiconductor element is bonded to a film carrier made of an insulating film with connection leads formed on one side, the land portion on the external substrate and At least one fine through hole is provided in the thickness direction in the bonding region of the contacting insulating film or in the region and its vicinity, and the through hole provided in the bonding region is filled with a metal substance. In addition, a bump-like protrusion is formed, and the connection lead is connected to a land portion on the external substrate via the bump-like protrusion. <Examples> Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the mounting structure of a semiconductor device according to the present invention. A semiconductor element l is mounted on a film carrier 3 made of an insulating film with connection leads 4 formed on one side, and a metal A material is filled into the through hole to form a bump-like protrusion (not shown; the bump-like protrusion is formed by filling the insulating film 3
An insulating film 3 provided with a metal wiring (located on the lower surface of the substrate) is connected to a metal wiring (land portion) 6 on an external substrate 5 via a bump-shaped protrusion.
第2図(a)および(b)は貫通孔7内に金属物質2゜
を充填し、バンプ状突出物を形成した絶縁性フィルム3
の部分断面図を示し、第2図(a)は金属物質2゛を充
填した各貫通孔7にそれぞれバンプ状突出物を設けた状
態を示し、第2図Φ)は複数の貫通孔7にわたって共通
のバンプ状突出物を設けた状態を示す.
第3図は外部基板5上の金属配線(ランド部)6に、第
2図(a)の状態のバンプ状突出物を介して半導体装置
を実装した構造を示す断面図である。FIGS. 2(a) and 2(b) show an insulating film 3 in which the through hole 7 is filled with a metal substance 2° to form a bump-like protrusion.
FIG. 2(a) shows a state in which a bump-like protrusion is provided in each through-hole 7 filled with a metal substance 2, and FIG. This shows the state in which a common bump-like protrusion is provided. FIG. 3 is a cross-sectional view showing a structure in which a semiconductor device is mounted on the metal wiring (land portion) 6 on the external substrate 5 via a bump-like protrusion in the state shown in FIG. 2(a).
第4図はフィルムキャリアを構成する絶縁性フィルム3
のバンプ状突出物形成面に、熱接着性樹脂層8を設けた
状態を示す断面図である。Figure 4 shows the insulating film 3 constituting the film carrier.
FIG. 3 is a cross-sectional view showing a state in which a heat-adhesive resin layer 8 is provided on the surface on which bump-like protrusions are formed.
零発.明において絶縁性フィルム3は、電気絶縁特性を
有するフィルム゛であればその素材に制限はなく、ポリ
エステル系樹脂、エボキシ系樹脂、ウレタン系樹脂、ボ
リスチレン系樹脂、ポリエチレン系樹脂、ボリアミド系
樹脂、ポリイミド系樹脂、ABS樹脂、ポリカーボネー
ト樹脂、シリコーン系樹脂などの熱硬化性樹脂や熱可塑
性樹脂を問わず使用できる。これらのうち、耐熱性や機
械的強度の点からポリイミド系樹脂を用いることが好ま
しい.
上記絶縁性フィルム3の片面に形成される接続リード4
は、例えば金、銀、銅、ニッケル、コバルトなどの各種
金属、またはこれらを主成分とする各種合金などの導電
性材料によって形成され、外部基板上の金属配線と電気
的に接続され、半導体装置に搭載されている半導体素子
の所定の機能を発揮せしめるように、所望の線状パター
ンにて配線されている。Starting from zero. In this specification, the material of the insulating film 3 is not limited as long as it has electrical insulation properties, and examples include polyester resin, epoxy resin, urethane resin, polystyrene resin, polyethylene resin, polyamide resin, and polyimide. Any thermosetting resin or thermoplastic resin can be used, such as ABS resin, polycarbonate resin, or silicone resin. Among these, polyimide resins are preferably used in terms of heat resistance and mechanical strength. Connection lead 4 formed on one side of the insulating film 3
is formed of conductive materials such as various metals such as gold, silver, copper, nickel, and cobalt, or various alloys containing these as main components, and is electrically connected to metal wiring on an external substrate, and is used to connect semiconductor devices. The wires are wired in a desired linear pattern so that the semiconductor elements mounted on the board can perform their predetermined functions.
フィルムキャリアの上記絶縁フィルム3に設ける貫通孔
7は、接続リード4と外部基板5上の金属配線(ランド
部)6との接続を果たすために重要であり、基板上のラ
ンド部6と接する絶縁性フィルム3のボンディング領域
内または該領域内とその近傍領域に、接続リードの幅よ
りも小さな孔間ピッチにて、少なくとも1個の微細貫通
孔7が厚み方向に設けられている。この貫通孔7は機械
加工やレーザー加工、光加工、化学エッチングなどの方
法を用いて、任意の孔径および孔間ピツチで設けること
ができ、例えばエキシマレーザーの照射にて穿孔加工を
行なうことが好ましい。また、貫通孔7の孔径は、隣合
う貫通孔同士が繋がらない程度にまで大きくし、さらに
孔間ピツチもできるだけ小さくしてリードに接する貫通
孔の数を増やすことが、後の工程にて充填する金属物質
の電気抵抗を小さくする上で好ましい。The through hole 7 provided in the insulating film 3 of the film carrier is important for connecting the connection lead 4 with the metal wiring (land part) 6 on the external board 5, and is important for achieving the connection between the connection lead 4 and the metal wiring (land part) 6 on the external board 5. At least one fine through-hole 7 is provided in the thickness direction in the bonding region of the flexible film 3 or in the bonding region and in the vicinity thereof, with a pitch between the holes smaller than the width of the connection lead. The through holes 7 can be formed with any hole diameter and hole pitch using methods such as machining, laser processing, optical processing, and chemical etching. For example, it is preferable to perform the drilling process by irradiating an excimer laser. . In addition, it is recommended that the diameter of the through-holes 7 be made large enough that adjacent through-holes do not connect with each other, and the pitch between the holes be made as small as possible to increase the number of through-holes in contact with the leads in the subsequent filling process. This is preferable in order to reduce the electrical resistance of the metallic substance.
上記のようにして設けられた貫通孔7のうち、ボンディ
ング領域内に設けられた貫通孔には、半田などの金属物
質2”が充填されており、絶縁フィルム3の表裏面を導
通させている。さらに、金属物質2゜が充填されている
貫通孔の接続リード4当接面と反対面には第2〜4図に
示すバンプ状突出物が数μm〜十数μmの高さにて形成
されている.
貫通孔7への金属物質2゜の充填およびバンプ状金属突
出物の形成は、例えば接続リード4を電極として電解メ
ッキすることによって、ボンディング領域内の貫通孔の
みに選択的に行なえるものである.
本発明では上記バンプ状突出物を介してフィルムキャリ
ア上の接続リード4が、外部基板5上のランド部6と熱
接着などの通常の電気的接続手段にて接続されて半導体
装置が実装され、電気的導通を得ることができるもので
ある。Among the through-holes 7 provided as described above, the through-holes provided in the bonding area are filled with a metal substance 2'' such as solder, making the front and back surfaces of the insulating film 3 electrically conductive. .Furthermore, on the surface of the through hole opposite to the contact surface of the connection lead 4 filled with the metal substance 2°, a bump-like protrusion shown in FIGS. 2 to 4 is formed at a height of several μm to more than ten μm. Filling the through hole 7 with the metal substance 2° and forming the bump-like metal protrusion can be selectively performed only in the through hole in the bonding region, for example, by electroplating using the connection lead 4 as an electrode. In the present invention, the connection leads 4 on the film carrier are connected to the land portions 6 on the external substrate 5 through the bump-like protrusions by ordinary electrical connection means such as thermal bonding, thereby forming a semiconductor. A device can be mounted and electrical continuity can be obtained.
また、第4図のように、熱接着性樹脂層8をバンプ状突
出物形成面に設ける場合は、通常5〜50μm、好まし
くは10〜30μmの厚みで設けられ、該樹脂としてエ
ポキシ樹脂の如き熱硬化性樹脂やフッ素樹脂の如き熱可
塑性樹脂を問わず使用できる。また、該樹脂層はバンプ
状突出物形成面に塗布して設けてもよいし、フィルム状
やリボン状にしたものをボンディング時に挟着して熱圧
着してもよい。In addition, as shown in FIG. 4, when the heat-adhesive resin layer 8 is provided on the bump-like protrusion formation surface, it is usually provided with a thickness of 5 to 50 μm, preferably 10 to 30 μm, and the resin is made of epoxy resin or the like. Any thermoplastic resin such as a thermosetting resin or a fluororesin can be used. Further, the resin layer may be provided by coating on the surface on which the bump-like protrusions are formed, or a film or ribbon may be sandwiched and thermocompressed during bonding.
このように熱接着性樹脂層8を介在させて外部基板5に
半導体装置を実装した場合、金属物質が充填されていな
い貫通孔にも樹脂が流入するので、半導体装置と外部基
板との密着性が向上し、電気的接続も強固となる。さら
に、表面保護も該樹脂層によって行なえるので、製造工
程も簡素化できるものである。なお、接続後、余分な樹
脂は金属物質が充填されていない貫通孔内に流入して内
部の空気を押し出すので、後の工程で樹脂封止する際に
ボイドの発生や、クラックが入ることもなく信頼性の高
いものとなる。When a semiconductor device is mounted on the external substrate 5 with the thermal adhesive resin layer 8 interposed in this way, the resin flows into the through-holes that are not filled with metal material, which improves the adhesion between the semiconductor device and the external substrate. This improves the electrical connection and makes the electrical connection stronger. Furthermore, since the resin layer can also protect the surface, the manufacturing process can also be simplified. Furthermore, after connection, excess resin flows into the through-hole that is not filled with metal material and pushes out the air inside, which may cause voids or cracks when sealing with resin in the later process. This makes it highly reliable.
なお、本発明の実装構造では外部基板と半導体とのアウ
ターリードボンディング部に特定の貫通孔を設けた絶縁
フィルムを用いているが、半導体素子とフィルムキャリ
ア部とのインナーリードボンディング部にも上記接続方
法を併用(第1図参照)しても良いことはいうまでもな
い。In addition, in the mounting structure of the present invention, an insulating film with specific through holes is used in the outer lead bonding part between the external board and the semiconductor, but the above-mentioned connection is also used in the inner lead bonding part between the semiconductor element and the film carrier part. It goes without saying that the methods may be used in combination (see Figure 1).
く発明の効果〉
以上のように、本発明の半導体装置の実装構造では、フ
ィルムキャリアと外部基板との接続に、ボンディング領
域内または該領域内とその近傍領域の絶縁性フィルムに
貫通孔を設け、その内部に金属物質を充填し、さらにバ
ンプ状突出物を形成しているので、貫通孔の形成時は接
続リード形成部に粗位置合わせをするだけで良く、また
、外部基板との接続もバンプ状の突出物によって、高精
度に位置決めできるものであり、信頼性の高い電気的接
続が得られるものである。Effects of the Invention> As described above, in the semiconductor device mounting structure of the present invention, a through hole is provided in the insulating film in the bonding region or in the bonding region and in the vicinity thereof for connection between the film carrier and the external substrate. , since the inside is filled with a metal substance and a bump-like protrusion is formed, when forming the through-hole, it is only necessary to roughly align it with the connection lead forming part, and it is also possible to connect it to an external board. The bump-shaped protrusion allows highly accurate positioning and provides highly reliable electrical connection.
また、従来のように接続リードを切断や折り曲げ加工す
る必要がないので接続、実装作業が容易になる.
さらに、比較的高価な異方導電性の膜や塗料を用いない
ので低コスト化が図れると共に、貫通孔の大きさや孔ピ
ッチを選択することによって接続面積も自由に設計でき
るので、接続面積の縮小化も可能となるものである。Additionally, there is no need to cut or bend the connection leads as in the past, making connection and mounting easier. Furthermore, since relatively expensive anisotropically conductive films and paints are not used, costs can be reduced, and the connection area can be freely designed by selecting the through-hole size and hole pitch, reducing the connection area. It is also possible to
第1図は本発明の半導体装置の実装構造を示す断面図、
第2図(a)および(b)は貫通孔内に金属物質を充填
し、バンプ状突出物を形成した絶縁性フィルムの部分断
面図、第3図は外部基板上の金属配!s(ランド部)に
、第2図(a)に示すバンプ状突出物を介して半導体装
置を実装した構造を示す断面図、第4図はフィルムキャ
リアを構成する絶縁性フィルムのバンプ状突出物形成面
に、熱接着性樹脂層を設けた状態を示す断面図である。
1・・・半導体素子、2″・・・金属物質、3・・・絶
縁性フィルム、4・・・接続リード、5・・・外部基板
、6・・・ランド部、7・・・微細貫通孔、8・・・熱
接着性樹脂層
第
第
図(こ)
第
/
図
図
第
図(bノFIG. 1 is a cross-sectional view showing the mounting structure of the semiconductor device of the present invention;
FIGS. 2(a) and 2(b) are partial cross-sectional views of an insulating film in which through-holes are filled with a metal substance to form bump-like protrusions, and FIG. 3 is a partial cross-sectional view of an insulating film in which through-holes are filled with a metal substance to form bump-like protrusions. A cross-sectional view showing a structure in which a semiconductor device is mounted on a land portion through a bump-shaped protrusion shown in FIG. 2(a), and FIG. FIG. 3 is a cross-sectional view showing a state in which a thermally adhesive resin layer is provided on a forming surface. DESCRIPTION OF SYMBOLS 1...Semiconductor element, 2''...Metallic substance, 3...Insulating film, 4...Connection lead, 5...External board, 6...Land part, 7...Minute penetration Hole, 8...Thermoadhesive resin layer Fig.
Claims (2)
なるフィルムキャリアに半導体素子を接合した半導体装
置と外部基板との実装構造において、外部基板上のラン
ド部と接する前記絶縁性フィルムのボンディング領域内
または該領域内とその近傍領域に、少なくとも1個の微
細貫通孔が厚み方向に設けられ、かつボンディング領域
内に設けられた貫通孔内が金属物質にて充填されている
と共にバンプ状突出物が形成され、このバンプ状突出物
を介して前記接続リードが外部基板上のランド部と接続
されてなる半導体装置の実装構造。(1) In a mounting structure of an external board and a semiconductor device in which a semiconductor element is bonded to a film carrier made of an insulating film with connection leads formed on one side, the bonding area of the insulating film that contacts the land portion on the external board Or, at least one fine through hole is provided in the thickness direction in the region and in the vicinity thereof, and the through hole provided in the bonding region is filled with a metal substance and a bump-like protrusion is provided. A mounting structure for a semiconductor device, in which the connection lead is connected to a land portion on an external substrate via the bump-like protrusion.
装置の実装構造。(2) The mounting structure for a semiconductor device according to claim (1), wherein the metal substance is solder.
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1050793A JP2785832B2 (en) | 1989-03-01 | 1989-03-01 | Semiconductor device mounting structure |
SG1996007397A SG49842A1 (en) | 1988-11-09 | 1989-11-07 | Wiring substrate film carrier semiconductor device made by using the film carrier and mounting structure comprising the semiconductor |
DE68929282T DE68929282T2 (en) | 1988-11-09 | 1989-11-07 | Conductor substrate, film carrier, semiconductor arrangement with the film carrier and mounting structure with the semiconductor arrangement |
EP89120640A EP0368262B1 (en) | 1988-11-09 | 1989-11-07 | Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device |
US07/433,108 US5072289A (en) | 1988-11-09 | 1989-11-08 | Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device |
KR1019890016132A KR960006763B1 (en) | 1988-11-09 | 1989-11-08 | Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1050793A JP2785832B2 (en) | 1989-03-01 | 1989-03-01 | Semiconductor device mounting structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02229442A true JPH02229442A (en) | 1990-09-12 |
JP2785832B2 JP2785832B2 (en) | 1998-08-13 |
Family
ID=12868679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1050793A Expired - Lifetime JP2785832B2 (en) | 1988-11-09 | 1989-03-01 | Semiconductor device mounting structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2785832B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5292401A (en) * | 1990-10-03 | 1994-03-08 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a fine pattern |
JPWO2016098865A1 (en) * | 2014-12-19 | 2017-09-21 | 富士フイルム株式会社 | Multilayer wiring board |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5358766A (en) * | 1976-11-09 | 1978-05-26 | Fujitsu Ltd | Packaging method of semiconductor element |
JPS5727141U (en) * | 1980-07-23 | 1982-02-12 |
-
1989
- 1989-03-01 JP JP1050793A patent/JP2785832B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5358766A (en) * | 1976-11-09 | 1978-05-26 | Fujitsu Ltd | Packaging method of semiconductor element |
JPS5727141U (en) * | 1980-07-23 | 1982-02-12 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5292401A (en) * | 1990-10-03 | 1994-03-08 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a fine pattern |
JPWO2016098865A1 (en) * | 2014-12-19 | 2017-09-21 | 富士フイルム株式会社 | Multilayer wiring board |
Also Published As
Publication number | Publication date |
---|---|
JP2785832B2 (en) | 1998-08-13 |
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