JPH02229432A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02229432A JPH02229432A JP5034389A JP5034389A JPH02229432A JP H02229432 A JPH02229432 A JP H02229432A JP 5034389 A JP5034389 A JP 5034389A JP 5034389 A JP5034389 A JP 5034389A JP H02229432 A JPH02229432 A JP H02229432A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- deposited
- mask
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 6
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 21
- 239000011229 interlayer Substances 0.000 abstract description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 abstract description 2
- 239000007853 buffer solution Substances 0.000 abstract description 2
- 229910018125 Al-Si Inorganic materials 0.000 abstract 4
- 229910018520 Al—Si Inorganic materials 0.000 abstract 4
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高信頼性の多層配線を有する半導体装置の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device having highly reliable multilayer wiring.
従来の技術
近年、半導体装置の高密度化.高集積化・高速化に伴な
い、配線寸法の微細化と配線の多層化が進んでいる。Conventional technology In recent years, the density of semiconductor devices has increased. With higher integration and faster speeds, interconnect dimensions are becoming smaller and interconnects are becoming more multi-layered.
以下に、従来方法により形成された2層配線について説
明する。第3図は、従来方法により形成された2層配線
の断面図であり、1は半導体基板、2は熱酸化膜、3は
第1配線層、6ぱ眉間絶縁膜、7は第2配線層である。A two-layer wiring formed by a conventional method will be described below. FIG. 3 is a cross-sectional view of a two-layer wiring formed by a conventional method, in which 1 is a semiconductor substrate, 2 is a thermal oxide film, 3 is a first wiring layer, 6 is an insulating film between the eyebrows, and 7 is a second wiring layer. It is.
配線の微細化に伴ない、第1配線層は主に異方性エッチ
ングによりパターンニングされる場合が多く、その断面
形状は、ほぼ垂直,角度は直角となる。As wiring becomes finer, the first wiring layer is often patterned mainly by anisotropic etching, and its cross-sectional shape is almost vertical and the angle is right angle.
発明が解決しようとする課題
しかしながら、異方性エッチングされた第1配線層上に
層間絶縁膜を堆積すると、第3図中βで示す第1配線層
表面とエッチング面とが交差する箇所においては、層間
絶縁膜は過剰に堆積し、断面でみると、ひさし状の形状
を呈する。この眉間絶縁膜上に第2配線層を被着すると
、前記ひさし形状の箇所で、第2配線層の断線を生じや
すいという問題を有していた。Problems to be Solved by the Invention However, when an interlayer insulating film is deposited on the anisotropically etched first wiring layer, at the location where the first wiring layer surface and the etched surface intersect, as indicated by β in FIG. , the interlayer insulating film is excessively deposited, and when viewed in cross section, it has an eave-like shape. When the second wiring layer is deposited on the glabella insulating film, there is a problem in that the second wiring layer is likely to be disconnected at the eaves-shaped portion.
本発明は、前記従来の問題点を解決するもので、層間絶
縁膜の被着形状を改善し、第2配線層の断線を防止する
半導体装置の製造方法を提供するものである。The present invention solves the above-mentioned conventional problems, and provides a method for manufacturing a semiconductor device that improves the adhesion shape of an interlayer insulating film and prevents disconnection of the second wiring layer.
課題を解決するだめの手段
この目的を達成するために、本発明は、半導体基板上全
面に被着した第1配線層となる金属薄膜上に、さらに絶
縁膜を被着させ、ついでレジストをパターンニング後、
前記レジストヲマスクに絶縁膜の等方性エッチングを行
ない、しかるのち、前記レジスtfマスクに金属薄膜を
異方性エッチングする工程とを備えた半導体装置の製造
方法である。Means for Solving the Problems In order to achieve this object, the present invention further deposits an insulating film on a metal thin film that is the first wiring layer that is deposited on the entire surface of a semiconductor substrate, and then patterns a resist. After ning,
This method of manufacturing a semiconductor device includes the steps of isotropically etching an insulating film on the resist mask, and then anisotropically etching a metal thin film on the resist TF mask.
作用
本発明の構成によると、第1層配線と絶縁膜とで形成さ
れた断面の角度は、直角とならず鈍角となり、この上に
堆積した層間絶縁膜の被覆特性も改善され、ひさし形状
とならず、第2層配線の断線金防止でき、高信頼性の多
層配線を形成することができる。According to the configuration of the present invention, the angle of the cross section formed by the first layer wiring and the insulating film is not a right angle but an obtuse angle, and the covering properties of the interlayer insulating film deposited thereon are also improved, resulting in a canopy shape. Therefore, disconnection of the second layer wiring can be prevented, and a highly reliable multilayer wiring can be formed.
実施例
以下、本発明の一実施例について図を参照しながら説明
する。第1図は、本発明で得られた半導体装置の断面図
であり、第2図a−fは、本発明実施例の工程順断面図
である。まず、第2図乙のように、熱酸化膜2が被着し
た半導体基板10表面に、▲l一阻M3をO.S〜1.
2μm蒸着する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device obtained by the present invention, and FIGS. 2 a-f are cross-sectional views in the order of steps of an embodiment of the present invention. Firstly, as shown in FIG. S~1.
Deposit 2 μm.
次に、第2図bのように、C V D ( Chemi
calVapor Deposition )法により
、N S G (Man−dopedSilicate
Glass )膜4を、2ooo〜6ooO人堆積す
る。次いで、第2図Cのように、通常のフォトリングラ
フィ技術により、パターンニングされたレジスト6を形
成する。次に、第2図dのように、このレジスト6′l
tマスクに弗酸と弗化アンモニウムの緩衝液によりNS
G膜4を等方性エッチングする。次に,第3図eのよう
に、レジスト6をマスクに、▲l − Si膜3を、通
常のRIM( Reactive Ion Itchi
ng 脹置を用い異方性エッチングする。次いで、レジ
スト6を除去すれば、第3図fのような構造になり、人
$−Si膜3とNSG膜4とで構成された断面部分であ
る第3図f中αの角度は鈍角となり、次いで、層間絶縁
膜としてP−SiN膜6を1μm堆積した時に、第3図
f中αの箇所での眉間膜の被覆形状は、ひさし形状とな
らず、第3図gのように、なだらかに被覆され、次いで
、第2配線層として、▲l−Si膜7を1.6〜2.0
μm蒸着しても、断線は生じない。Next, as shown in Figure 2b, C V D (Chemi
NSG (Man-doped Silicate)
Glass) film 4 is deposited to a thickness of 200 to 600 times. Next, as shown in FIG. 2C, a patterned resist 6 is formed by a normal photolithography technique. Next, as shown in FIG. 2d, this resist 6'l
NS with a buffer solution of hydrofluoric acid and ammonium fluoride on the T-mask.
The G film 4 is isotropically etched. Next, as shown in FIG.
Perform anisotropic etching using ng expansion. Next, when the resist 6 is removed, a structure as shown in FIG. 3f is obtained, and the angle α in FIG. Then, when a 1 μm thick P-SiN film 6 was deposited as an interlayer insulating film, the covering shape of the glabellar film at the point α in FIG. Then, as a second wiring layer, a ▲l-Si film 7 with a thickness of 1.6 to 2.0
Even with μm deposition, no disconnection occurs.
発明の効果
以上説明したように、本発明の半導体装置の製造方法に
よれば、多層配線工程における層間絶縁膜の被覆形状が
改善でき、第2層以降の配線の断線を防止し、高信頼性
の多層配線形成が容易にできる。Effects of the Invention As explained above, according to the method for manufacturing a semiconductor device of the present invention, the covering shape of the interlayer insulating film in the multilayer wiring process can be improved, the disconnection of the wiring in the second and subsequent layers can be prevented, and high reliability can be achieved. Multilayer wiring can be easily formed.
第1図は本発明の方法で得られた半導体装置の断面図、
第2図八〜gは本発明の一実施例の工程預断面図、第3
図は従来の半導体装置の断面図である。
1・・・・・・半導体基板、2・・・・・・熱酸化膜、
3・・・・・・第1配線層、4・・・・・・絶縁膜、5
・・・・・・レジスト、6・・・・・・層間絶縁膜、7
・・・・・・第2配線層、8・・・・・・保護膜。
代理人の氏名 弁理士 粟 野 重 孝 ほか1名/・
一半譚体基板
2・一一醗化膜
3 −一一 聳3 j 西己御艮贋
4−1球頃
g゛−層間花球侯
7゜゜〕I眉配課
第
図
第
図
SFIG. 1 is a cross-sectional view of a semiconductor device obtained by the method of the present invention;
Figures 2-8-g are process cross-sectional views of an embodiment of the present invention;
The figure is a cross-sectional view of a conventional semiconductor device. 1... Semiconductor substrate, 2... Thermal oxide film,
3...First wiring layer, 4...Insulating film, 5
...Resist, 6...Interlayer insulating film, 7
...Second wiring layer, 8...Protective film. Name of agent: Patent attorney Shigetaka Awano and 1 other person/・
1st half body board 2 11th film 3 - 11th layer 3
Claims (1)
前記半導体基板上全面に絶縁膜を被着する工程と、前記
半導体基板上にレジストをパターンニングする工程と、
前記レジストをマスクに絶縁膜を等方性エッチングする
工程と、前記レジストをマスクに金属薄膜を異方性エッ
チングする工程を有することを特徴とする半導体装置の
製造方法。A process of depositing a metal thin film for wiring on the entire surface of the semiconductor substrate,
a step of depositing an insulating film on the entire surface of the semiconductor substrate; a step of patterning a resist on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising the steps of isotropically etching an insulating film using the resist as a mask, and anisotropically etching a metal thin film using the resist as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5034389A JPH02229432A (en) | 1989-03-01 | 1989-03-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5034389A JPH02229432A (en) | 1989-03-01 | 1989-03-01 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02229432A true JPH02229432A (en) | 1990-09-12 |
Family
ID=12856274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5034389A Pending JPH02229432A (en) | 1989-03-01 | 1989-03-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02229432A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4897487A (en) * | 1972-03-27 | 1973-12-12 | ||
JPS63119547A (en) * | 1986-11-07 | 1988-05-24 | Nippon Telegr & Teleph Corp <Ntt> | Formation of wiring structure |
JPS6435931A (en) * | 1987-07-30 | 1989-02-07 | Nec Corp | Semiconductor device and manufacture thereof |
-
1989
- 1989-03-01 JP JP5034389A patent/JPH02229432A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4897487A (en) * | 1972-03-27 | 1973-12-12 | ||
JPS63119547A (en) * | 1986-11-07 | 1988-05-24 | Nippon Telegr & Teleph Corp <Ntt> | Formation of wiring structure |
JPS6435931A (en) * | 1987-07-30 | 1989-02-07 | Nec Corp | Semiconductor device and manufacture thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62295437A (en) | Forming method for multilayer interconnection | |
JPH02229432A (en) | Manufacture of semiconductor device | |
JPH0456254A (en) | Manufacture of semiconductor device | |
KR20010092704A (en) | Sputtering method and manufacturing method of semiconductor device using the same | |
JPS6360539B2 (en) | ||
JPH0799198A (en) | Manufacture for semiconductor device | |
JP2817752B2 (en) | Method for manufacturing semiconductor device | |
JP2702010B2 (en) | Method for manufacturing semiconductor device | |
JPS63228736A (en) | Manufacture of semiconductor device | |
JPS59195844A (en) | Manufacture of semiconductor device | |
JPS5833854A (en) | Manufacture of semiconductor device | |
JPS6254427A (en) | Manufacture of semiconductor device | |
JPS62136857A (en) | Manufacture of semiconductor device | |
JPH02105554A (en) | Manufacture of semiconductor device | |
JPH04102331A (en) | Manufacture of semiconductor device | |
JPS62293644A (en) | Manufacture of semiconductor device | |
JPH0324728A (en) | Manufacture of semiconductor device | |
JPS6065548A (en) | Forming method for multilayer interconnection | |
JPS63172444A (en) | Manufacture of semiconductor device | |
JPH056342B2 (en) | ||
JPS597220B2 (en) | Multilayer wiring method | |
JPS592351A (en) | Manufacture of semiconductor device | |
JPS62200746A (en) | Semiconductor device | |
JPS63166248A (en) | Semiconductor integrated circuit device and manufacture thereof | |
JPS60147137A (en) | Forming process of multilayered metallic wiring |