JPH02228633A - Semiconductor optical switch and its production - Google Patents

Abstract

PURPOSE:To provide an excellent small-loss characteristic and to perform optical switching independent upon wavelength by forming a waveguide layer as a low carrier layer interposed between a semiconductor substrate having a high carrier concentration and a clad layer and interposing the waveguide layer between areas having a low refractive index. CONSTITUTION:A waveguide layer 6 is vertically interposed between a lower clad layer 4 of first conductive type and an upper clad layer 8 of second conductive type, which have an inhibition zone larger than that of the layer 6, to have a double hetero structure. A low-refractive index area is generated in a part of the waveguide layer 6 by the plasma effect, and incident light is totally reflected on the boundary independently of the wavelength. The waveguide layer 6 is the low carrier layer interposed between upper and lower clad layers 8 and 4 and is interposed between areas having a low refractive index, and the carrier injection area is limited by a low resistance area 14 and an electric current block area 4a to reduce the loss, thereby performing the optical switching of high extinction ratio. Thus, a semiconductor optical switch is obtained which has the small-loss characteristic improved and is independent of the wavelength.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor optical switch, and particularly to a semiconductor optical switch that is composed of a semiconductor optical waveguide layer and that switches optical paths essential for optical communication and optical information processing. Regarding optical switches.

[Conventional technology]

Conventional optical switches include those that use polarization of light due to the acousto-optic effect of the optical transmission medium, those that use polarization of light due to the electro-optic effect of the medium, and those that use the electro-optic effect to change the coupling coefficient of a directional coupler. There are also devices that combine a directional coupler and an optical phase modulator. However, none of these waveguides satisfy all the basic characteristics of a waveguide switch, such as low loss characteristics, low crosstalk characteristics, and high speed. As a solution to these problems, proposals have been made to inject carriers into the waveguide layer to lower its refractive index and to utilize this change in refractive index for optical switches.

For example, in the semiconductor optical switch shown in Japanese Patent Application Laid-Open No. 60-173519, non-doped InGaAsP
The optical waveguide layer has a so-called double hetero structure sandwiched between an L1n-type 1nP substrate and an n-type 1nP grading layer with a larger forbidden band than this, and current flows in the forward direction in the p-n junction of this double heterostructure. to inject carriers into the InGaA5P optical waveguide layer. The refractive index is lowered by the plasma effect in this InGaAsP optical waveguide layer. However, the above JP-A-60
In the semiconductor optical switch of No. 173519, the loss has not yet been sufficiently improved, and its applications are also limited.

Furthermore, for example, in a semiconductor optical switch shown in Japanese Patent Application Laid-Open No. 60-134219, an InP substrate and an InP
InGaAs P layer and InP layered in order on the substrate
It has a superlattice layer consisting of layers and an InP grading layer on the superlattice layer, and carriers are injected by passing a current through the superlattice layer. Then, the absorption edge wavelength of light is shifted by the band filling effect in this superlattice layer. Thus, Kr.
The refractive index in the vicinity of the absorption edge wavelength is lowered due to the relationship: aIIers-Kronlg). However, the above-mentioned Japanese Patent Publication No. 6
In the semiconductor optical switch of No. 0-134219, the loss has not yet been sufficiently improved, and furthermore, the wavelength dependence that the applicable wavelength of light is limited to approximately match the bandgap energy Eg of the semiconductor is a problem. Yes, and its uses were limited.

[Problem to be solved by the invention]

As described above, conventional semiconductor optical switches do not fully satisfy low loss characteristics, and some have wavelength dependence, among other problems.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor optical switch with improved low loss characteristics and no wavelength dependence, and a method for manufacturing the semiconductor optical switch with high yield.

[Means to solve the problem]

A semiconductor optical switch according to the present invention includes: a first conductivity type semiconductor substrate having a first electrode formed on one surface; a first conductivity type lower cladding layer formed on the other surface of the semiconductor substrate;
a waveguide layer formed on the lower cladding layer and having a forbidden band smaller than that of the lower cladding layer and having a lower carrier concentration; and a waveguide layer formed on the waveguide layer and having a forbidden band lower than that of the waveguide layer. The second one is large and has a high carrier concentration.
a conductive type upper cladding layer; a buried layer provided on both sides of the waveguide layer and the upper and lower cladding layers and having a forbidden band larger than that of the waveguide layer; A resistance region, a second electrode formed on a low resistance region of the upper cladding layer, and a current in the lower cladding layer below the optical waveguide layer, only below the low resistance region. forming the low resistance region of the upper cladding layer and the current blocking region by applying a voltage between the first electrode and the second electrode; Furthermore, in the method for manufacturing a semiconductor optical switch of the present invention, which is characterized in that carriers are injected into a predetermined region of the waveguide layer through a region except for a portion of the waveguide layer, a lower cladding layer is formed on a semiconductor substrate of a first conductivity type. a first step of forming a first epitaxial layer of a first conductivity type, a second step of forming a high resistance region to serve as a current blocking region in a predetermined region of the first epitaxial layer; a third step of growing a second epitaxial layer having a forbidden band smaller than that of the semiconductor substrate and a lower carrier concentration on the first epitaxial layer; a fourth step of growing a third epitaxial layer of the second conductive 7u type which is larger than that of the second epitaxial layer and has a higher carrier concentration; and selectively etching the second and third epitaxial layers; a fifth step of forming a waveguide layer made of the second epitaxial layer and an upper cladding layer made of the third epitaxial layer on this waveguide layer; and both sides of the waveguide layer and the upper cladding layer. To,
a sixth step of forming a buried layer whose forbidden band is larger than that of the waveguide layer; a seventh step of forming a low resistance region in a part of the upper cladding layer; and a seventh step of forming a low resistance region of the cladding layer. A sixth step of forming a first electrode on the bottom surface of the semiconductor substrate and forming a second electrode on the bottom surface of the semiconductor substrate is included.

[Effect]

According to the semiconductor optical switch of the present invention, the waveguide layer is formed into a double layer sandwiched from above and below between a lower cladding layer of the first conductivity type and an upper cladding layer of the second conductivity type, each having a forbidden band larger than that of the waveguide layer. Due to the terrorist structure, a low refraction region is generated in a part of the waveguide layer due to the plasma effect, and the incident light is totally reflected at the boundary without depending on its wavelength. In addition, the waveguide layer is a low carrier layer sandwiched between the upper and lower cladding layers, and is sandwiched by low refractive regions on both sides, and the carrier injection region is further limited by the low resistance region and the current blocking region to reduce loss. let As a result, optical switching with a high extinction ratio is performed.

〔Example〕

Hereinafter, the present invention will be specifically described based on illustrated embodiments.

FIG. 1 is a sectional view showing a cross section of a semiconductor optical switch according to a first embodiment of the present invention, and FIG. 2 is a plan view showing a plane of the semiconductor optical switch shown in FIG. fj41.

In FIG. 1, for example, the carrier concentration is 2×10 18 co
On the n+ type GaAs substrate 2 of I-3, the carrier concentration l
x10cm, thickness 2μm n-type AI Ga A
s (x-0,1) lower cladding x 1-x layer 4 is formed. On this n-type AlGaAs lower cladding layer 4, there is a carrier concentration of 1×1015Qll-
Three n-type GaAs waveguide layers 6 are formed. On this n-type GaAs waveguide layer 6, a p+-type AfIC with a carrier concentration of 1×10 cln and a thickness of 1 μm is disposed.
;a As (x-0,1) cladding layer x
1-x8 is formed. In this way, the n-type GaAs waveguide layer 6, which has a small forbidden band, is sandwiched from above and below between the n+-type Ail Ga As lower cladding layer 4, which has a larger forbidden band, and the p+-type All GaAs cladding layer 8. In addition, a so-called double heterostructure is formed.

Carriers are formed on the p+ type An Ga As cladding layer 8.
An n-type GaAs contact layer 10 having a thickness of 1 .mu.m with a concentration of -3 a concentration IXIQc+n% is formed. In addition, n-type Ga A
An i-type AI GaAs (xmx 1-x 0.02) buried layer 12 is formed on both sides of the s-waveguide layer 6, the p-type AN GaAs cladding layer 8, and the n-type GaAs contact layer 10.

Furthermore, a current blocking region 4a, which is a high resistance region, is formed in a part of the lower cladding layer 4, as shown in FIG.

As shown in FIGS. 1 and 2, p+ type Aff
For example, zinc (Z
Low resistance region 1 where resistance is lowered by adding n )
4 is formed. And the current block area 4a is
As shown in FIG. 1, it is not provided in the lower portion of this low resistance region 14.

In addition, an n-type GaAs contact layer 10 and an i-type fi
, l On the GaAs buried layer 12, a thickness of 1000 nm is formed.
A silicon nitride film (S13N4 film) 16 and thickness 2
A silicon oxide film (SiO2 film) 18 of 00OA is deposited. Then, the silicon nitride layer 16 above the low resistance region 10 of the p+ type AD GaAs cladding layer 8 and the Cr layer connected to the n-type GaAs contact layer 10 through a contact hole opened in the silicon oxide film 18 are formed.
/Au electrode 20 is formed. Furthermore, n-type Ga
Au Ge /Nl/Au7 is also formed on the bottom surface of the As substrate 2.
Thirteen poles 22 are formed.

As shown in FIG. 2, in the n'''' type GaAs waveguide layer 6, two waveguides 24.
26 intersect at an intersection angle of 2θ. That is, p type A
D With respect to the boundary between the low resistance region 14 and other relatively high resistance regions in the GaAs cladding layer 8,
They intersect in opposite directions at intersecting angles θ. and,
Waveguide 24 has an input boat 28 and an output boat 30, and waveguide 26 has an input boat 32 and an output boat 34.

Next, the operation of the apparatus of the first embodiment will be explained.

A predetermined voltage is applied between the Cr/Au electrode 20 and the Au Ge /Nl /Au electrode 22 to form a p+ type AlGaAs
When current is passed in the forward direction through the pn junction of the double heterostructure consisting of the cladding layer 8, the n'''' type GaAs waveguide layer 6, and the n type AlGaAs lower cladding layer 4, carriers are injected. However, since the low resistance region 14 is formed in one half of the p+ type AI Ga As cladding layer 8, the carriers are injected only into one half of the n type GaAs waveguide 6 through this low resistance region 14. It will be done.

Furthermore, carriers are injected only from the lower part of the low resistance region 14 by the current blocking region 4a formed in the lower cladding layer 4. Therefore, carriers are not injected into the other half of the n-type GaAs waveguide layer 6 that is not located below the low resistance region 14. That is, the low resistance region 14 formed in the p+ type AD Ga As cladding layer 8 and the current blocking region 4a formed in the lower cladding layer 4 limit the injection of carriers to a predetermined region, and due to this restriction, the injection of carriers is Improving injection efficiency.

In this way, carriers are injected into only one half of the n'''' type GaAs waveguide layer 6 and confined there, so that the dielectric constant of that portion is lowered by the plasma effect and the refractive index is lowered. Therefore, the n-type GaAs waveguide layer 6 is divided into two regions having mutually different refractive indexes.

Now, as shown in FIG. 2, the light incident from the input boat 28 of the waveguide 24 passes through the Cr/Au electrode 20 and
When no voltage is applied between the Ge /Ni /Au electrode 22 , the light passes through the n″″ type GaAs waveguide layer 6 to the output boat 30 of the waveguide 24 . However, C
A predetermined voltage is applied between the r/Auff1 pole 20 and the Au Ge /N1 /Au electrode 22, and the n-type Ga A
When the refractive index of one half of the s waveguide layer 6 decreases, the refractive index change rate is Δn, and the refractive index of the waveguide 24.26 is n.
, where θ is the intersection angle between the waveguide 24 and the boundary between two regions with different refractive indexes in the n-type GaAs waveguide layer 6, the relationship is θ×90°−s i n−′ (1+Δn/n). When the following is satisfied, the light incident from the input boat 28 of the waveguide 24 does not proceed to the output boat 30, and the light enters the waveguide 24 as n-type GaAs.
The light is totally reflected at the boundary between two regions of the waveguide layer 6 having different refractive indexes, and travels to the output boat 34 of the waveguide 26 . In this way, switching for incident light is performed.

In the semiconductor switch manufactured according to the first embodiment, the carrier concentration of the n'''' type GaAs waveguide layer 6 is as low as I x 1015c+n-3;
Free carrier absorption is suppressed to a low level, and loss due to light absorption is small. Furthermore, since the carrier concentration of the p+ type AN GaAs cladding layer 8 is as high as I x 1018 cm-'',
A plasma effect occurs in the entire n-type GaAs waveguide layer 6 into which carriers are injected, and the refractive index decreases more rapidly in a portion of the n-type GaAs waveguide layer 6 into which carriers are injected. Even if the p+ type AI Ga As cladding layer 8 has a high carrier content, the loss due to light absorption is small because not much light enters the p+ type AI Ga As cladding layer 8.

Further, the confinement of light in the lateral direction in the n-type GaAs waveguide layer 6 is not achieved by making the n-type GaAs waveguide layer 6 ridge-shaped, but by forming n″″-type GaA on both sides thereof.
This is achieved by having a structure sandwiched between the i-type AI GaAs buried layer 12, which has a larger forbidden band than the s-waveguide layer 6, that is, has a low refractive index.
Optical loss on the side walls of the As waveguide layer 6 is small.

Furthermore, since the plasma effect in which the refractive index decreases due to carrier injection is used, the n-type GaAs waveguide layer 6
This makes it possible to perform a wide switching action on light with energy smaller than the forbidden band width.

In other words, wavelength dependence is eliminated. For example, in the first embodiment, since GaAs is used for the waveguide layer,
It can be used for light with a wavelength longer than the forbidden band width of 0.9 μm, and is 1.3 μm, which is normally used in optical communications.
It can sufficiently cover the m band.

In the device according to the first embodiment, the waveguide layer 6 is formed of n'' type GaAs with a low carrier concentration, but its conductivity type is not limited to the n-type. p-type GaAs'Pi-type GaAs. However, since holes absorb more light than electrons, n-type is more desirable than p-type.

Furthermore, the lower cladding layer 4 and the cladding layer 8, which sandwich the n-type GaAs waveguide layer 6 in a double/tero structure, are a combination of n-type and p-type AllGaAs, respectively, but it is unclear which conductivity type they have. Replaced, p type A
I GaAs lower cladding layer and n-type AD Ga
It may also be a combination of As cladding layers. Of course in this case, base! i22 is a p+ type GaAs substrate.

Furthermore, in the first embodiment, GaAs
Although the optical switch is constructed using a semiconductor of the above-mentioned type, an optical switch having a similar structure can also be constructed using other semiconductors such as InGaAs P-based or InP-based semiconductors.

Next, a semiconductor optical switch according to a second embodiment of the present invention will be described.

FIG. 3 is a sectional view showing the cross section of the semiconductor optical switch of the second embodiment, and FIG. 4 is a plan view showing the plane thereof.

In FIG. 3, for example, the carrier concentration is 2×1018, −
On the p+ type GaAs p layer 42 of No. 3, there is an n-type AD layer with a carrier x'B-a rear concentration lX10c+n and a thickness of 2 am.
Ga As (x=0.1) lower cladding X
A l-X layer 44 is formed. On this n-type AN GaAs lower cladding layer 44, there is a carrier concentration of 1×10 15 C.
An n-type GaAs waveguide layer 46 of I11-3 is formed. On this n-type GaAs waveguide layer 46, a p-type layer with a carrier concentration lX10an and a thickness of 1 μm
A type AI Ga As (x-x 1-x 0.1) cladding layer 48 is formed. In this way, the n″″ type GaAs waveguide layer 46 with a small forbidden band is formed.
The n-type AfIGaAs lower cladding layer 44 and the p-type AfIGaAs cladding layer 4 have larger forbidden bands than this.
A so-called double heterostructure is formed, which is sandwiched between the two from above and below.

Then, on the p'' type AlGaAs cladding layer 48, an n type Ga A layer with a carrier concentration lX1Oc+n and a thickness of 1 μm is formed.
An s-contact layer 50 is formed. Also, n-type G
An i-type AgGaAs buried layer 52 is formed on both sides of the a As waveguide layer 46, the p+-type AN GaAs cladding layer 48, and the n-type GaAs contact layer 50.

Furthermore, a current blocking region 44a, which is a high resistance region, is formed below the waveguide layer 46 in the lower cladding layer 44, as shown in FIG.

As shown in FIGS. 3 and 4, p+ type Aj!
A low-resistance region 54 is formed in the center of the GaAs cladding layer 48 to which, for example, zinc is added and the resistance is lowered. The current block region 44a is not provided in the lower part of the low resistance region 54, as shown in FIG. Then, an n-type GaAs contact layer 5
A silicon nitride film 56 with a thickness of 1000A and a silicon nitride film 56 with a thickness of 20A are formed on the 0 and i type Ail Ga As buried layers 52.
A silicon oxide film 58 of 0OA is deposited. Then, an n-type G
a Au Ge / connected to As contact layer 5°
A Nl/Au electrode 60 is formed. Furthermore, n
Cr/Au is also formed on the bottom surface of the GaAs type substrate 42.
An electrode 62 is formed.

As shown in FIG. 4, an n-type GaAs waveguide layer 4
6, two "waveguides 64 having a waveguide width W
．． 66 intersect at an intersection angle of 2θ.

That is, they intersect the boundaries between the low resistance region 54 and other relatively high resistance regions in the p+ type AN Ga As cladding layer 48 in opposite directions at a crossing angle θ. The waveguide 64 has an input boat 68 and an output boat 70, and the waveguide 66 has an input boat 72 and an output boat 74.

Next, the operation of the device of the second embodiment will be explained.

The operation of the device of this second embodiment is almost the same as that of the first embodiment, except that p+ type An Ga As
Since the low resistance region 54 is formed in the center of the cladding layer 48, carriers pass through the low resistance region 54 of the p-type GaAs cladding layer 48 and enter only the center of the n-type GaAs waveguide 46. Injected. Furthermore, the current blocking region 44a formed in the lower cladding layer 44 limits the current to only the central portion of the waveguide layer 46 below the low resistance layer 54. Therefore, n-
No carriers are injected into both sides of the GaAs waveguide layer 46. That is, the p+ type AgcaAs cladding layer 4
Low resistance region 54 and current block region 4 formed in 8
4a limits carrier injection to a predetermined region, and
This restriction increases carrier injection efficiency. In the second embodiment, the region into which carriers are injected is more limited than in the first embodiment, so that the carrier injection efficiency is even higher.

In this way, carriers are injected only into the central part of the n-type GaAs waveguide layer 46 and are confined there, so that the dielectric constant of that part decreases due to the plasma effect, and the refractive index decreases. Therefore, the n-type GaAs waveguide layer 46 is divided into three regions having different refractive indexes.

Now, as shown in FIG. 4, the light incident from the input boat 68 of the waveguide 64 and the input boat 7 of the waveguide 66
The light incident from 2 is Au Ge /Ni/Auff1
When no voltage is applied between pole 60 and Cr/Au electrode 62, output ports 70 of waveguide 64 and waveguide 66 pass through n-type GaAs waveguide layer 46, respectively.
proceed to the launch boat 74. However, Au Ge/
A predetermined voltage is applied between the Nt/Au electrode 60 and the Cr/Au electrode 62, and the n″″ type GaAs waveguide layer 46
When the refractive index of the central part of the waveguide 64 decreases, the light incident from the input boat 68 of the waveguide 64 is totally reflected at the boundary between two regions of the n-type GaAs waveguide layer 46 having different refractive indexes, and Light that travels to the output boat 74 of the waveguide 66 and similarly enters from the input boat 72 of the waveguide 66 travels to the output boat 70 of the waveguide 64 .

In this way, the semiconductor switch according to the second embodiment performs a switching action on incident light, whereas the semiconductor switch according to the first embodiment performs a switching action only on incident light from one direction. In contrast to the directional switch, this second embodiment is a so-called bidirectional switch that performs a switching action on incident light from two directions. All of the various effects of the first embodiment described above also exist in this m2 embodiment.

In the second embodiment, the waveguide layer 46 is formed of n-type GaAs with a low carrier concentration, but the Tu type is not limited to the n-type. It may be formed from p-type GaAs or i-type GaAs. However, since holes absorb more light than electrons, n-type is more desirable than p-type.

Further, the lower cladding layer 44 and the cladding layer 48 which sandwich the low-type GaAs waveguide layer 46 in a double heterostructure are a combination of n+ type and p+ type AN GaAs, respectively, but their conductivity types are reversed. , p-type AI GaAs lower cladding layer and n+-type AΩGa
It may also be a combination of As cladding layers. Furthermore, although the optical switch is constructed using a GaAs-based semiconductor, an optical switch having a similar structure can also be constructed using other semiconductors such as InGaAsP-based or InP-based semiconductors.

Next, a method for manufacturing a semiconductor optical switch according to a first embodiment of the present invention will be sequentially explained using FIG.

As a semiconductor substrate, for example, the carrier concentration is 2×1018 cI.
On the n+ type Ga As substrate 2 of 11-3,
IJA concentration lx10cm, thickness 2μm n-type Ag G
a As (x-0,1) lower cladding x
Grow l-X layer 4. Next, a portion corresponding to the lower part of the low resistance region to be formed later on the lower cladding layer 4 is covered with a mask layer, and H+ is 3×10/3×400Ke■.
Ions are implanted to a concentration of cs+2, and the current block region 4a is
form. As a method for forming this current blocking region 4a, further, Be ions are irradiated with I×10 at 400 KeV.
It can also be formed by ion implantation at a concentration of /c112 or by zinc diffusion. Then, on this n+ type Ap GaAs lower cladding layer 4, an n- type GaAs layer with a carrier concentration of 1×10 and a thickness of 1 μm is deposited.
Epitaxial layer 5 is grown. Furthermore, on this n″″ type GaAs epitaxial layer 5, a p+ type A layer with a B −8 carrier concentration of l×10 cm and a thickness of 1 μm is disposed.
N Ga 1. An As (x-0,1) layer 7 is grown. In this way, n-type Ga A with a small forbidden band
s epitaxial layer 5 has a larger forbidden band than n+
type AgGaAs lower cladding layer 4 and p+ type A, l?
sandwiched between the GaAs epitaxial layer 7 from above and below,
It forms a so-called double heterostructure.

Then, on the p-type AgGaAs epitaxial layer 7,
Carrier concentration lXl0CII+, thickness 1 μm n-type Ga
An As epitaxial layer 9 is grown.

Note that these n-type AN GaAs lower cladding layers 4
, n-type GaAs epitaxial layer 5, p+-type AD
The GaAs epitaxial layer 7 and the n-type GaAs epitaxial layer 9 are lattice-matched and stacked one after another by epitaxial growth using OMVPE (organic metal vapor phase epitaxial) method (see FIG. 5(a)).
.

In the next step, heat C is applied onto the n-type GaAs epitaxial layer 9.
Silicon nitride film 8 is grown using the VD (chemical vapor deposition) method.
2 (see FIG. 5(b)). Subsequently, a resist 84 having a cross waveguide pattern having a waveguide width W and a cross angle 2θ is formed on the silicon nitride film 82 using photolithography (see FIG. 5(c)).

After removing the silicon nitride film 82 by etching using the patterned resist 84 as a mask, the n-type GaAs epitaxial layer 9, the p-type AlGaAs epitaxial layer 7 and the n-type GaAs epitaxial layer are further etched using a dry etching method. Etching step 5 is performed until the upper surface of n-type AfIGaAs lower cladding layer 4 is reached.

The dry etching conditions are, for example, BCRa: 10
sec1M, 1. 5 P a, 0, 5 W
/ am 2.

By this dry etching, Aff GaA
an n-type GaAs waveguide layer 6 on the s lower cladding layer 4;
p+ type AN Ga on this n- type GaAs waveguide layer 6
As cladding layer 8 and this p+ type AN Ga A
An n-type GaAs contact layer 10 is formed on each of the s-cladding layers 8. After that, the resist 84 is removed (
(See Figure 5(d)).

Next, the already patterned silicon oxide 88
2 as a mask, the exposed n-type AfIGaAs
i-type AgXGaAs (
x-0,02) The buried layer 12 is grown by -X. The i-type Ai)GaAs buried layer 12 is grown using the OMVPE method under conditions such as a substrate temperature Tsub of 650° C. and an atmospheric pressure of 10 Torr until it reaches the height of the upper surface of the n-type GaAs contact layer 10. In this way, n-type Ga
As waveguide layer 6, p-type AρG@As cladding layer 8,
Both sides of the n-type GaAs contact layer 10 are sandwiched between 1-type AN GaAs buried layers 12 (see FIG. 5(e)).

Next, after removing the silicon nitride film 82, the i-type AΩG
a. On the As buried layer 12 and the n-type GaAs contact layer 10, NH:
5.6Ω/min, S1H (4%)/N2 (96%)
:2.9j! /min, thickness 100OA
A silicon nitride film 16 is deposited. Subsequently, the silicon nitride film 16 is coated at a temperature of 2 using plasma CVD.
50℃, 50W 1 atm 0. 9TorrSS i H4
(4%)/N (96%): 20scca+
, N20: Under the condition of 30.0 sec+a,
A silicon oxide film 18 having a thickness of 200° is deposited (see FIG. 5(f)).

Next, a resist 86 is applied to the entire surface, and an opening is opened in the resist 86 at a location corresponding to a half of the p-type AN Ga As cladding layer 8 using photolithography.

Using the patterned resist 86 as a mask, the silicon oxide film 18 and the silicon nitride film 14 are etched using, for example, RIE (reactive ion etching) using CF4 to form a window (FIG. 5). (see (g)).

Next, after removing the resist 86, this sample was
Vacuum seal in a quartz ampoule with rl AS 2. Then, using the silicon oxide film 16 and the silicon nitride film 14, which have openings corresponding to a portion of the p+ type A11GaAs cladding layer 8, as masks, zinc is diffused at a temperature of 630°C. At this time, this zinc diffusion occurs in the p region slightly above the top surface of the n-type GaAs waveguide layer 6.
The type A, 17 Ga As cladding layer 8 is made to reach inside. The reason why zinc diffusion is prevented from reaching the upper surface of the n-type GaAs waveguide layer 6 in this way is to prevent zinc from being diffused into the n-type GaAs waveguide layer 6 during heat treatment in a later step. It is. In this way, a low resistance region 14 having a relatively low resistance due to addition of zinc Zn is formed in a part of the p-type A, 77 Ga As cladding layer 8 (see FIG. 5(h)). .

Next, a Cr/Auff1 pole 20 is formed on the upper surface and connected to the n-type GaAs contact layer 10 through a contact hole already made in the silicon oxide film 18 and silicon nitride film. Further, an AuGe/Ni/Au electrode 22 is also formed on the bottom surface of the n-type GaAs substrate 2 (see FIG. 5(i)).

Although not shown, the waveguide has a width W and a crossing angle 2θ.
Two waveguides intersecting each other are connected to an n-type GaAs waveguide layer 6. These two waveguides are connected to the boundary between the low resistance region 14 and other relatively high resistance regions in the p+ type AΩGaAs cladding layer 8.
They intersect in opposite directions at an intersection angle θ.

Finally, the end face is opened to a length of 5III, and the waveguide chip is cut out. In this way, the first
A semiconductor optical switch according to the embodiment is manufactured.

Note that in patterning the resist 86, instead of opening the resist 86 at a location corresponding to a part of the p+) MAD Ga As cladding layer 8 as described above,
An opening is opened in the resist 86 at a location corresponding to the center of the p+ type AN Ga As cladding layer 8, and the silicon oxide film 1 is formed using the patterned resist 86 as a mask.
8 and silicon nitride 816, and using the silicon oxide film 18 and silicon nitride film 16, which are opened in a location corresponding to the center of the p-type AgGaAs cladding layer 8, as a mask, zinc is diffused.
If a low resistance region is formed in the center of the + type AΩGaAs cladding layer 8 and a current blocking region is formed except for the lower part of the low resistance region in the lower cladding layer 44, an M structure similar to that of the second embodiment can be obtained. This makes it possible to manufacture bidirectional semiconductor optical switches.

Further, although zinc is diffused into one half of the p-type AJ7 GaAs cladding layer 8 to form the low resistance region 14, for example, beryllium (Be) may be used instead of zinc.

Also, n-type GaAs l;! ;On board 2, n+ type A
J7GaAs lower cladding layer 4, n-type GaAs waveguide layer 6, p-type Aj! Although a GaAs cladding layer 8 and an n-type GaAs layer contact layer 10 are formed, this combination is not used.
The conductivity types of the substrates and each layer sandwiching the As waveguide layer 6 are exchanged, and a p+ type AN G is formed on the p type Ga As substrate.
a As lower cladding layer, p-type GaAs waveguide layer 6
, n+ type AM Ga As cladding layer, and p type Ga
It may be formed in combination with an As layer and a contact layer. However, in this case, n+ type A, 9 Ga
The impurity implanted to form a low resistance region in a part of the As cladding layer must be silicon (Sl), for example.

In either case, the conductivity type of the waveguide layer 6 is not limited to n-type, but is, for example, p-type Ga with a low carrier concentration.
It may be As or i-type GaAs.

However, since holes absorb more light than electrons, p
The n-type is more desirable than the ``'' type.

[Effects of the Invention] As described above in detail, according to the optical switch manufactured by the present invention, the waveguide layer has a semiconductor substrate of a first conductivity type having a forbidden band larger than the forbidden band thereof, and a second conductive type semiconductor substrate. By forming a double heterostructure sandwiched from above and below by the cladding layer of the mold, a low refraction region is created in a part of the waveguide layer due to the plasma effect, and at the boundary, the incident light depends on its wavelength. Allows total reflection without any interference. Further, the waveguide layer is a low carrier layer sandwiched between a semiconductor substrate with a high carrier concentration and a cladding layer, and is sandwiched on both sides by low refractive regions, thereby reducing loss. Furthermore, the carrier injection region is precisely defined by the low resistance region formed in the upper cladding layer and the current blocking region formed in the lower cladding layer, which provides optical switching with a high extinction ratio. It is possible to perform optical switching that has Ti loss characteristics and is not wavelength dependent.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the cross section of a semiconductor optical switch manufactured according to the first embodiment of the present invention, FIG. 2 is a plan view showing the plane thereof, and FIG. Sectional view showing the cross section of the semiconductor optical switch manufactured according to the example, No. 4
The figure is a plan view showing the plane, and FIG. 5 is the first embodiment of the present invention.
FIG. 3 is a process diagram showing a method for manufacturing a semiconductor optical switch according to an embodiment of the present invention. 2--- n+ type Ga As substrate, 4... n+ type AI Ga As lower cladding layer, 4a
...Current block region, 5...n-type GaAs epitaxial layer, 6.46
...n'' type Ga As waveguide layer, 7...p+ type A
, Q GaAs epitaxial layer, 8...p type A
ΩGaAs cladding layer, 9...n-type GaAs epitaxial layer, 10...n-type GaAs layer contact layer, 12.52-i-type AfIGaAs buried layer, 1
454...Low resistance region, 16.56.82...Silicon nitride film (S13N4 film), 18°20°22°24°28°58...Silicon oxide film (SiO2 film), 62-C
r/A u electrode, 60・=Au Ge/Nl/Au electrode, 26.64
．． 66... Waveguide, 32.68,72. ...Incidence boat.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type having a first electrode formed on one surface; a lower cladding layer of a first conductivity type formed on the other surface of the semiconductor substrate; and the lower cladding layer of the first conductivity type formed on the other surface of the semiconductor substrate. a waveguide layer formed on the cladding layer and having a forbidden band smaller than that of the lower cladding layer and a lower carrier concentration; and a waveguide layer formed on the waveguide layer and having a forbidden band larger than that of the waveguide layer and having a lower carrier concentration. an upper cladding layer of a second conductivity type with a high concentration; a buried layer provided on both sides of the waveguide layer and the upper and lower cladding layers and having a forbidden band larger than that of the waveguide layer; and a part of the upper cladding layer. a second electrode formed on the low resistance region of the upper cladding layer and the lower cladding layer below the optical waveguide layer, only below the low resistance region. a current blocking region formed to allow a current to flow through the low resistance region of the upper cladding layer and the current blocking region by a voltage applied between the first electrode and the second electrode. A semiconductor optical switch characterized in that carriers are injected into a predetermined region of the waveguide layer through a region excluding a region forming portion. 2. The semiconductor optical switch according to claim 1, wherein the low resistance layer is formed in one half of the upper cladding layer. 3. The semiconductor optical switch according to claim 1, wherein the low resistance region is formed in the center of the upper cladding layer. 4. A first step of forming a first epitaxial layer of a first conductivity type to serve as a lower cladding layer on a semiconductor substrate of a first conductivity type, and forming a current blocking region in a predetermined region of the first epitaxial layer. a third step of growing a second epitaxial layer on the first epitaxial layer with a forbidden band smaller than that of the semiconductor substrate and with a lower carrier concentration; , a fourth step of growing, on the second epitaxial layer, a third epitaxial layer of the second conductivity type, the third epitaxial layer having a forbidden band larger than that of the second epitaxial layer and having a higher carrier concentration; and a fifth epitaxial layer for selectively etching the third epitaxial layer to form a waveguide layer made of the second epitaxial layer and an upper cladding layer made of the third epitaxial layer on the waveguide layer, respectively. a sixth step of forming a buried layer having a forbidden band larger than that of the waveguide layer on both sides of the waveguide layer and the upper cladding layer; forming a low resistance region in a part of the upper cladding layer; seventh to form
and an eighth step of forming a first electrode on the low resistance region of the cladding layer and forming a second electrode on the bottom surface of the semiconductor substrate. A method of manufacturing an optical switch. 5. When forming the high resistance region in the second step, Z
5. The method of manufacturing a semiconductor optical switch according to claim 4, wherein an n-diffusion method, an ion implantation method, or the like is used. 6. The method of manufacturing a semiconductor optical switch according to claim 4 or 5, wherein the low resistance region is formed in one half of the upper cladding layer. 7. The method of manufacturing a semiconductor optical switch according to claim 4, 5 or 6, wherein the low resistance region is formed in the center of the cladding layer.