JPH0279820A - Production of semiconductor optical switch - Google Patents

Abstract

PURPOSE:To obtain a semiconductor optical switch generating scarce optical loss and having no dependency on wavelength by constituting a waveguide layer of a double hetero structure inserted between a first electroconducting type semiconductor substrate having a large forbidden band than the forbidden band of the waveguide layer and a second electroconducting type clad layer above the waveguide layer and an embedding layer therefor. CONSTITUTION:After forming an epitaxial layer 5 having a forbidden band smaller than the forbidden band of a semiconductor substrate 2 and smaller carrier concentration on a first electroconducting type semiconductor substrate 2 by epitaxial growth, a waveguide layer 6 is formed by etching the epitaxial layer 5 selectively. Then, a second electrconducting type clad layer 10 having a larger forbidden band than the forbidden band of the waveguide layer 6 and a higher carrier concn. is formed above the waveguide layer 6 and an embedding layer 8 by forming an embedding layer 8 having a larger forbidden band than that of the waveguide layer on both sides of the waveguide layer 6. Thus, the waveguide layer 6 has a double hetero structure inserted from above and below between a first electroconducting type semiconductor substrate 2 having a forbidden band larger than the forbidden band of the waveguide layer 6 and a second electroconducting type clad layer 10. Thus, optical switching with high light extinction ratio has become possible.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor optical switch, and particularly to a semiconductor optical switch that is composed of a semiconductor optical waveguide layer and that switches optical paths essential for optical communication and optical information processing. Regarding optical switches.

[Conventional technology]

Conventional optical switches include those that use polarization of light due to the acousto-optic effect of the optical transmission medium, those that use polarization of light due to the electro-optic effect of the medium, and those that use the electro-optic effect to change the coupling coefficient of a directional coupler. There are also devices that combine a directional coupler and an optical phase modulator. However, none of these waveguides satisfy all the basic characteristics of a waveguide switch, such as low loss characteristics, low crosstalk characteristics, and high speed. As a solution to these problems, proposals have been made to inject carriers into the waveguide layer to lower its refractive index and to utilize this change in refractive index for optical switches.

For example, in the semiconductor optical switch shown in Japanese Patent Application Laid-Open No. 60-173519, non-doped InGaAsP
The optical waveguide layer has a so-called double heterostructure sandwiched between an n-type 1nP substrate with a larger forbidden band and a p-type 1nP grading layer, and current flows in the forward direction in the p-n junction of this double heterostructure. to inject carriers into the InGaAs optical waveguide layer. The refractive index is lowered by the plasma effect in this InGaAs optical waveguide layer.

However, in the semiconductor optical switch disclosed in Japanese Patent Application Laid-Open No. 60-173519, the loss has not yet been sufficiently improved, and its applications are also limited.

Furthermore, for example, in a semiconductor optical switch shown in Japanese Patent Application Laid-Open No. 60-134219, an InP substrate and an InP
InGaAs P layer and InP layered in order on the substrate
It has a superlattice layer consisting of layers and an InP grading layer on the superlattice layer, and carriers are injected by passing a current through the superlattice layer. The absorption edge wavelength of light is shifted by the band filling effect in this superlattice layer. Thus, Kramers-Kro
nig ), the refractive index near the absorption edge wavelength is lowered. However, in the semiconductor optical switch of JP-A No. 60-134219, the loss has not yet been sufficiently improved, and furthermore, the applicable wavelength of light is limited to almost match the bandgap energy Eg of the semiconductor. It has wavelength dependence, which limits its applications.

[Problem to be solved by the invention]

As described above, conventional semiconductor optical switches do not fully satisfy low loss characteristics, and some have wavelength dependence, among other problems.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor optical switch with improved low loss characteristics and no wavelength dependence and a high yield.

[Means to solve the problem]

The method for manufacturing a semiconductor optical switch according to the present invention includes a first step of growing an epitaxial layer having a forbidden band smaller than that of the semiconductor substrate and a lower carrier concentration on a semiconductor substrate of a first conductivity type, and selectively growing an epitaxial layer. a second step of etching to form a waveguide layer; a third step of forming a buried layer on both sides of the waveguide layer with a forbidden band larger than that of the waveguide layer; and a third step of etching the waveguide layer and the buried layer. a fourth step of forming a second conductivity type cladding layer having a forbidden band larger than that of the waveguide layer and a high carrier concentration; a fifth step of forming a low resistance region in a part of the cladding layer;
The method is characterized by comprising a sixth step of forming a first electrode on the low resistance region of the cladding layer and forming a second electrode on the bottom surface of the semiconductor substrate.

[Effect]

According to the semiconductor optical switch manufactured by the method of the present invention, the waveguide layer is sandwiched from above and below between the semiconductor substrate of the first conductivity type and the cladding layer of the second conductivity type, which has a forbidden band larger than the forbidden band of the waveguide layer. Due to the double heterostructure, a low refraction region is generated in a part of the waveguide layer due to the plasma effect, and incident light is totally reflected at the boundary thereof, regardless of its wavelength. Further, the waveguide layer is a low carrier layer sandwiched between a semiconductor substrate with a high carrier concentration and a cladding layer, and is sandwiched on both sides by low refractive regions, thereby reducing loss.

As a result, optical switching with a high extinction ratio is performed.

〔Example〕

Hereinafter, the present invention will be specifically described based on illustrated embodiments.

FIG. 1 is a sectional view showing a cross section of a semiconductor optical switch manufactured according to a first embodiment of the present invention, and FIG. 2 is a plan view showing the plane thereof.

In FIG. 1, for example, the carrier concentration is 2×1018 c
n-type AN with a carrier concentration I x 1018 mark-3 and a thickness of 2 pm on an n+ type GaAs substrate 2 of m-3.
GaAs (x-0,1) lower cladding y,
1-x layer 4 is formed. On this n-type AN GaAs lower cladding layer 4, there is a carrier concentration lX1015cI.
A T+-3 n-type GaAs waveguide layer 6 is formed. On both sides of this n'''' type GaAs waveguide layer 6, n-type Aff GaAs (x-0,02) with a carrier concentration I x 1015clI+-3 or less is formed.
A buried x l-x buried layer 8 is formed. Furthermore, these n-type G
a On the As waveguide layer 6 and the n-type AI GaAs buried layer 8, there is a carrier concentration of 1×]018cITl-3
, 1 μm thick p+ type AflGal-xAs
(x=0.1) A cladding layer 10 is formed.

In this way, the n"" type GaAs waveguide layer 6 with a small forbidden band becomes the n+ type AN Ga with a larger forbidden band.
A so-called double heterostructure is formed between the As lower cladding layer 4 and the p-type AN Ga As cladding layer 10 from above and below.

A p-type GaAs contact layer 12 having a carrier concentration of 1×10 cm and a thickness of 0.5 μm is formed on the p-type A, 17 GaAs cladding layer 8.

As shown in FIGS. 1 and 2, p+ type ARGa
In the As cladding layer 10, for example, zinc (Zn
) is added to form a low resistance region 14 whose resistance is low. Further, on the p+ type GaAs contact layer 12, a silicon nitride film (Si3
N4 film) 16mm thick and silicon oxide film (2000mm thick)
A SiO2 film) 18 is deposited. and p type A
A Cr/Au IE electrode 2 is connected to the p-type GaAs contact layer 12 through a contact hole opened in the silicon nitride film 16 and silicon oxide film 18 above the low resistance region 14 of the D GaAs cladding layer 10.
0 is formed. Furthermore, an n-type GaAs substrate 2
An Au Ge /Ni/Au electrode 22 is also formed on the bottom surface.

As shown in FIG. 2, an n-type GaAs waveguide layer 6
In , two waveguides 24 and 26 with waveguide width W are used.
intersect at an intersection angle of 2θ. That is, p+ type A, 1
7 Low resistance region 14 in GaAs cladding layer 10
and other regions of relatively high resistance, each intersects in the opposite direction at a crossing angle θ. The waveguide 24 has an input boat 28 and an output boat 30, and the waveguide 26 has an input port 32 and an output boat 34.

Next, the operation of the above device will be explained.

A predetermined voltage is applied between the Cr/Au electrode 20 and the Au Ge /Nl /Au electrode 22 to form a p-type AlGaAs
When current is passed in the forward direction through the pn junction of the double heterostructure consisting of the cladding layer 10, the n-type GaAs waveguide layer 6, and the n+-type AΩGaAs lower cladding layer 4, carriers are injected. However, p-type Aj2 Ga As
In the cladding layer 10, the n-type GaAs waveguide layer 6
Since the low resistance region 14 is formed corresponding to one half, carriers are injected into only one half of the n'''' type GaAs waveguide 6 through the low resistance region 14.

Therefore, the n″″ type Ga that is not located below the low resistance region 14
No carriers are injected into the other half of the As waveguide layer 6. That is, the p-type AN Ga As cladding layer 10
The low resistance region 14 formed in this region limits carrier injection to a predetermined region, and this limitation increases carrier injection efficiency.

In this way, carriers are injected into only one half of the n-type GaAs waveguide layer 6 and confined there, so that the dielectric constant of that part decreases due to the plasma effect, and the refractive index decreases. Therefore, the n'''' type GaAs waveguide layer 6 is divided into two regions having mutually different refractive indexes.

Now, as shown in FIG. 2, the light incident from the input port 28 of the waveguide 24 passes through the Cr/Au electrode 20
When no voltage is applied between the Ge /Nl /Au electrode 22 , the light passes through the n″″ type GaAs waveguide layer 6 to the output boat 30 of the waveguide 24 . However, C
r/Au electrode 20 and Au Ge /Ni /Au electrode 2
When a predetermined voltage is applied between the n-type GaAs waveguide layer 24 and the refractive index of one half of the n-type GaAs waveguide layer 6, the refractive index change rate is expressed as the refractive index of the Δn1 waveguide 24.26. n, n
When the intersection angle between the boundary of two regions having different refractive indexes in the −-type GaAs waveguide layer 6 and the waveguide 24 is θ, the relationship of θ × 90°−5in−1 (1+Δn/n) is satisfied. The light incident from the input boat 28 of the waveguide 24 does not proceed to the output boat 30, but is totally reflected at the boundary between the two regions of the n''' type GaAs waveguide layer 6 having different refractive indexes, and the light enters the waveguide 24. 26 to the output boat 34. In this way, switching for the incident light is performed.

In the semiconductor switch according to the first embodiment, since the carrier concentration of the n'''' type GaAs waveguide layer 6 is as low as 1 x 1015cII+-3, free carrier absorption is suppressed to a low level, and optical absorption is suppressed. There is little loss due to Furthermore, since the carrier concentration of the p-type AN GaAs cladding layer 10 is as high as I x 1018 am-3, a plasma effect occurs throughout the carrier-injected n-type GaAs waveguide layer 6, and the carrier-injected n The refractive index decreases more rapidly in one half of the "" type GaAs waveguide layer 6. Even if the p+ type A, 11Ga'As cladding layer 10 has a high carrier content, it does not allow much light to enter, so there is little loss due to light absorption.

Further, the confinement of light in the lateral direction in the n-type GaAs waveguide layer 6 is not achieved by making the n-type GaAs waveguide layer 6 ridge-shaped, but by forming n-type GaAs on both sides.
This is achieved by sandwiching the n-type AfIGa As buried layer 8, which has a larger forbidden band than the As waveguide layer 6, that is, has a lower refractive index.
a The optical loss on the side wall of the As waveguide layer 6 is small.

Furthermore, since the plasma effect in which the refractive index is lowered by carrier injection is used, it is possible to perform a wide switching action on light having an energy smaller than the forbidden band width of the n'''' type GaAs waveguide layer 6.

In other words, wavelength dependence is eliminated. For example, in the first embodiment, since GaAs is used for the waveguide layer,
It can be used for light with a wavelength longer than the forbidden band width of 0.9 μm, and is 1.3 μm, which is normally used in optical communications.
It can sufficiently cover the m band.

Note that in the first embodiment, the waveguide layer 6 is formed of n-type GaAs with a low carrier concentration;
Its conductivity type is not limited to n-type, and may be formed of, for example, p'''' type GaAs or i-type GaAs with a low carrier concentration. However, since holes absorb more light than electrons, n-type is more desirable than p'''' type.

Further, the lower cladding layer 4 and the cladding layer 10 which sandwich the n-type GaAs waveguide layer 6 in a double heterostructure are a combination of n-type and p-type AI GaAs, respectively, but their conductivity types are different from each other. Replaced with p type A
D GaAs lower cladding layer and n+ type AfIGa
It may also be a combination of As cladding layers. Of course, in this case, the substrate 2 will be a p+ type GaAs substrate. Furthermore, in the first embodiment, the optical switch is composed of a GB As-based semiconductor, but for example, an I
An optical switch having a similar structure can be constructed using other semiconductors such as nGaAsP-based or InP-based.

Next, a semiconductor optical switch manufactured according to a second embodiment of the present invention will be described.

FIG. 3 is a sectional view showing the cross section of a semiconductor optical switch manufactured according to the second embodiment of the present invention, and FIG. 4 is a plan view showing the plane thereof.

In FIG. 3, for example, the carrier concentration is 2×10 18 cl.
On the l-3 p+ type GaAs substrate 42, a p-type AN
a As (x-0,1) lower cladding x
A l-x layer 44 is formed. This p type Aj! GaAs
The lower cladding layer 44 has a carrier concentration of 1×10 15
An n-type GaAs waveguide layer 46 of cIT+-3 is formed. Then, this n″″ type GaAs waveguide layer 4
An n-type AgGaxl-xAs(xmO,02) buried layer 48 having a carrier concentration of 1x10110l5 or less is formed on both sides of the layer 6. moreover,
On these n-type GaAs waveguide layer 46 and n-'' type AI GaAs buried layer 48, an n-type AΩ Ga
A s (xm0.1) cladding layer x1-x50 is formed. In this way, the n-type GaAs waveguide layer 46, which has a small forbidden band, is connected to the p+-type AN GaAs lower cladding layer 44, which has a larger forbidden band.
A so-called double heterostructure is formed which is sandwiched between the + type AJll GaAs cladding layer 50 from above and below. Then, on the n-type Aj)GaAs cladding layer 48, an n-type film with a carrier concentration lX1018-3 and a thickness of 0.5 μm is
A GaAs type 7-tact layer 52 is formed.

As shown in FIGS. 3 and 4, n-type AN G
In the a As cladding layer 50, a low resistance region 54 is formed in a region corresponding to the center of the n-type GaAs waveguide layer 6, to which zinc is added, for example, and the resistance is reduced. On the n-type GaAs contact layer 52, a silicon nitride film 56 with a thickness of 1000 nm and a silicon nitride film 56 with a thickness of 20 nm are formed.
00 silicon oxide film 58 is deposited. n+ type GaAs is passed through contact holes opened in the silicon nitride film 56 and silicon oxide film 58 above the low resistance region 54 of the n type AJ7 GaAs cladding layer 50.
Au Ge /Ni connected to contact layer 52
/Au electrode 60 is formed. Furthermore, p-type G
a A Cr/Au electrode 62 is also formed on the bottom surface of the As substrate 42 .

As shown in FIG. 4, in the n'''' type GaAs waveguide layer 46, two waveguides 64 having a waveguide width W are formed.
．． 66 intersect at an intersection angle of 2θ.

That is, they intersect the boundaries between the low-resistance region 54 and other relatively high-resistance regions in the n-type Ajl Ga As cladding layer 50 in opposite directions at a crossing angle θ. The waveguide 64 has an input port 68 and an output boat 70, and the waveguide 66 has an input port 72 and an output boat 74.

Next, the operation of the apparatus of the second embodiment described above will be explained.

The operation of the second embodiment is almost the same as that of the first embodiment, but since the low resistance region 54 is formed in the center of the n-type AllGaAs cladding layer 50, carriers are transferred to the n-type AfIGaAs. It is implanted only into the center of the n'' type GaAs waveguide 46 through the low resistance region 54 of the cladding layer 50. Therefore, carriers are not injected into both sides of the n-type GaAs waveguide layer 46 that are not located below the low resistance region 54. That is, n-type AfIGa
The low resistance region 54 formed in the As cladding layer 50 limits carrier injection to a predetermined region, and this limitation increases carrier injection efficiency. In the second embodiment, the region into which carriers are injected is more limited than in the first embodiment, so that the carrier injection efficiency is even higher. In this way, n″″ type Ga
Since carriers are injected only into the central portion of the As waveguide layer 46 and confined there, the dielectric constant of that portion decreases due to the plasma effect, and the refractive index decreases.

Therefore, the n-type GaAs waveguide layer 46 is divided into three regions having different refractive indexes.

Now, as shown in FIG. 4, the light incident from the input port 68 of the waveguide 64 and the input port 7 of the waveguide 66
The light incident from the Au Ge /N1/Au electrode 6
When no voltage is applied between 0 and the Cr/Au electrode 62, the light propagates through the n-type CaAs waveguide layer 46 to the output boat 70 of the waveguide 64 and the output boat 74 of the waveguide 66, respectively. do. However, Au Ge /Ni
When a predetermined voltage is applied between the /Au electrode 60 and the Cr/Au electrode 62 and the refractive index of the central part of the n″″ type GaAs waveguide layer 46 decreases, the incidence port of the waveguide 64 decreases. The light incident from 68 passes through the n-type GaAs waveguide layer 4
The light is totally reflected at the boundary between the two regions with different refractive indexes in the waveguide 66 and travels to the output boat 74 of the waveguide 66. Similarly, the light incident from the input boat 72 of the waveguide 66 is Proceed to the launch boat 70.

In this way, the semiconductor switch according to the second embodiment performs a switching action on incident light, whereas the semiconductor switch according to the first embodiment performs a switching action only on incident light from one direction. In contrast to the directional switch, this second embodiment is a so-called bidirectional switch that performs switching on incident light from two directions. All of the various effects of the first embodiment described above also exist in this second embodiment.

In the second embodiment, the waveguide layer 46 is formed of n-type GaAs with a low carrier concentration, but its conductivity type is not limited to the n-type. For example, the conductivity type is not limited to the n-type. It may be formed from type GaAs or i-type GaAs. However, since holes absorb more light than electrons, n'' type is more desirable than p'' type.

Further, the lower cladding layer 44 and the cladding layer 48 which sandwich the n-type GaAs waveguide layer 46 in a double heterostructure are a combination of p+ type and n+ type AN GaAs, respectively, but their conductivity types are exchanged. So, n+ type AN Ga As lower cladding layer and p+ type A, 1?
It may also be a combination of GaAs cladding layers. Furthermore, although the optical switch is constructed using a GaAs-based semiconductor, an optical switch having a similar structure can also be constructed using other semiconductors such as InGaAsP-based or InP-based semiconductors.

Next, a method for manufacturing a semiconductor optical switch according to a first embodiment of the present invention will be sequentially explained using FIG.

As a semiconductor substrate, for example, a carrier concentration of 2×10 18 CI
I+-3 n+ type GaAs substrate 2, carrier concentration 1×1018CI11″″3, thickness 2 μm (7) n
+ type Aj! Grow a GaAs (x,-0,1) lower cladding x 1-x layer 4. Then, on this n-type AI GaAs lower cladding layer 4, a carrier concentration of 1×1015cI1
1-3, grow an n-type Ga A3 epitaxial layer 5 with a thickness of 1 μm. Note that these n-type AN Ga
The As lower cladding layer 4 and the n'''' type GaAs epitaxial layer 5 are lattice-matched and laminated one after another by epitaxial growth using OMVPE (organic metal vapor phase epitaxial) method (see FIG. 5(a)). .

Next, a silicon nitride film 82 is deposited on the n-type GaAs epitaxial layer 5 using a thermal CVD (chemical vapor deposition) method. Subsequently, a resist 84 having a cross waveguide pattern having a waveguide width W and a cross angle 2θ is formed on the silicon nitride film 82 using photolithography (see FIG. 5(b)).

Using the RIE (reactive ion etching) method using the patterned resist 84 as a mask,
The silicon nitride film 82 and the n'''' type GaAs epitaxial layer 5 are etched until the top surface of the n+ type AD GaAs lower cladding layer 4 is reached. By this etching, an n-type GaAs waveguide layer 6 is formed on the n+-type Aff GaAs lower cladding layer 4.

Furthermore, the resist 84 is removed (see FIG. 5(C)).

Next, the silicon nitride film 8 that has already been patterned is
2 as a mask, the exposed n-type Ap GaAs
On the lower cladding layer 4, a carrier concentration of 1×10 15 CI
11-3 or less n-type AN Gax 1-
x As (x=0.02) A buried layer 8 is buried and grown. This n-type AN GaAs buried layer 8 is grown using a low-pressure OMVPE method, for example, under the conditions of a substrate temperature Tsub: 650° C. and an atmospheric pressure of 10 Torr, to the same thickness as the n'''' type GaAs waveguide layer 6. Do this until it becomes full. In this way, both sides of the n-type GaAs waveguide layer 6 are sandwiched between the n-type AfiGaAs buried layers 8 (see FIG. 5(d)).

Next, after removing the silicon nitride film 82, the n-type Ga
On the As waveguide layer 6 and the n'''' type AI GaAs buried layer 8, a p+ layer with a l8-3 carrier concentration of 1×10 cII+ and a thickness of 1 μm is formed using the OMVPE method.
Type A, l) GaAs (x-0,1) cladding layer x l-x 10 and carrier concentration l x 10 cm, thickness 0.5. c.
A p-type GaAs contact layer 12 of zm is sequentially grown. In this way, the forbidden band is small and Lsn-type Ga
The As waveguide layer 6 has a larger forbidden band than this n-type Ag
GaAs lower cladding layer 4 and p+ type AllGaAs
A so-called double heterostructure is formed between the cladding layer 10 and the cladding layer 10 from above and below (see FIG. 5(e)).

Next, heat C is applied onto the p+ type GaAs contact layer 12.
Using VD method, temperature 650°C, NH3: 5.6g/m
ins St H4 (4%)/N2 (96%): 2.
A silicon nitride film 16 with a thickness of 1000 Å is deposited under the condition of 9 fI/min. Next, BLAZE is applied on this silicon nitride film 16. Using CVD method, temperature 250℃,
50W 1 atm 0, 9 Torr, SIH (4%)/
N2 (96%): 20sccm, N20: 30
A silicon oxide film 18 with a thickness of 2000 mm is deposited under the condition of 0 sec (see FIG. 5(f)).

Next, a resist 86 is applied to the entire surface, and an opening is opened in the resist 86 at a location corresponding to a half of the n'''' type GaAs waveguide layer 6 using a photolithography technique. Using the patterned resist 86 as a mask, the silicon oxide film 18 and the silicon nitride film 16 are etched using, for example, RIE using CF4.
Open the window (see Figure 5 (g)).

Next, after removing the resist 86, this sample was
Vacuum seal in a quartz ampoule with nA S2. Then, using the silicon oxide film 18 and the silicon nitride film 16, which have openings corresponding to a portion of the p-type A9 GaAs cladding layer 8, as masks, zinc is diffused at a temperature of 630°C. This zinc diffusion is of type G
a P-type A, Q slightly above the top surface of the As waveguide layer 6
It is made to reach into the GaAs cladding layer 10. The reason why zinc diffusion is prevented from reaching the upper surface of the n-type GaAs waveguide layer 6 in this way is to prevent zinc from being diffused into the n-type GaAs waveguide layer 6 by heat treatment in a later step. It's for a reason. In this way, zinc is added to the p+ type A ill GaAs cladding layer 10 in a region corresponding to a part of the n-type GaAs waveguide layer 6, resulting in a low resistance region having a relatively low resistance. 14 (see FIG. 5(h)).

Next, a Cr/Au electrode 20 is formed on the upper surface and connected to the p-type GaAs contact layer 12 through contact holes already made in the silicon oxide film 18 and silicon nitride film 16. In addition, an n-type GaAs substrate 2
An Au Ge /Ni/Au electrode 22 is also formed on the bottom surface (see FIG. 5(i)).

Although not shown, two waveguides having a waveguide width W and intersecting at an intersection angle 2θ are connected to the n-type GaAs waveguide layer 6. And these waveguides are p+ type Aj7
They intersect the boundaries between the low-resistance region 14 and other relatively high-resistance regions in the GaAs cladding layer 8 in opposite directions at intersecting angles θ.

Finally, the end face is folded in five lengths, and the waveguide chip is cut out. In this way, the semiconductor optical switch according to the first embodiment is manufactured.

Note that in patterning the resist 86, instead of opening the resist 86 at a location corresponding to a part of the n'''' type GaAs waveguide layer 6 as described above,
a The photoresist 86 is opened at a location corresponding to the center of the As waveguide layer 6, and the silicon oxide film 18 and the silicon nitride film 16 are etched using the patterned resist 86 as a mask, and the p-type is etched. Zinc is diffused using the silicon oxide film 18 and the silicon nitride film 16, which are opened at a location corresponding to the center of the AfIGaAs cladding layer 10, as a mask to form a p+ type A.
By forming a low resistance region in the center of the IGaAs cladding layer 8, a structure similar to that of the second embodiment can be obtained, and a bidirectional semiconductor optical switch can be manufactured.

Further, although zinc is diffused into a portion of the p-type AlGaAs cladding layer 10 to form the low resistance region 14, for example, beryllium (Be) may be used instead of zinc.

Further, on the n+ type GaAs substrate 2, an n type Aj7Ga
The As lower cladding layer 4, the n'''' type GaAs waveguide layer 6, the p+ type Ajl GaAs cladding layer 10, and the p+ type GaAs layer contact layer 12 are formed respectively, but this is not a combination. , n-type Ga
The conductivity types of the substrates and each layer sandwiching the As waveguide layer 6 are exchanged, and a p+ type GaAs substrate is formed on the p+ type GaAs substrate.
a As lower cladding layer, n-type GaAs waveguide layer 6
, n-type AfIGa As cladding layer, and n+-type G
It may be formed in a combination of a As layer contact layer. However, in this case, n+ type AN Ga
The impurity implanted to form a low resistance region in a part of the As cladding layer must be, for example, silicon (St).

In either case, the conductivity type of the waveguide layer 6 is not limited to n-type, but is, for example, p-type Ga with a low carrier concentration.
It may be As or ■-shaped GaAs.

However, since holes absorb more light than electrons, p
The n″″ type is more desirable than the − type.

〔Effect of the invention〕

As described above in detail, according to the device manufactured according to the present invention, the waveguide layer is formed between the semiconductor substrate of the first conductivity type and the cladding layer of the second conductivity type, which has a forbidden band larger than the forbidden band of the waveguide layer. Due to the sandwiched double heterostructure, a low refraction region is generated in a part of the waveguide layer due to the plasma effect, and the incident light is totally reflected at the boundary without depending on its wavelength. Further, the waveguide layer is a low carrier layer sandwiched between a semiconductor substrate with a high carrier concentration and a cladding layer, and is sandwiched on both sides by low refractive regions, thereby reducing loss.

As a result, optical switching with a high extinction ratio is performed, so that optical switching with excellent low loss characteristics and without wavelength dependence can be performed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the cross section of a semiconductor optical switch manufactured according to the first embodiment of the present invention, FIG. 2 is a plan view showing the plane thereof, and FIG. Sectional view showing the cross section of the semiconductor optical switch manufactured according to the example, No. 4
The figure is a plan view showing the plane, and FIG. 5 is the first embodiment of the present invention.
FIG. 3 is a process diagram showing a method for manufacturing a semiconductor optical switch according to an embodiment of the present invention. 2-n-type GaAs substrate, 4...n-type AN GaAs lower cladding layer, 5...
・・n″″ type GaAs epitaxial layer, 6.46・
n-type GaAs waveguide layer, 8.48 n-type AI G
a As buried layer, 10 ・p type AN Ga A
s cladding layer, 12... p-type GaAs layer contact layer, 14.54... low resistance region, 16.56.82... silicon nitride film (S13N4 film), 18.58... silicon oxide Membrane (S102 membrane), 20
．． 62--Cr/Au electrode, 22.60...Au Ge/Nl/Au electrode, 2
4.26.64.66... Waveguide, 28.32. ．． 6
8.72...Injection port, 30.34, 70.74.
・・Emission boat, 42 ・P type Ga As substrate, 44 ・・P type Ajl Ga As lower cladding layer,
50 ・n-type AN Ga As cladding layer, 52-
n W: 1 GaAs layer contact layer, 84.86...
・Resist. Patent Applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney Yoshiki Hase Li Cross-sectional view of the first embodiment Figure 1 Plan view of the first embodiment Figure 2 Figure 3 Plan view of the second embodiment Figure 4 Figure 5 (1) Figure 5 (2)

Claims (1)

[Claims] 1. A first step of growing an epitaxial layer having a forbidden band smaller than that of the semiconductor substrate and a lower carrier concentration on a semiconductor substrate of a first conductivity type, and selectively growing the epitaxial layer. a second step of etching to form a waveguide layer made of the epitaxial layer; and a third step of forming a buried layer on both sides of the waveguide layer, the forbidden band of which is larger than that of the waveguide layer. and a second layer having a forbidden band larger than that of the waveguide layer and a higher carrier concentration on the waveguide layer and the buried layer.
a fourth step of forming a conductive type cladding layer; a fifth step of forming a low resistance region in a part of the cladding layer; and forming a first electrode on the low resistance region of the cladding layer. A method for manufacturing a semiconductor optical switch, further comprising a sixth step of forming a second electrode on the bottom surface of the semiconductor substrate. 2. The method of manufacturing a semiconductor optical switch according to claim 1, wherein the low resistance region is formed corresponding to one half of the waveguide layer. 3. The method of manufacturing a semiconductor optical switch according to claim 1, wherein the low resistance region is formed corresponding to a central portion of the waveguide layer.