JPH02228635A - Semiconductor optical switch and its production - Google Patents

Abstract

PURPOSE:To reduce the loss by forming a waveguide layer as a low carrier layer interposed between a semiconductor substrate having a high carrier concentration and a clad layer and surrounding the waveguide layer with a low- refractive index layer on both sides. CONSTITUTION:A waveguide layer 6 is vertically interposed between a lower clad layer 4a of first conductive type and an upper clad layer 8a of second conductive type, which have an inhibition zone larger than that of the layer 6, to have a double hetero structure. A low-refractive index area is generated in a part of the waveguide layer 6 by the plasma effect dependent upon this structure, and incident light is totally reflected on the boundary independently of the wavelength. The waveguide layer 6 is the low carrier layer interposed between upper and lower clad layers 8a and 4a and is surrounded with the low-refractive index area on both sides, and the carrier injection area is limited. Thus, a semiconductor switch is obtained which has the loss reduced and performs optical switching of high extinction ratio and is independent of the wavelength.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor optical switch, and particularly to a semiconductor optical switch that is composed of a semiconductor optical waveguide layer and that switches optical paths essential for optical communication and optical information processing. Regarding optical switches.

[Conventional technology]

Conventional optical switches use polarization of light due to the acousto-optic effect of the optical transmission medium, polarization of light due to the electro-optic effect of the medium, and electro-optic coupling coefficients of directional couplers. There are those that vary depending on the effect, and those that combine a directional coupler and an optical phase modulator. However, none of these waveguides satisfy all the basic characteristics of a waveguide switch, such as low loss characteristics, low noise characteristics, and high speed. As a solution to these problems,
Inject carriers into the waveguide layer to lower its refractive index,
Proposals have been made to utilize this change in refractive index in optical switches.

For example, Japanese Patent Application Publication No. 1983-1999. In the semiconductor optical switch shown in No. 173519, non-doped InGaAs
The P optical waveguide layer has a so-called double hetero structure sandwiched between an n-type 1nP substrate with a larger forbidden band and an n-type 1nP grading layer, and the p-n junction of this double heterostructure has a forward direction. A current is applied to inject carriers into the InGaAsP optical waveguide layer. The refractive index is lowered by the plasma effect in this InGaAsP optical waveguide layer. However, the above JP-A-60
In the semiconductor optical switch of No. 173519, the loss has not yet been sufficiently reduced, and the applications are also limited.

Furthermore, for example, in a semiconductor optical switch shown in Japanese Patent Application Laid-Open No. 60-134219, an InP substrate and an InP
nGaAs P layer and InP layered in order on the substrate
It has a superlattice layer consisting of layers and an InP grading layer on the superlattice layer, and carriers are injected by passing a current through the superlattice layer. Then, the absorption edge wavelength of light is shifted by the band filling effect in this superlattice layer. Thus, Kramers Kronig (Kr.
The refractive index in the vicinity of the absorption edge wavelength is lowered due to the relationship: aIlers-Kronlg). However, the above-mentioned Japanese Patent Publication No. 6
In the semiconductor optical switch of No. 0-134219, the loss has not yet been sufficiently improved, and furthermore, the wavelength dependence that the applicable wavelength of light is limited to approximately match the bandgap energy Eg of the semiconductor is a problem. Yes, and its uses were limited.

[Problem to be solved by the invention]

As described above, conventional semiconductor optical switches do not fully satisfy low loss characteristics, and some have wavelength dependence, among other problems.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor optical switch with improved low loss characteristics and no wavelength dependence, and a method for manufacturing the semiconductor optical switch with high yield.

[Means to solve the problem]

A semiconductor optical switch according to the present invention includes a first conductivity type semiconductor substrate having a first electrode formed on one surface, a high resistance lower cladding layer formed on the other surface of the semiconductor substrate, and the lower cladding layer. an upper cladding portion of a first conductivity type formed by ion implantation within the cladding layer; a waveguide layer formed on the lower cladding layer and having a forbidden band smaller than that of the lower cladding portion and having a lower carrier concentration; a high-resistance upper cladding layer formed on the waveguide layer; and a high-resistance upper cladding layer formed in the upper cladding layer by ion implantation, located above the lower cladding part, and having a forbidden band larger than that of the waveguide layer and a carrier concentration. an upper cladding portion of a second conductivity type with a high conductivity, a buried layer provided on both sides of the waveguide layer and the upper cladding layer, and a buried layer having a forbidden band larger than that of the waveguide layer, and an upper cladding portion of the upper cladding layer. The second formed in
carriers are injected into a predetermined region sandwiched between the upper and lower cladding portions of the waveguide layer by a voltage applied between the electrode, the first electrode, and the second electrode. shall be.

Furthermore, the method for manufacturing a semiconductor optical switch of the present invention includes a first step of forming a high-resistance first epitaxial layer to serve as a lower cladding layer on a first conductivity type semiconductor substrate; A second step of implanting ions into a predetermined region to form a lower cladding portion of the first conductivity type, and forming a forbidden band g? on the first epitaxial layer. a third step of growing a second epitaxial layer that is smaller than that of the lower cladding part and has a lower carrier concentration; and a fourth step of forming a high-resistance upper cladding layer on the second epitaxial layer. , implanting ions into a region above the lower cladding in the upper cladding layer to form an upper cladding of a second conductivity type having a forbidden band larger than that of the second epitaxial layer and a higher carrier concentration; Step 5 and selectively etching the second epitaxial layer and the high-resistance upper cladding layer to form a waveguide layer made of the second epitaxial layer and an upper cladding region on the waveguide layer, respectively. a sixth step, on both sides of the waveguide layer and the upper cladding region;
a seventh step of forming a buried layer whose forbidden band is larger than that of the waveguide layer; forming a first electrode on the upper cladding part of the upper cladding layer; and forming a second electrode on the bottom surface of the semiconductor substrate. and an eighth step of forming an electrode.

[Effect]

According to the semiconductor optical switch of the present invention, the waveguide layer is
+? The double hetero structure is sandwiched from above and below by a lower cladding part of the first conductivity type and an upper cladding part of the second conductivity type, which have a forbidden zone larger than the tourniquet, and the plasma effect generated from this structure causes the waveguide layer to A low refraction area is created in a part of the area, and the incident light is totally reflected at the boundary without depending on its wavelength. Further, the waveguide layer is a low carrier layer sandwiched between the upper and lower cladding parts, and both sides are sandwiched by low refraction regions to limit the carrier injection region, thereby reducing loss. As a result, optical switching with a high extinction ratio is performed.

〔Example〕

Hereinafter, the present invention will be specifically described based on illustrated embodiments.

FIG. 1 is a sectional view showing a cross section of a semiconductor optical switch according to a first embodiment of the present invention, and FIG. 2 is a plan view showing a plane of the semiconductor optical switch shown in FIG.

In FIG. 1, for example, the carrier concentration is 2×1018,
-3 n+ type GaAs substrate 2, 1 type Ag Ga
As (x-0,1) lower cladding X
1-x layer 4 is formed. This i-type AgGHAs on the lower cladding layer 4 has a carrier concentration IXIO15cm=n
- type GaAs waveguide layer 6 is formed. Then, on this n-type GaAs waveguide layer 6, an i-type AII G
a As (x-0,1) cladding X l-
An n-type AN layer 8'' is formed in this i-type AgGaAs lower cladding layer 4 by Si ion implantation.
A GaAs lower grid portion 4a is formed as shown in FIG. Furthermore, a p-type AlGaAs upper cladding portion 8a is formed in the i-type AllGaAs upper cladding layer 8 by Be ion implantation. In this way,
The n-type GaAs waveguide layer 6, which has a small forbidden band, is sandwiched from above and below by the n+-type AllGaAs lower quad portion 4a, which has a larger forbidden band, and the p-type AΩGaAs2571 portion 8a, into a so-called double layer. A terrorist structure is forming.

The i-type AΩGaAs cladding layer 8 has a carrier concentration of 1
×1017cln-3 p-type GaAs cap layer 1
0 is formed. In addition, the i-type GaAs waveguide layer 6
, i+ type AI Ga As cladding layer 8 and p type Ga
On both sides of the As cap layer 10, i-type Aρ Ga
An As buried layer 12 is formed.

As shown in FIGS. 1 and 2, i-type AN Ga
A double heterostructure region sandwiched between the upper and lower cladding parts 4a and 8a is formed in one half of the As upper and lower cladding layers 6 and 8. In addition, p-type Ga
A Cr/Au m pole 20 is formed on the As cap layer 10 and the i-type Aff GaAs buried layer 12. Furthermore, an AuGc/Nl/Au electrode 22 is also formed on the bottom surface of the n+ type GaAs substrate 2.

As shown in FIG. 2, an n-type GaAs waveguide layer 6
In , two waveguides 24.2 having a waveguide width W
6 intersect at an intersection angle of 2θ. That is, n-type Ga
Upper and lower cladding parts 4a and 8a of As waveguide layer 6
The boundary between the region sandwiched between the regions and the region not sandwiched between these regions intersects in opposite directions at a crossing angle θ. The waveguide 24 has an input boat 28 and an output boat 30, and the waveguide 26 has an input boat 32 and an output boat 34.

Next, the operation of the apparatus of the first embodiment will be explained.

A predetermined voltage is applied between the Cr/Au electrode 20 and the Au Ge /Nl /Au electrode 22 to form a p+ type AlGaAs
When current is passed in the forward direction through the p-n junction of the double heterostructure consisting of the 2571 part 8a, the n-type GaAs waveguide layer 6, and the n+-type A, Q GaAs lower shield part 4a, carriers is injected.

Since the p+ type Ap Ga As upper cladding part 8a and the n+ type A, 9 Ga As lower cladding part 4a are formed in one half of the waveguide layer 6, the upper and lower cladding parts 4a, The carriers are injected into only one half of the n'''' type GaAs waveguide 6 through the channel 8a. Therefore, the upper and lower cladding parts 4a.

n-type GaAs waveguide layer 6 at a position not sandwiched by 8a
No carrier is injected into one half of the cell. That is, i'
Only in the region of the waveguide layer 6 sandwiched between the upper cladding part 8a formed in the JIA I GaAs cladding layer 8 and the lower cladding part 4a formed in the lower cladding layer 4,
Carrier injection is restricted, and this restriction increases carrier injection efficiency.

In this way, carriers are injected into only one half of the n-type GaAs waveguide layer 6 and confined there, so that the dielectric constant of that part is lowered by the plasma effect, and the refractive index is lowered. Therefore, the n-'' type GaAs waveguide layer 6 is divided into two regions having mutually different refractive indexes.

Now, as shown in FIG. 2, the light incident from the input boat 28 of the waveguide 24 passes through the Cr/Au electrode 20 and
When no voltage is applied between the Ge 2 /Nl 2 /Au electrode 22 , the light passes through the n-type GaAs waveguide layer 6 to the output boat 30 of the waveguide 24 . However, Cr
/A U electrode 20 and Au Gc /N1 /Au
A predetermined voltage is applied between the electrode 22 and the n″″ type Ga
When the refractive index of the negative half of the As waveguide layer 6 decreases, the refractive index change rate is determined by Δn1, the refractive index of the waveguide 24. The intersection angle between the boundary of two regions with different ratios and the waveguide 24 is θ
Then, when the relationship of θ 90°−5in”−1 (1+Δn/n) is satisfied, the light incident from the input boat 28 of the waveguide 24 does not proceed to the output boat 30, and is an n-type Ga
The light is totally reflected at the boundary between two regions of the As waveguide layer 6 having different refractive indexes, and travels to the output boat 34 of the waveguide 26 . In this way, switching for incident light is performed.

In the semiconductor switch manufactured according to the first embodiment, the carrier concentration of the n-type GaAs waveguide layer 6 is 1. Since it is as low as X 10 'cm-'', free carrier absorption is suppressed to a low level, and loss due to light absorption is small.
Since the carrier concentration of n-
A plasma effect occurs throughout the GaAs waveguide layer 6,
The refractive index decreases more rapidly in one half of the n-type GaAs waveguide layer 6 into which carriers are injected. and,
Even if the p-type AgGaAs cladding 8a has a high carrier content, there is little loss due to light absorption because there is not much light.

Further, the confinement of light in the lateral direction in the n-type GaAs waveguide layer 6 is not achieved by making the n-type GaAs waveguide layer 6 ridge-shaped, but by forming n-type GaAs on both sides.
This is achieved by sandwiching the i-type Al)GaAs buried layers 12, which have a larger forbidden band than the As waveguide layer 6 and have a low refractive index. Light loss is low.

Furthermore, since the plasma effect in which the refractive index decreases due to carrier injection is used, the n-type GaAs waveguide layer 6
This makes it possible to perform a wide switching action on light with energy smaller than the forbidden band width.

In other words, wavelength dependence is eliminated. For example, in the first embodiment, since GaAs is used for the waveguide layer,
It can be used for light with a wavelength longer than the forbidden band width of 0.9 μm, and is 1.3 μm, which is normally used in optical communications.
It can sufficiently cover the m band.

In the device according to the first embodiment, the waveguide layer 6 is formed of n-type GaAs with a low carrier concentration, but its conductivity type is not limited to the n-type. It may be formed from p-type GaAs or l-type GaAs. However, since holes absorb more light than electrons, n type is more desirable than p'' type.

Further, the lower cladding part 4a and the upper cladding layer 8a which sandwich the n-type GaAs waveguide layer 6 in a double heterostructure are a combination of n-type and p-type AgGaAs, respectively, but their conductivity types are different. Switched places, p
Type AN Ga As lower cladding part and n+ type A, l
! It may also be a combination of a GaAs upper cladding part. Of course, in this case, the substrate 2 will be a p+ type GaAs substrate. Furthermore, in the first embodiment, G
Although the optical switch is constructed using an As-based semiconductor, an optical switch having a similar structure can also be constructed using other semiconductors such as InGaAsP-based or InP-based semiconductors.

Next, a semiconductor optical switch according to a second embodiment of the present invention will be explained.

FIG. 3 is a sectional view showing the cross section of the semiconductor optical switch of the second embodiment, and FIG. 4 is a plan view showing the plane thereof.

In FIG. 3, for example, the carrier concentration is 2×10i8 mark −
On the p-type GaAs substrate 42 of No. 3, the i-type Aj7
Ga As (x-0,1) lower cladding x
A l-X layer 44 is formed. This i type AgxGa A
An n-type AfIGaAs lower cladding portion 44a is formed in the center of the s(x-0,1) lower cladding layer by implanting St ions.

An n- type GaAs waveguide layer 46 having a carrier concentration I x 1015cTn-3 is formed on the n+-type AN GaAs lower quad portion 44a. And this n
- On the GaAs waveguide layer 46, an i-type Aj7xGa
As (x=0.1) upper cladding layer 481-
x is formed. This i type AN Ga Ax
l-X 5 (x-0, 1) Be in the center of the upper cladding layer 48
An upper cladding portion 48a of p-type AgGaAs is formed by ion implantation. In this way, the n"" type GaAs waveguide layer 46 with a small forbidden band is replaced with the n type AjJ GaAs lower cradle layer 4 with a larger forbidden band.
4a and the p-type AI Ga As upper quad portion 48a are sandwiched from above and below, forming a so-called double heterostructure.

A p-type GaAs cap layer 50 having a carrier concentration of 1×10 cffl and a thickness of 1 μm is formed on the p+-type AN GaAs cladding layer 48a. In addition, an n-type GaAs waveguide layer 46, a p-type All Ga
As cladding 48a1 and p-type GaAs waveguide layer 5
1-type Ajll GaAs buried layers 52 on both sides of the
is formed. Furthermore, a p-type GaAs cap layer 50
And on the top of the i-type AM GaAs buried layer 52, n
Au Ge type connected to the Ga As cap layer 50
/N1 /Au electrode 60 is formed. Furthermore, n
Cr/Auff1 is also formed on the bottom surface of the + type GaAs substrate 42.
A pole 62 is formed.

As shown in FIG. 4, an n-type GaAs waveguide layer 4
In 6, two waveguides 64.6 each have a waveguide width W.
66 intersect at an intersection angle of 2θ.

That is, the upper cladding part 48a and the lower cladding part 4
The waveguide layer 46 intersects the boundary between the waveguide layer 46 sandwiched between the waveguide layers 4a and the region not sandwiched therebetween in opposite directions at a crossing angle θ. The waveguide 64 has an input port 68 and an output port 70, and the waveguide 66 has an input port 72 and an output port 74.

Next, the operation of the device of the second embodiment will be explained.

The operation of the device of this second embodiment is almost the same as that of the first embodiment, except that
s An upper cladding part 48a is provided in the center of the upper cladding layer 48.
On the other hand, since a lower cladding part 44a is formed in the center of the i-type AfIGaAs lower cladding layer 44, carriers are formed in the n-type AD GaAs2911 part 48.
a, and is injected only into the center of the n-type GaAs waveguide 46.

Furthermore, the lower cladding portion 44a formed in the lower cladding layer 44 limits carrier injection to only the central portion of the waveguide layer 46. Therefore, n-type Ga A that is not sandwiched between the upper cladding part 48a and the upper cladding part 44a
No carriers are injected into one half of the s-waveguide layer 46.

In other words, the upper cladding part 48a formed in the l-type AρGaAs cladding layer 48 and the i-type ANGaAs
The lower cladding portion 44a formed in the cladding layer 44 limits carrier injection to a predetermined region, and this restriction increases carrier injection efficiency. In the second embodiment, the region into which carriers are injected is more limited than in the first embodiment, so that the carrier injection efficiency is even higher.

In this way, carriers are injected only into the central part of the low-type GaAs waveguide layer 46 and are confined there, so that the dielectric constant of that part decreases due to the plasma effect, and the refractive index decreases. Follow.

The n-type aAs waveguide layer 46 is divided into three regions having different refractive indexes.

Now, as shown in FIG. 4, the light incident from the input boat 68 of the waveguide 64 and the input port 7 of the waveguide 66
The light incident from the Au Ge /Nl/Au electrode 6
When no voltage is applied between 0 and the Cr/Au electrode 62, the light propagates through the n-type GaAs waveguide layer 46 to the output boat 70 of the waveguide 64 and the output boat 74 of the waveguide 66, respectively. do. However, Au Ge/N
When a predetermined voltage is applied between the i/Au electrode 60 and the Cr/Au electrode 62 and the refractive index of the central part of the n-type GaAs waveguide layer 46 decreases, the input port of the waveguide 64 The light incident from the waveguide 68 is totally reflected at the boundary between the two regions of the n'''' type GaAs waveguide layer 46 having different refractive indexes, and travels to the output port 74 of the waveguide 66, and in the same way, the light enters the waveguide 66. The light incident from the input boat 72 of the waveguide 64 travels to the output boat 70 of the waveguide 64 .

In this way, the semiconductor switch according to the second embodiment performs a switching action on incident light, whereas the semiconductor switch according to the first embodiment performs a switching action only on incident light from one direction. In contrast to the directional switch, this second embodiment is a so-called bidirectional switch that performs a switching action on incident light from two directions. All of the various effects of the first embodiment described above also exist in this second embodiment.

In the second embodiment, the waveguide layer 46 is formed of n'''' type GaAs with a low carrier concentration, but its conductivity type is not limited to the n'''' type. It may be formed from p'' type GaAs or l type GaAs. However, since holes absorb more light than electrons, n'''' type is more desirable than p-type.

In addition, a lower cladding part 44a and an upper cladding part 4 sandwiching the n-type GaAs waveguide layer 46 into a double heterostructure.
8 are p-type and n-type A, Q Ga As, respectively.
However, these conductivity types are swapped, and the n-type Al)GaAs lower cladding and the p
It may also be a combination of type AI Ga As upper cladding. Furthermore, although the optical switch is constructed using a GaAs-based semiconductor, an optical switch having a similar structure can also be constructed using other semiconductors such as InGaAsP-based or InP-based semiconductors.

Next, a method for manufacturing a semiconductor optical switch according to a first embodiment of the present invention will be sequentially explained using FIG.

For example, the semiconductor substrate has a carrier concentration of 2×10 18 cl.
On the I+-3 n+ type Ga As substrate 2, a high resistance i-type/l Ga As (x-0,1) lower layer x
1-x Grow rad layer 4. Next, the lower cladding layer 4 is covered with a mask layer except for a portion corresponding to the lower part of the upper cladding that will be formed later, and Si ions are heated at 400K.
Ions were implanted at a concentration of 1×10L3/cm2 at eV,
A lower cladding portion 4a of n mAlGaAs is formed (see FIG. 5(a)).

Next, on this i-type AlGaAs lower cladding layer 4, an n-type Ga A layer with a carrier concentration of 1×10 cm is applied.
s epitaxial layer 5 is grown. Furthermore, this n′″
i type Ai) on the type GaAs epitaxial layer 5
GaAs (x-0,1) layer 7 is formed x
Lengthen l-x. And then this i type Aj? A mask layer was formed except for the upper part of the GaAs layer (the part corresponding to the upper part of the lower cladding part 4a formed earlier), and Be ions were ionized at a concentration of 400 K e Vte I X 1013a/cj. An upper cladding part 8a of p-type AD GaAs is formed by implantation (see FIG. 5(b)).

In this way, the n'''' type GaAs epitaxial layer 5 with a small forbidden band becomes the n+ type A with a larger forbidden band.
j) Ga As lower grid part 4a and p-type AN Ga
A so-called double heterostructure is formed between the Astuk 9 and the As 18a from above and below.

Then, on the l-type AN GaAs epitaxial layer 7, a p-type G layer with a carrier concentration I
An aAs epitaxial layer 9 is grown. Note that these i-type Ail Ga As lower cladding layer 4, n-type Qa
As epitaxial layer 5. The 1-type AN GaAs epitaxial layer 7 and the p-type GaAs epitaxial layer 9 are lattice-matched and stacked one by one by epitaxial growth using OMVPE (organic metal vapor phase epitaxial) method ( (See Figure 5(c)).

Next, heat C is applied onto the p-type GaAs epitaxial layer 9.
Silicon nitride film 8 is grown using the VD (chemical vapor deposition) method.
2 (see FIG. 5(d)). Subsequently, a resist 84 having a cross waveguide pattern having a waveguide width W1 and a cross angle 2θ is formed on the silicon nitride film 82 using photolithography (see FIG. 5(e)).

After removing the silicon nitride film 82 by etching using the patterned resist 84 as a mask, the p-type GaAs epitaxial layer 9 and the i+-type AN GaAs epitaxial layer 7 are further etched using a dry etching method.
Then, the i'''' type GaAs epitaxial layer 5 is etched until it reaches the upper surface of the n type AI GaAs lower cladding layer 4.

The dry etching conditions are, for example, 80g3:1
0secI, 1. 5 P a, 0. 5W/
Let it be cm2.

By this dry etching, l-type AllGaAs
n-type GaAs waveguide layer 6 on lower cladding layer 4;
As cladding layer 8, and this p-type AJ7 Ga
A p-type GaAs cap layer 10 is formed on each of the As cladding layers 8. After that, the resist 84 is removed (
(See Figure 5(d)).

Next, the silicon nitride film 8 that has already been patterned is
2 as a mask, the exposed n-type A, T! Ga
An i-type AlXGaAs buried layer 12 is buried and grown on the As lower cladding layer 4. The i-type A, Q Ga As buried layer 12 is grown using the OMVPE method, for example, at a substrate temperature Ts.
ub: p under the conditions of 650°C and atmospheric pressure 10 Torr
This process is continued until the height of the upper surface of the GaAs type contact layer 10 is reached. In this way, the n-type GaAs waveguide layer 6,
i-type AI Ga As cladding layer 8 and p-type Ga
Both sides of the As cap layer 10 are made of i″″ type AΩGaAs.
It is sandwiched between the buried layers 12 (Fig. 5(g)
reference).

Next, the silicon nitride VI 82 is removed, and the p-type GaAs waveguide layer 10 and the i-type AI GaAs embedding layer 12 are
A Cr/Au electrode 20 is formed on the top surface, and an n+ type Ga
An Au Ge/Nl/Au electrode 22 is also formed on the bottom surface of the As u plate 2 (see FIG. 5(h)).

Although not shown, the waveguide has a width W and a crossing angle 2θ.
Two waveguides intersecting each other are connected to an n-type GaAs waveguide layer 6. And these two waveguides are i-type A
f) In opposite directions with respect to the boundary between the region sandwiched between the upper cladding part 8a of the GaAs upper cladding layer 8 and the lower cladding part 4a of the i-type AN GaAs lower cladding layer 4 and the other region. They intersect at an intersection angle θ.

Finally, the end face is folded to a length of 51, and a waveguide chip is cut out. In this way, the semiconductor optical switch according to the first embodiment is manufactured.

As described above, the i-type AD GaAs cladding layer 8 and i
Rather than forming the upper cladding part 8a and the lower cladding part 4a at locations corresponding to one half of the type AlGaAs cladding layer 4, the i-type A, pGaAs cladding layer 8 and the i-type AN GaAs cladding layer 4 are If upper and lower cladding parts 4a and 8a are formed in the central part by ion implantation, a structure similar to that of the second embodiment can be obtained, and a bidirectional semiconductor-based switch can be manufactured.

Further, on the n+ type GaAs substrate 2, an n+ type AlGaA
s, lower cladding part 4a, n-type GaAs waveguide layer 6
, p+ type AN Ga As2971 part 8a.

and a p-type GaAs layer cap layer 1o, but this combination is not used; instead, an n-type GaAs layer is formed.
The conductivity types of the substrates and each layer sandwiching the As waveguide layer 6 are exchanged, so that p" MAD is formed on the p" type GaAs substrate.
Ga As lower cladding, low type GaAs waveguide layer 6, n+ type AI GaAs upper cladding, and n
A GaAs type cap layer may be formed in combination. However, in this case, i-type A, 1) Ga
The ions implanted into the As cladding layer 4.8 must be replaced.

In either case, the conductivity type of the waveguide layer 6 is not limited to the low type, but is, for example, a p-type Ga with a low carrier t of 6 degrees.
It may be As or i-type GaAs.

However, since holes absorb more light than electrons, p
The n-type is more desirable than the -type.

〔Effect of the invention〕

As described above in detail, according to the optical switch manufactured according to the present invention, the waveguide layer has a semiconductor substrate of the first conductivity type having a forbidden band larger than the forbidden band thereof, and a cladding portion of the second conductivity type. By forming a double heterostructure sandwiched between the top and bottom, a low refraction region is created in a part of the waveguide layer due to the plasma effect, and incident light is totally reflected at the boundary without depending on its wavelength. . Further, the waveguide layer is a low carrier layer sandwiched between a semiconductor substrate with a high carrier concentration and a cladding layer, and is sandwiched on both sides by low refractive regions, thereby reducing loss.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the cross section of a semiconductor optical switch manufactured according to the first embodiment of the present invention, FIG. 2 is a plan view showing the plane thereof, and FIG. Sectional view showing the cross section of the semiconductor optical switch manufactured according to the example, No. 4
The figure is a plan view showing the plane, and FIG. 5 is the first embodiment of the present invention.
FIG. 3 is a process diagram showing a method for manufacturing a semiconductor optical switch according to an embodiment of the present invention. 2-n type GaAs substrate, 4... SI type A, 12 GaAs lower cladding layer,
4a... Lower cladding part of n-type Ap Ga As, 5
...n-type GaAs epitaxial layer, 6.46-
n-type GaAs waveguide layer, 7...SI type AN Ga
As epitaxial layer, 8 ・SI type AN Ga
As cladding layer, 8a... p-type Ai) GaAs upper cladding part, 9... p-type GaAs epitaxial layer, 10... p-type Cla AS layer cap layer, 12.
52-3 I) MARGa As buried layer, 82...
・Silicon nitride film (Si3N4 film), 20.62...C
r/Au electrode, 22, 60-=AuGe/Ni/
A u electrode, 24.26, 64.66... waveguide, 2
8.32, 68.72... - Incoming boat.

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate having a first electrode formed on one surface; a high-resistance lower cladding layer formed on the other surface of the semiconductor substrate; and the lower cladding layer. a waveguide layer formed on the lower cladding layer and having a forbidden band smaller than that of the lower cladding layer and a lower carrier concentration; a high-resistance upper cladding layer formed on the waveguide layer; and a high-resistance upper cladding layer formed by ion implantation into the upper cladding layer, located above the lower cladding part, having a forbidden band larger than that of the waveguide layer and having a carrier concentration. an upper cladding portion of a second conductivity type with a high conductivity; a buried layer provided on both sides of the waveguide layer and the upper cladding layer and having a forbidden band larger than that of the waveguide layer; and an upper cladding portion of the upper cladding layer. A voltage is applied between the second electrode formed on the waveguide layer, the first electrode, and the second electrode to cause carriers to be applied to a predetermined region sandwiched between the upper and lower cladding portions of the waveguide layer. A semiconductor optical switch characterized by being injected with. 2. The semiconductor optical switch according to claim 1, wherein the upper and lower cladding portions are formed in one half of the upper and lower cladding layers, respectively. 3. The semiconductor optical switch according to claim 1, wherein the upper and lower cladding portions are formed in central portions of the upper and lower cladding layers, respectively. 4. A first step of forming a high-resistance first epitaxial layer to serve as a lower cladding layer on a semiconductor substrate of a first conductivity type; and a first step of implanting ions into a predetermined region of the first epitaxial layer. a second step of forming a lower cladding portion of a conductivity type, and a second epitaxial layer having a forbidden band smaller than that of the lower cladding portion and a lower carrier concentration on the first epitaxial layer.
a third step of growing an epitaxial layer of the second epitaxial layer; a fourth step of forming a high-resistance upper cladding layer on the second epitaxial layer; and a fourth step of growing a high-resistance upper cladding layer on the second epitaxial layer; a fifth step of implanting a second conductivity type upper cladding portion having a forbidden band larger than that of the second epitaxial layer and a higher carrier concentration; a sixth step of selectively etching the layers to respectively form a waveguide layer comprising the second epitaxial layer and an upper cladding region on the waveguide layer; a seventh step of forming a buried layer on both sides with a forbidden band larger than that of the waveguide layer; forming a first electrode on the upper cladding part of the upper cladding layer; and forming a first electrode on the bottom surface of the semiconductor substrate. and an eighth step of forming a second electrode. 5. The method of manufacturing a semiconductor optical switch according to claim 4, wherein the upper and lower cladding portions are formed in half of the upper and lower cladding layers, respectively. 6. Claim 4, wherein the upper and lower cladding portions are formed at central portions of the upper and lower cladding layers.
Or the manufacturing method of the semiconductor optical switch according to 5.