JPH0222849A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0222849A JPH0222849A JP17321788A JP17321788A JPH0222849A JP H0222849 A JPH0222849 A JP H0222849A JP 17321788 A JP17321788 A JP 17321788A JP 17321788 A JP17321788 A JP 17321788A JP H0222849 A JPH0222849 A JP H0222849A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- plug
- integrated circuit
- resin layer
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000011347 resin Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 238000007789 sealing Methods 0.000 claims description 2
- 238000003780 insertion Methods 0.000 abstract description 13
- 230000037431 insertion Effects 0.000 abstract description 13
- 238000000605 extraction Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特にその外部接続
機構の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of its external connection mechanism.
従来、半導体集積回路装置は、それ自身が外部端子を備
え、例えばデュラル・イン・タイプ・パッケージの如く
外部端子はパッケージの側辺部から外部に導出される。Conventionally, a semiconductor integrated circuit device itself has external terminals, and the external terminals are led out from the sides of the package, such as in a dual-in-type package, for example.
このように、従来の半導体集積回路装置は、パッケージ
の表面から外部に導出させた端子を介してそれ自身を回
路基板と接続する構造となっているので、体積が大きく
回路基板上の占有実装面積を増大せしめる。また、これ
に対する回路基板側においても集積回路装置を載置する
実装部位に端子を持たず平坦に形成されるため、基板試
験の実行が困難であるという問題が派生的に生じている
。In this way, conventional semiconductor integrated circuit devices have a structure in which they are connected to the circuit board through terminals led out from the surface of the package, so they have a large volume and occupy a large mounting area on the circuit board. increase. Furthermore, on the circuit board side, the mounting area on which the integrated circuit device is mounted is formed flat without having any terminals, which creates a secondary problem in that it is difficult to perform a board test.
本発明の目的は、上記の状況に鑑み、電子システム回路
を極めて高い実装効率で構築することのできる外部接続
機構を備えた半導体集積回路装置を提供することである
。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device equipped with an external connection mechanism that allows electronic system circuits to be constructed with extremely high mounting efficiency.
本発明によれば、半導体集積回路装置は、半導体チップ
と、前記半導体チップを気密封止するパッケージ樹脂層
と、前記パッケージ樹脂層内に埋込まれる埋込メス型引
出電極とを備えることを含んで構成される。According to the present invention, a semiconductor integrated circuit device includes a semiconductor chip, a package resin layer for hermetically sealing the semiconductor chip, and an embedded female lead-out electrode embedded in the package resin layer. Consists of.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す半導体集積回路装置の断面図およびその底面図で
ある０本実施例によれば、本発明の半導体集積回路装置
は、半導体チップ１と、内部リード２と、半導体チップ
１の電極と内部り一ド２とを接続するボンデング・ワイ
ヤ３と、半導体チップ１をボンディング・ワイヤ３を含
んで気密封止するパッケージ樹脂層４と、内部リード２
と電気的に内部接続されると共にパッケージ樹脂層４の
裏面にプラグ状差込電極差込口５を形成してパッケージ
樹脂層４内に埋込まれる埋込メス型引出電極６とを含む
、すなわち、本発明によれば、半導体チップ１の外部へ
の引出電極は、従来の導出リード形状に代えてパッケー
ジ樹脂層４の内部に埋込まれるメス型形状に形成される
。従って、これを基板実装する場合には特別な回路基板
が準備される。FIGS. 1(a) and 1(b) are a cross-sectional view and a bottom view of a semiconductor integrated circuit device showing an embodiment of the present invention, respectively.According to this embodiment, the semiconductor integrated circuit device of the present invention includes: A semiconductor chip 1 , an internal lead 2 , a bonding wire 3 that connects the electrode of the semiconductor chip 1 and the internal lead 2 , and a package resin layer 4 that hermetically seals the semiconductor chip 1 including the bonding wire 3 . and internal lead 2
and an embedded female lead-out electrode 6 that is electrically connected to the package resin layer 4 and is embedded in the package resin layer 4 by forming a plug-shaped insertion electrode insertion port 5 on the back surface of the package resin layer 4. According to the present invention, the lead-out electrodes to the outside of the semiconductor chip 1 are formed in a female shape that is embedded inside the package resin layer 4 instead of the conventional lead-out lead shape. Therefore, when mounting this on a board, a special circuit board is prepared.
第２図は本発明半導体集積回路装置を基板実装する場合
に使用する回路基板の構造例を示す斜視図であって、絶
縁基板７上の回路パターン８上にプラグ状差込電極９が
それぞれ設けられ、実装に際しては、集積回路装置裏面
のプラグ状差込電極差込口５にこの差込電極９がそれぞ
れ差込まれることによって互いの接続関係が完了される
。このように、集積回路装置と回路基板との接続端子構
造を従来と全く逆の関係におくことによって、集積回路
装置を従来より小型化することができ実装密度を高める
ことができる他、回路基板はそのプラグ状電極を利用し
て基板試験が容易に行い得るようになる。FIG. 2 is a perspective view showing an example of the structure of a circuit board used when mounting the semiconductor integrated circuit device of the present invention on a board, in which plug-shaped insertion electrodes 9 are provided on circuit patterns 8 on an insulating substrate 7, respectively. During mounting, the plug-in electrodes 9 are respectively inserted into the plug-shaped plug-in electrode insertion openings 5 on the back surface of the integrated circuit device, thereby completing the mutual connection. In this way, by placing the connection terminal structure between the integrated circuit device and the circuit board in a completely opposite relationship to the conventional one, the integrated circuit device can be made smaller than before, the packaging density can be increased, and the circuit board By using the plug-shaped electrode, board tests can be easily performed.
第３図は本発明の他の実施例を示す半導体集積回路装置
の斜視図である。本実施例によれば、引出電極の一方の
片側面のみが埋込メス型形状とされる。すなわち、埋込
メス型引出電極はパッケージ樹脂Ｍ４の一方の側面のみ
に平板状差込電極差込口１０を形成してパッケージ樹脂
層４内に埋込まれ、また、他方の片側面からは引出電極
が平板状差込電極１１に形成されてパッケージ樹脂層４
の側辺から突き出すように導出される。すなわち、本実
施例によれば、本発明の半導体集積回路装置は、埋込メ
ス型引出電極と差込型引出電極の双方を同一平面上に具
備するよう構成される。本実施例の構造は基板実装には
不向きであるが、２つ以上を′カスケードに接続すれば
回路基板を介さずに一つ、のシステムを構築することが
可能となる。FIG. 3 is a perspective view of a semiconductor integrated circuit device showing another embodiment of the present invention. According to this embodiment, only one side of the extraction electrode has a buried female shape. That is, the embedded female lead-out electrode is embedded in the package resin layer 4 by forming the flat plug-in electrode insertion port 10 only on one side of the package resin M4, and is not drawn out from the other side. An electrode is formed on a flat plug-in electrode 11 and the package resin layer 4
It is derived so that it protrudes from the side of. That is, according to this embodiment, the semiconductor integrated circuit device of the present invention is configured to include both the embedded female type extraction electrode and the plug-in type extraction electrode on the same plane. Although the structure of this embodiment is not suitable for mounting on a board, if two or more are connected in cascade, it is possible to construct a system without using a circuit board.
第４図は上記実施例の半導体集積回路装置をカスケード
接続した場合の接続状態図で、一方の平板状差込電極１
１ａを他方の平板状差込電極差込口１０ｂに差込む動作
を順次繰返せばよいことを示す、ここで、４ａ、４ｂは
２つの集・積回路装置それぞれのパッケージ樹脂層であ
る。FIG. 4 is a connection state diagram when the semiconductor integrated circuit devices of the above embodiment are connected in cascade.
This shows that the operation of inserting 1a into the other plate-like plug-in electrode insertion port 10b can be repeated in sequence. Here, 4a and 4b are the package resin layers of the two integrated circuit devices, respectively.
以上詳細に説明したように、本発明によれば、半導体集
積回路装置の引出電極はパッケージ内に埋込まれたメス
型電極に形成され、差込電極を介して他と接続されるの
で、形状寸法を小形化することができる。従って、回路
基板上への実装密度を上げることが可能となる他、メス
型電極と差込電極の両者が併せ形成された場合では、回
路基板を介さずに集積回路装置同志を直接接続してシス
テム回路を構成することができるので、システム構築の
小形化、迅速化、経済化に極めて顕著な効果をあげるこ
とができる。As described above in detail, according to the present invention, the extraction electrode of the semiconductor integrated circuit device is formed as a female electrode embedded in the package, and is connected to other parts via the insertion electrode, so that the Dimensions can be reduced. Therefore, it is possible to increase the packaging density on the circuit board, and when both the female electrode and the plug-in electrode are formed together, it is possible to directly connect the integrated circuit devices without using the circuit board. Since system circuits can be configured, extremely significant effects can be achieved in downsizing, speeding up, and economical system construction.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す半導体集積回路装置の断面図およびその底面図、
第２図は本発明半導体集積回路装置を基板実装する場合
に使用する回路基板の構造例を示す斜視図、第３図は本
発明の他の実施例を示す半導体集積回路装置の斜視図、
第４図は上記実施例の半導体集積回路装置をカスケード
接続した場合の接続状態図である、
１・・・半導体チップ、２・・・内部リード、３・・・
ボンディング・ワイヤ、４．４ａ、４ｂ・・・パッケー
ジ樹脂層、５・・・プラグ状差込電極差込口、６・・・
埋込メス型引出電極、７・・・絶縁基板、８・・・回路
パターン、９・・・プラグ状差込電極、１０．１０ａ。
１０ｂ・・・平板状差込電極差込口、１１．ｌｌａ。
１１ｂ・・・平板状差込電極。
茅
回
Ｃａ２
！FIGS. 1(a) and 1(b) are a cross-sectional view and a bottom view of a semiconductor integrated circuit device showing an embodiment of the present invention, respectively;
FIG. 2 is a perspective view showing an example of the structure of a circuit board used when mounting the semiconductor integrated circuit device of the present invention on a board, and FIG. 3 is a perspective view of a semiconductor integrated circuit device showing another embodiment of the present invention.
FIG. 4 is a connection state diagram when the semiconductor integrated circuit devices of the above embodiment are connected in cascade. 1... Semiconductor chip, 2... Internal lead, 3...
Bonding wire, 4.4a, 4b...Package resin layer, 5...Plug-shaped insertion electrode insertion port, 6...
Embedded female type extraction electrode, 7... Insulating substrate, 8... Circuit pattern, 9... Plug-shaped insertion electrode, 10.10a. 10b...Flat plug-in electrode insertion port, 11. lla. 11b... Flat plug-in electrode. Makai Ca2!
Claims (1)
ケージ樹脂層と、前記パッケージ樹脂層内に埋込まれる
埋込メス型引出電極とを備えることを特徴とする半導体
集積回路装置。1. A semiconductor integrated circuit device comprising: a semiconductor chip; a package resin layer for hermetically sealing the semiconductor chip; and an embedded female lead-out electrode embedded in the package resin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17321788A JPH0222849A (en) | 1988-07-11 | 1988-07-11 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17321788A JPH0222849A (en) | 1988-07-11 | 1988-07-11 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0222849A true JPH0222849A (en) | 1990-01-25 |
Family
ID=15956301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17321788A Pending JPH0222849A (en) | 1988-07-11 | 1988-07-11 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0222849A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0622760A1 (en) * | 1993-04-28 | 1994-11-02 | Kabushiki Kaisha Toshiba | External storage device and external storage device unit and method of producing external storage device |
-
1988
- 1988-07-11 JP JP17321788A patent/JPH0222849A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0622760A1 (en) * | 1993-04-28 | 1994-11-02 | Kabushiki Kaisha Toshiba | External storage device and external storage device unit and method of producing external storage device |
| US5552632A (en) * | 1993-04-28 | 1996-09-03 | Kabushiki Kaisha Toshiba | Plate-shaped external storage device and method of producing the same |
| KR100239261B1 (en) * | 1993-04-28 | 2000-01-15 | 니시무로 타이죠 | External memory apparatus unit |
| US6201295B1 (en) | 1993-04-28 | 2001-03-13 | Kabushiki Kaisha Toshiba | Plate-shaped external storage device and method of producing the same |
| US6274926B1 (en) | 1993-04-28 | 2001-08-14 | Kabushiki Kaisha Toshiba | Plate-shaped external storage device and method of producing the same |
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