JPH02226197A - Crt display controller - Google Patents

Abstract

PURPOSE:To reduce necessary memory capacity by providing >=2 frame buffer memories having capacity less than one image plane and repeating plotting operation and display operation alternately. CONSTITUTION:The CRT display controller consists of a display memory 1, a plotting circuit 2, two frame buffer memories 3 and 4, a display control circuit 5 and a CRT 6. In this case, display information on the frame buffer memory 3 while displayed on the CRT 6 is plotted on the frame buffer memory 4 and after the display of the frame buffer memory 4 which is being performed is finished, the display of the frame buffer memory having display information of a next raster is performed. The total capacity of the frame buffer memories 3 and 4 is a half as large as that of one image plane. Consequently, the necessary memory capacity is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CRT display control device, and particularly to a CRT display control device having a CRT using a raster scan method.

[Conventional technology]

A conventional CRT display control device of this type has a frame buffer memory for one screen or more, and serially reads out data for each rask and displays it on the CRT.

[Problem to be solved by the invention]

The conventional CRT display control device described above has a frame buffer memory for more than one screen, so in order to achieve high resolution and multiple colors, a large amount of frame buffer memory is required. There were drawbacks.

[Means to solve the problem]

The device of the present invention includes two or more sets of frame buffer memories each having a number of rasters smaller than the number of rasters required for displaying one screen, a drawing means for drawing display information on the frame buffer memory, and within the frame buffer memory. The display information of C
a display control circuit that performs control for displaying on the RT, and while the display information in one set of the frame buffer memories is being displayed on the CRT, drawing is performed on another frame buffer memory, and the display information is displayed on the CRT. The present invention is characterized in that after the display of the frame buffer memory is completed, the frame buffer memory having the display information of the next raster is displayed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a display memory 1. It is composed of a drawing circuit 2, two frame buffer memories 3 and 41, a display control circuit 5, and a CRT 6.

A display list memory 1 is a memory that stores information such as figures to be displayed. The drawing circuit 2 is a circuit that reads stored information from the display memory 1 and draws display figures etc. according to the contents to the frame buffer memory 3 or 4. The frame buffer memories 3 and 4 each have a capacity of 1024 pixels x 256 rusks. have.

The display control circuit 5 performs control to display the display information of the frame buffer memory 3 or 4 on the CRT 6, and immediately after the display of the frame buffer memory 3 is finished, the display of the frame buffer memory 4 is performed. Immediately after the display in the memory 4 is finished, the frame buffer memory 3 is displayed. CRT6 has 1024 pixels x
Rusk scan type CRT with 1024 Rusk resolution
It is.

Assume that triangle data is stored in the display list memory 1 in the form of geometric coordinate data. The display operation at this time is shown in FIG.

In FIG. 2 (2), first, a portion displayed at positions 1 to 256 rasks from the top is drawn in the frame buffer memory 3.

Next, in step (3), the portion from rasters 257 to 512 is drawn to the frame buffer memory 4, and at the same time, the contents of the frame buffer memory 3 are displayed at the positions from rasters 1 to 256 on the CRT. Similarly, in ■, drawing for the next 256 rusks is performed in frame buffer memory 3, and frame buffer memory 4
From then on, display is performed at the 257th to 512th raster positions of the CRTI.

Similarly, each frame buffer memory 3 is 256 rasks.
And the drawing/display of the frame buffer memory 4 is repeated. By repeating steps 2 to 2, the figure 2 is always displayed on the CRTI. At this time, the total capacity of the frame buffer memories 3 and 4 is only 1/2 of one screen.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing the required memory capacity by having two or more sets of frame buffer memories each having a capacity smaller than one screen and repeating drawing/display alternately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of drawing and display operations. DESCRIPTION OF SYMBOLS 1... Display list memory, 2... Drawing circuit, 3, 4... Frame buffer memory, 5... Display control circuit, 6... CRT.

Claims (1)

[Scope of Claims] Two or more sets of frame buffer memories each having a number of rasters smaller than the number of rasters required for one screen display; a drawing means for drawing display information on the frame buffer memory; and within the frame buffer memory. The display information of C
a display control circuit that performs control for displaying on the RT, and while the display information in one set of the frame buffer memories is being displayed on the CRT, drawing is performed on another frame buffer memory, and the display information is displayed on the CRT. A CRT display control device characterized in that, after the display of the frame buffer memory is finished, display of the frame buffer memory having the display information of the next raster is performed.