JPH02223220A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a propagation delay time and its output capacitor dependency by comprising an output transistor to execute the charge or discharge of the output capacitor of an input/output level converter of a bipolar transistor. CONSTITUTION:The title device is equipped with an internal logic block 11 having plural logic gate circuits including at least CMOS circuits and an input circuit 10 including the bipolar transistor to drive the input of the block. And the plural logic gate circuits are connected mutually with a gate array method. In the level converters of input and output buffers 10 and 12 for TTL-CMOS level conversion for the internal logic block 11 operated by a CMOS level, the output transistor which executes the charge and discharge of the output capacitor of the level converter is comprised of the bipolar transistor. Thereby, the propagation delay time and the capacitor dependency of the input and output buffers 10 and 12 can be reduced.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when used in a semiconductor integrated circuit device, for example, a logic semiconductor integrated circuit device whose input/output level is a TTL level and whose internal logic level is a CMOS level. It is.

[Background technology]

In FIG. 1, the input/output level tested by the inventor prior to the present invention is the TTL level.

1 shows a block diagram of a logic semiconductor integrated circuit device IC whose internal logic level is CMOS level.

Such a circuit device IC receives TTL level input signals IN, .
IN,=4Nn ftcMO8v An input buffer 10 for converting the level of the signal into a signal of 4Nn, an internal logic block 11 for performing logic operation at the CMOS level.
It includes an output buffer 12 for level converting the 0M08 level output No. 1 of this internal logic block 11 into a TTL level output signal, and each circuit 10, 11.12 is supplied with a 5 volt power supply voltage Vee, and Properly grounded.

Input terminals IN, IN, ... IN of the input buffer 10
The high level input voltage VlO' supplied to n is 2.0 volts or more, and the low level input voltage Vihto is 0.
Set to 3 volts or less. Therefore, input buffer 10
The input voltages and hold voltages Vithro for the input terminals IN, , IN, ...INn are 0.8 volts and 2
．． It is set at 1.3 to 1.5 volts between 0 volts.

On the other hand, the high level output voltage VOHIO obtained from the output of the input buffer 7710 is set equal to the high level input voltage V int 1 of the internal logic block 11, and the low level input voltage VOL obtained from the output of the input buffer 10 is set equal to the high level input voltage V int 1 of the internal logic block 11.
IO is the low level input voltage Vi of the internal logic block 11
Set equal to hxx. Therefore, P channel M constituting the CMOS inverter in internal logic block ll
O8FET threshold 1 hold voltage VTP, N channel MO8FET threshold 8. Hold voltage VTN
+Power supply N voltage 1k Vc c ): -Sult, above voltage”
0HIO+V 1)111. pVOLIO+ vi
Each Lll is set as follows.

Vauxo = Vil(tz > Vcc-I VTP
l ”(1,)VOLIO=VILl!, <VTN
l'' (2) Vcc to 5 volts j I
VTP 1iko, 6 volt IVTN wo 0.6 hok
Thread set to VOHIO and VIHtx is 4.4
VOLIO and V1Llr should be set to 0.6 volts or more.

Therefore, the input logic threshold voltage Vlthxt of the CMOS inverter within the internal logic block 11
is set at approximately 2.5 volts between 0.6 volts and 4.4 volts.

Similarly, the high level output voltage v of the internal logic block 11
outi and the no-level input voltage V of the output buffer 12
The low level output voltage VOLII of the internal logic block 11 and the low level input voltage ViLx2 of the output buffer 12 are set to 0.6 volts or less, and the output buffer 120 input logic
Threshold Vith12 is 0.6 volts and 4.
It is set at about 2.5 volts between 4 volts and 4 volts.

The high level output voltage VOH of the output buffer 12 is set so that the output buffer 12 generates a TTL level output signal.
II is 2.7 volts or more, its low level output voltage V
OLI! is set to 0.5 volt or less.

FIG. 2 is a circuit diagram showing one of the input roses 7710 tested by the inventor of the present invention prior to the present invention, and has a P channel M 08 F E T M p+ 2M p.

N channel M 08 F E T M n 1 +
M n yi + M n @.

It is composed of a resistor Rp. The gate, source, and drain of each MO8FET are indicated by the symbol g*s+dK, respectively.

1st stage CMOS composed of MpI and Mn.
The inverter and a second stage CMOS inverter composed of Mpt and Mn are connected in cascade, and Rp and Mu constitute a gate protection circuit for protecting the gate insulating films of MpI and Mrl. . The output capacitance Cs connected to the drains of Mpt and Mn of the second stage CMOS inverter is actually the drain capacitance of Mpt and Mrl, the output of the input buffer 7 and the internal logic block 11.
Its value is determined by the wiring stray capacitance between it and the input of the internal logic block 11, and the input capacitance of the internal logic block 11.

Each M08 FETMI)zMrit*MJtMnt+M
The ratio W/L of channel width W and channel length of n is 27/3.5.42/3 and 126/3.5, respectively.
42/3 and 15/3, and the resistance Rp is set to a value of 2 kilohms.

FIG. 3 shows the propagation delay time tP of the input buffer 10 in FIG.
The dependence of the output capacitance Cs of HL e j PLH is shown, the vertical axis shows the propagation delay time, and the horizontal axis shows the output capacitance Cs.

As shown in FIG. 35, the first propagation delay time t PH
L is defined as the time from when the input INPUT changes with the 50% value as the border until the output 0UTPUT changes from the high level to the low level with the 50% value as the border, and is the second propagation delay time t. PLH is input I
Output becomes 0UT after NPUT changes around 50% value.
Part 5 when PUT changes from low level to high level
It is defined as the time until it changes from the 0% value.

Note that in FIG. 35, tf is defined as falling time, and tr is defined as rising time.

in this way,! s3, the output capacitance dependence KHL (=ΔtpHL/ΔCs) of the first propagation delay time tFIL of the input buffer 10 in FIG. 2 is approximately 0.
8nsec/pF *Second propagation delay time L PL
Output capacitance dependence of H Khn (=△t PLH/ΔCm)
Both are large, approximately 1.4 nsec/pF.

In the input buffer 10 of FIG. 2, in order to set the input threshold voltage Vtthlo to approximately 1.3 to 1.5 volts, the M I of the first stage CMOS inverter is
), and Mn, the ratio of channel width to channel length W
/L are greatly different, and the propagation delay time jPHL
+ In order to reduce the output capacitance dependence KHL and KLH of 1PLH, the ratio W/I of M9t and Mn of the second stage CMo and 9I/verters are both set to large values of 42/3, and Mp and Mrl are , which increases the channel fundance of .

In order to reduce the dependence of both output capacitances KHL y KLH, the ratio W/L between Mn5 and Mn of the second stage CMOS inverter should be increased, but this is because the This results in a significant increase in the area occupied by the input buffer 10, which hinders improvement in integration density.

In other words, although miniaturization is currently being vigorously promoted in the manufacturing technology of integrated circuits, the lower limit of the channel length of MOS FET in current photolithography using ultraviolet exposure is 3 μm, and the ratio W/L of MOS PET is
In order to make the channel width W extremely large, the channel width W must be made extremely large, and ultimately the M
This is because the area of the element region of the OS FET is significantly increased.

On the other hand, FIG. 4 is a circuit diagram showing one of the output buffers 12 studied by the inventor of the present invention prior to the present invention.
O8FET Mn4)? : Therefore, it is configured. The gate, source and drain of each MO8FET are respectively designated by the symbol g+'+dK.

Internal logic block 110C'MO within the integrated circuit device IC
The 8-level output signal is output from Mn4 and Mn of the output buffer 12.
The power supply voltage CC of 5 ports is supplied to the terminal No. 30, which is applied to the gate of 4. Therefore, the output buffer 120 input logic threshold, hold voltage V
In order to set ith1z to about 2.5 volts, the ratios W/L of Mri4 and Mn4 are set to equal values.

Similarly, a TTL circuit 14 is shown in FIG. 4, and a power supply voltage Vcc of 5 volts is supplied to this circuit 14 through a terminal No. 35. The output signal of the output buffer 12 at the TTL level is obtained from the 20th terminal, and is sent to the multi-emitter transistor Q of the TTL circuit 14 via the 32nd terminal.
, is fed to one emitter of .

On the other hand, as a TTL circuit, it is a standard type TTL circuit.

Shisotki T T Lfi13, Low Power Shitki T'rLll Road, Advanced Low Power
A number of digital TTL circuits have been published, and their characteristics are, of course, somewhat different from each other.

Further, the output of the output buffer 12 is transmitted to a large number of TTL circuits 14.
It is necessary to drive the 0 inputs simultaneously and in parallel. One measure of this driving ability is low power
It is possible to drive 20 inputs of the Toki TTL circuit in parallel.

When the output of the output buffer 12 is low level, the low level
0.0 from one input of the power switch TTL circuit.
4mA low level input current III, output buffer 1
2 N-channel MO8FB'l'Mn4 drain
flows into the source path. Therefore, in order for the output buffer 12 to drive the 20 inputs to the low level as described above, Mn4 needs to flow a total of gmA.

On the other hand, the low level output voltage VOL1 of the output buffer 12
As explained above, t must be less than 0.5 volts, so N channel A/MO8 of output buffer 12
On-resistance ROM of FET Mn4 is 0.5 volts/8
It must be set to a small value of -62.5 ohms.

In this way, in order to make the on-resistance ROM of Mn4 a small value, the ratio W/L of Mn should be set from 700/3 to 1000.
It must be set to an extremely large value of /3. On the other hand, as mentioned above, the input logic threshold voltage h1g of the output buffer 120 is set to about 2. ．． In order to set it to 5 volts, the ratio W/L of MP4 and Mn4 must both be the same value, so the ratio W/L of P-channel MO8FET MP4 of the output buffer 12 is also 700/3.
It must be extremely large, ranging from 1000/3 to 1000/3.

This also results in a significant increase in the area occupied by the output buffer 12 on the surface of the integrated circuit chip, which not only hinders the improvement of integration density but also increases the switching speed of the internal logic block 11 for the following reasons. causes a severe drop in

That is, both MO8FETM p of the output buffer 12
When the ratio W/L of 4*M n 4 is both set to a large value, the gate capacitance of both MO8PET Mp4 s Mna also becomes a proportionally large value. Since these gate capacitances of Mp4°Mn4 become the output load capacitance of the internal logic block 11, the output resistance of the internal logic processor 11 and these gate capacitances cause a reduction in the switching speed of the internal logic block 11.

On the other hand, the output of the output buffer 12 is not only led out as an external output terminal (terminal 20) of the integrated circuit device IC, but also connected to the human power terminals of a large number of TTL circuits 14 via external wiring. A12 output load capacity Ox
1. may be an extremely large value. It happens often.

Figure 5 shows the output load capacitance Cx of the output buffer 12 in Figure 4.
Propagation delay time for! The dependence of PHL r fPLH is shown, the vertical axis shows the propagation delay time, and the horizontal axis shows the output load capacity.

As can be understood from Fig. 85, the capacitance dependence KHL (-ΔtpuL/ΔCx) of the first propagation delay time t PHL of the output buffer j2 in Fig. 4 is approximately 0.3 ns.
c/p F, jg 2 propagation M chicken time t PLH
The capacity-dependent KLH (-△tpLu/△Cx) is approximately 0.
17 n5ec /pF, both of which are large.

Therefore, the problems of the input buffer 100 shown in FIG. 2, which are the background art of the present invention, can be summarized as follows.

(1) In order to reduce the dependence of the propagation delay time of the input buffer 10 on the output capacitance, K is the input buffer 002nd stage C
Both M08 FE'l'Mpt of MOS inverter,
The ratio W/L of Mnt must be increased, which is a hindrance to improving the integration density. In particular, when the integrated circuit device IC is of the master slice type or semi-custom gate array type, there is a possibility that an extremely large number of gated input terminals in the internal logic block 11 are connected to the output of the input buffer 10, and the input Output capacity O of buffer 10
When s becomes extremely large, the above problem becomes extremely serious.

(2) Furthermore, the first stage of the input buffer 10 is CMOS
Since it is composed of inverters Mp+ r Mn1,
Even if a gate protection circuit composed of Rp and Mns is connected, the breakdown strength of the gate insulating films of both MO8PETs against the surge voltage applied to the input terminal IN is not sufficient.

Further, the problems of the output buffer 12 shown in FIG. 4, which are the background art of the present invention, can be summarized as follows.

(3) In order to set the output buffer 7a 120 input logic thread and hold voltage Vith1g to approximately 2.5 volts and to increase the current sinking ability of the output buffer 7a 12 during low level output, both MO8FETs must be Mp4,
Both Mn4 f) ratios W/L must be set to equal and large values, which hinders the improvement of the integration density.

(4) When the ratio W/L of both MO8FETs Mp4°Mn4 of the output buffer 7a 12 is increased, both Mp4 +
The gate capacitance of Mn also increases. Therefore, the output resistance of the internal logic block 11 and the gate capacitance cause a reduction in the switching speed of the internal logic block 11. especially,
The output stage of the internal logic block 11 is an MO with a large output resistance.
In the case of a SPET, this reduction in switching speed becomes a significant problem.

(5) Output buffer 12 is MOS FET 'Mp
<.

Mfm, the propagation delay time is highly dependent on the output load capacitance CXK. This problem becomes particularly important when the output of the output buffer 12 is connected to a large number of TTL circuit 140 input terminals.

[Purpose of the invention]

The object of the present invention is to provide an internal logic block that generates an output signal of 0MO8 level by applying a CMOS level input signal, and a level conversion system such as TTL-0MO8 level conversion for this internal logic block. In a semiconductor integrated circuit device having a manual buffer and/or an output buffer for power conversion such as 0MO8-TTL level conversion, the integration density can be improved, and the input buffer and/or the output buffer
The purpose of this invention is to reduce the dependence of the operating speed on the output capacitance and to improve the operating speed.

The above and other objects and novel features of the present invention include:
It will become clear from the description of the invention and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a converting buffer converter for TTL-CMOT level conversion for an internal logic block that operates at the 0M08 level, the output transistor that charges or discharges the output capacitance of the level converter is configured with a bipolar transistor. By this, M
Compared to an OS FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of the input buffer and its capacitance dependence It is possible to achieve the purpose of reducing the

In addition, in the level converter of the 0MO8-TTL level conversion output buffer for the internal logic block that operates at the 0MO8 level, the output transistor that charges or discharges the output load capacitance of the level converter is a bipolar transistor. By configuring
Compared to a MOS FET, the Pipo 11 transistor has a small element size, but its output resistance is small and its current amplification factor is large, so it can handle a large charging current or discharging 1! By virtue of the effect that the flow is obtained, the purpose of reducing the propagation delay time of the input buffer and its capacity dependence can be achieved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 shows a block diagram of a logic semiconductor integrated circuit device IC according to an embodiment of the present invention, in which the input buffer 10 of FIG.
Internal logic block 1 of the TTL-CM08 level conversion conversion buffer 20 that performs the same operation as
The internal logic block 21.1 operates at the 0MO8 level similarly to .1. 0MO8-TTL level conversion output buffer 7a2 which performs the same operation as the output buffer 7a in FIG.
2, each circuit 20, 21, 22 is connected to 5 through terminal 30.
It is supplied with a power supply voltage Vcc of volts and is properly grounded via terminal No. 31.

The input buffer 7a 20 has a plurality of TTL-CMOS level converters 201, 202...20rl, and each input is connected to the 1st terminal, 2nd terminal...19th terminal,
Each output is connected to the internal logic block 21 by an aluminum wiring layer inside the circuit device IC.

Internal logic block 21 is 0MO8, NAND goo) 21
1,212,213.21'4 SaraKCMQ8- No
Dag-21 (l-1), 2] 1 and 0 as necessary
MO8 exclusive OR gate, 0MO8 transmission gate.

Includes 0MO8 inverter, etc.

The 0MO8-NAND gate 211 is, for example, a P channel MO8FETM, ,M, and an Nf channel MO8F'ETM, as shown in FIG.

It is composed of a pure CMOS circuit including M4. Further, as other examples of the 0MO8-NAND gate 211, as shown in FIG.
Resistance 7. It can also be configured by a quasi-CMOS circuit that further includes R3, and since the output stage of such a quasi-CMOS circuit is composed of Bibo2 transistors Q= and Qt, the output drive capability is improved and the propagation delay time is reduced. Output load capacitance dependence can be reduced.

Further, the 0MO8-No gate 211 includes, for example, P-channel MO8FETM, M, and N-channel MO8FET M, as shown in FIG.

It is composed of a pure CMOS circuit including M4. Further, as another example of the 0MO8-NOR gate 211, the first
As shown in figure O, the NPN transistor Q1. It can also be configured by a quasi-CMOS circuit including Q2 and resistors R, ,R, in the sheath, and since the output stage of such a quasi-CMOS circuit is composed of Bibo2 transistors Q, ,Q, the output drive is The performance is improved, and the dependence of the propagation delay time on the output load capacitance can be reduced.

In the internal logic block 21, these 0M08, N
AND gates and 0MO8-NO gates are connected in various configurations according to the master slice method or semi-custom gate array method.

For example, as shown in Figure 11, two 0MO8 NAN
By combining D gates or by combining two 0MO8-NOR gates as shown in FIG. 12, a 70-87 lip is constructed, and as shown in FIG. Gated gates controlled by clock signal C by combining gates
Furi, Pu Frog is composed.

In this way, in a master slice type or gate array type logic semiconductor integrated circuit device IC that meets customer needs, the input buffer 200 level converter 201.2 can be configured by changing only the wiring pattern.
The outputs of 02...20rl and the inputs of various gates or inverters of the internal logic block 210 are connected in various ways, and the outputs of the various gates or inverters of the internal logic block 210 and the output buffer 220 level are similarly connected. The inputs of the converters 221, 222, . . . 22m are connected in various ways.

The output buffer 22 has a plurality of 0MO8-TTI level converters 221, 222...22m, each output is 20@
Terminal, 21@terminal...Connected to terminal 29.

Input buffer 200 level converter 201, 202...
The essential features of 20n are as follows.

(1) Each level converter 201.202...20n
Press the input threshold of Vith
It is set between the L o -v level input voltage of 0.8 volts and the TTL high level input voltage of 2.0 volts.

(2) The output transistor that charges or discharges the output capacitance Cm of each level converter 201, 202, . . . 2011 in response to the input signal supplied to its input terminal is constituted by a bipolar transistor.

Furthermore, an input buffer 200 and a level converter 201゜20
Preferred features of preferred embodiments of 2...20n are as follows.

(3) A Schottky barrier diode is connected between the base and collector of the bipolar output transistor Q, which discharges the output capacitance Cs in (2) above.

(4) The base and collector of the drive transistor Q for driving the base of the bipolar output transistor Q1 with its output in response to the input signal supplied to the input terminal of each level converter 201, 202...20n. A second Schittky barrier diode is connected between the two.

(5) The output transistor for charging the output capacitance Cs of each level converter 201, 202, . . . 20n is also constituted by a bipolar transistor Q1.

(6) Drive transistor Q via MO8 buffer with high input impedance and amplification effect.

The base or collector signal of Q is transmitted to the base of the charging bipolar output transistor Q.

(Power) Between the input terminal of each level converter 201, 202, .

(8) A PNP emitter/7-lower transistor Q4 and a PN junction diode D for level shifting are connected between the input terminal of each level converter 201.202-2On and the base of the drive transistor Q. There is.

14 to 31 show various circuit diagrams of the level converter 201 of the input buffer 20 according to an embodiment of the present invention, and all of these level converters are configured according to the above (1) and (2).
It has the essential characteristics of Furthermore, these level converters have at least one of the preferred features (3) to (8) above.

In the level converter 201 of FIG. 14, the input i
Nl is connected to the cand of a Schottky barrier diode D for level shifting, and its seventh lead is connected to the base of the drive transistor Q. The forward voltage V of this diode D is 0.35 volts to 0.41 volts.
The ai and barrier area of the barrier metal are determined to be set for the bolt. The forward voltage P of the switching barrier diode D of the level converter shown in FIGS. 15 to 31 is similarly set to 0.35 volt to 0.41 volt.

Furthermore, in FIG. 14, the drive transistor Q and the discharging output transistor Q have a lock barrier diode D between their bases and collectors, as shown by their hook-shaped pace electrode signals. is connected. Clamped transistors with Schottky barrier diodes thus have a very small storage time, as is well known. In the examples below, transistors with key-shaped base electrode signals are shown to be such clamped transistors. Note that the base of the discharge output transistor Q has a resistance ratio of 5 kilohms for discharging the base charge. is connected to the ground potential point via.

Further, in FIG. 14, a resistance ratio of 18 kilohms and a resistor Riffi of 2 kilohms are connected in series between the power supply voltage Vcc and the 7th node of the Schittke barrier diode D1. Both resistances R,,,R,! The common connection point is a P-channel MO8FET as a phase inverter.
Mp. , and its drain is connected to the base of the charging output transistor Q.

Furthermore, in order to ensure that transistor Q is turned off when the level converter 201 generates a low level output,
A diode D is connected.

The output of the level converter 201 at the emitter of the charging output transistor Q is connected to the output capacitor Cs and the CMOS NAND gate 2 of the internal logic block 21.
11 inputs.

Also, bipolar transistors Q,,Q.

The area of each emitter of Q is 100μ to 144μ. am'
It is also possible to set the area to be smaller than this. Furthermore, the ratio W/L of MOS F'ET is 3
The value is 2/3 to 64/3.

The inventor has confirmed that the embodiment shown in FIG. 14 having the above configuration has the following propagation delay time and its output capacitance dependence.

t PHL (when C5=QpF)...1.
6 n5ect PLH (when C5=QpP)・
-・5.7nsecKHL
o-0,4n5ec/pFKLH...0.4nsec/p
F It can be seen that the propagation delay time I PHL * L PLH and the output capacitance dependence KHL + KLH described above are superior when compared with the characteristics of the input buffer 10 shown in FIG.

Furthermore, the level converter 201 in FIG. 14 can obtain desired characteristics for the following reasons.

(1) Barrier diode D, +7)
[The directional voltage V, is set to 0635 to 0.41 volts, and the base-emitter voltage V of the transistors Q, , Q,
BI! l e Since VBE2 is approximately 0.75 volts, the input threshold voltage V of the level converter 201
ith is set as follows.

Vith=-Vr+Vagl+Vagz=1.09 to 1.15 volts (2) The output transistors Q+ and Q- that discharge or charge the output capacitance CII of the level converter 201 are composed of bipolar transistors with small output resistance. Therefore, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Transistors Q, , Q driven into the saturation region
.

Since a Schottky barrier diode is connected between each base and each collector of Q, the accumulation time is reduced when both transistors Q, Q, switch from ON to OFF. be able to.

(4) The potential at the common connection point of resistors R, 1, 几 and t rises, resulting in phase inversion MO8FET Mp+. , when the charging output transistor Q is turned off, the MOSFET
Since the input impedance of the gate of MP++ is very high, the current flowing from the common connection point to the gate of Mp,0 becomes very small. Therefore, MOS FET
Mf)t. Compared to the case where the phase inverter is configured by a Bibo 2 transistor instead, the operating speed for switching the charging output transistor Q from off to on is improved.

The level converter 201 in FIG. 15 differs from the one in FIG. 14 only in that another PN junction diode D is added, and the addition of this D4 further reduces the low level output voltage of the level converter. be able to.

Regarding the level converter 201 shown in FIG. 15, the propagation delay time and its output capacitance dependence were confirmed by the inventor as follows.

t PHL (However, when C5=OpF)...1.89
nsectpt, n (when C5=OpF) -6,
37naecKHL...
0.4 n5ec/pFKLH=0.4 n5ec/
pF' Further, the level converter 201 in FIG. 15 can also obtain desired characteristics for the same reason as in the case of FIG. 14.

The level converter 201 in FIG. 16 includes a drive transistor Q,
Only the collector connection method in FIG. 14 is different from that in FIG. 14, and the propagation delay time of the level converter in FIG. 16 and its output capacitance dependence were confirmed as follows.

tpuL (when C5==OpF)"1.81ns
ectpLH (when C5=OpF)...5.0
8nsecKHL”・0.
4 n5ec/pFKL! (...0.4 n5ec/pF Also, in the level converter 201 in FIG. 16, the first
Desired characteristics can be obtained for the same reason as in the case of Figure 4.

Each level converter 201 in FIG. 17 is a MO8F for phase inversion.
ET Mp,. The only difference from the one in FIG. 15 is that another NPN transistor Q is connected between the drain of the charging output transistor Q and the base of the charging output transistor Q, and the propagation delay time of the level converter in FIG. And its output capacity dependence was confirmed as follows.

t PHL (However, when C5==OpF)...2.
O1nsectrhii (when C5==OpF)
”・7.30nsecKHL
...0.4 n5ec/pFKLH”・0.4 n
5ec/pF In the level converter 201 of FIG. 18, the transistors Q, , Q, are clamped transistors with Schottky barrier diodes, and the base of the discharging output transistor Q, is 5 kΩ for discharging the base charge. It is connected to the ground potential point via a resistor R8°. Also, transistor Q.

A 20 kilohm resistor for collector current limiting is connected to the collector.

Power supply voltage Vcc and shuttling barrier diode D1
A resistor R8I of 18 kilohms and a 2
A kilohm resistor R1 is connected in series. The common connection point of both resistors is the P-channel O8FET Mp+ as a charging output transistor.
It is connected to the + gate.

Further, the ratio W/L of Mp, , is 64/3.

The propagation delay time of the level converter 201 shown in FIG. 18 and its output capacitance dependence were confirmed as follows.

tpHL (when C5=OpF)...-1,9n
5ectpLH (when C5=OpF) -2,9n
secKnL...0.4 n5ec/pF K LH...1.3 n5ec/pF Furthermore, the level converter 201 in FIG. 18 can obtain desired characteristics for the following reason.

(1) As in the case of FIG. 14, the level converter 2010
Input voltage hold voltage ■ith 1.09 to 1
．． It can be set to 15 volts.

(2) Since the output transistor Q that discharges the output capacitance C3 of the level converter 201 is composed of a bipolar transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacity dependence can be reduced.

(3) As in the case of Fig. 14, transistor Q++Q
, the accumulation time can be reduced.

In the level converter 201 of FIG. 19, the transistors Q, Q, are glued transistors with shield barrier diodes, and the base of the discharging output transistor Q, is 5 kΩ for base charge discharging. It is connected to the ground potential point via a resistor R2°. A load resistance R of 8 kilohms is placed on the collector of the transistor Q.
1, and a 20 kilohm resistor R24 is connected between the power supply voltage Vcc and the anode of the Schottky barrier diode D. Drive transistor Q!
The collector signal of is connected to the gate of an N-channel MOB FET Mn1t as a charging output transistor. Moreover, the ratio W/L of this Mn11 is 64/3
is set to .

The propagation delay time of the level converter 20 in FIG. 19 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=OpF)...1.
1 n5ectPLH (however, C5=OpF Tokito...
8.6nsecKHL conflict/
-0.3 nsec/pFKLH=2.0 nsec/pF Furthermore, the level converter 201 in FIG. 19 can obtain desired characteristics for the same reason as in the case of FIG. 18.

In the level converter 201 of FIG. 20, the transistors Q, , Q, are similarly clamped transistors, and the base of the output transistor Q for discharging also has a 5 kilohm resistor for discharging the base charge. connected to the ground potential point via ~). 1 at the collector of transistor Q.
A load resistor of 0 kilohms is connected, and the power supply voltage V
A 20 kilohm resistor RI4 is connected between cc and the anode of the Schottky barrier diode D. The collector signal of the drive transistor Q is an N-channel M08 FET M as an amplification transistor.
applied to the gate of nn, and the ratio W/L of Mfl+3 is 32
/3, and a load resistance ratio of 20 kilohms is connected to the drain of Mn+s. The drain signal of Mnts is connected between P channels as an amplification transistor.
It is applied to the gate of 8FET Mptm, the ratio W/L of Mp, , is set to 64/3, the drain of Mp, , has a load resistance of 10 kilohms, and the pace charge of the bipolar output transistor Q, for charging.几3 as a discharge resistor
．． is connected.

The propagation delay time of the level converter 201 shown in FIG. 20 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=OpFO)...-2,2
nsectpLH (when C5=OpF) -...
7.5 n5ecKHL…
0.4 n5ec/pFKLH...0.4 n5ec
/pF Furthermore, the level converter 201 in FIG. 20 can obtain desired characteristics for the following reason.

(1) As in the case of FIG. 14, the level converter 2010
Set the input threshold voltage between 1.09 and 1.
．． It can be set to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time in charging and discharging the output capacitance Cs and its dependence on the output capacitance can be reduced.

(3) As in the case of FIG. 14, transistor QstQ
, the accumulation time can be reduced.

(4) The collector potential of the drive transistor Q increases and [
When the charging output transistor Q switches from off to on, the amplification MO8FET M n I
a and Mp,, is Q! Amplify the collector potential change of Q
, as well as transmitting the pace of the Mn8 FE
The extremely large gate impedance of T Mn+m prohibits a large pace current from flowing directly from the collector of Q to the pace of Q, thereby increasing the switching speed of the output transistor Q3.

In the level converter 201 of FIG. 21, QI#Q,
The clamped transistor 11 is a shuttling barrier diode for level shifting, and the resistor R8°,
R, 4, R, are set to 5 kilo ohms, 20 kilo ohms, and 8 kilo ohms, respectively. The collector signal of the drive transistor Q is a P-channel MO8PET Mp1 that constitutes a CMOS inverter as a voltage amplifier.
4 and N channel # M O8F E T M n 1
MMO8FET MP+a
, Mnn drain signals are applied to the gates of P-channel MO8FETs Mp, , as charging output transistors OMp, 4. Mn+41 Mp+t(7)
W/L+- in various places! , 24/3.22/3.64 respectively.
/3.

The propagation delay time of the level converter 201 shown in FIG. 21 and its output capacitance dependence were confirmed as follows.

tpuL (when Cs = Op F)...2.
02n3eC・tpt, H (Cs = Op F
)...4,27nsecKHL
...0.42nsec/pFKLH...1.3
2 nsec/pF Furthermore, each level converter 201 in FIG. 21 can obtain desired characteristics for the following reasons.

(1) As in the case of FIG. 14, set the input threshold and hold voltage vtth of the level converter 201 to 1.09 to 1.
．． It can be set to 15 volts.

(2) The output transistor Q that discharges the output capacitance C3 of the level converter 201 is composed of a bipolar transistor with a small output resistance. Output capacitance dependence can be reduced.

(3) As in the case of Fig. 14, K, transistor QllQ
, the accumulation time can be reduced.

In the level converter 201 in FIG. 22, h>, Q+ is a clamped transistor as an output transistor for discharging, and the cathode of a Schottky barrier diode D10 for level shifting is connected to the input terminal IN. . A PN junction diode D for level shifting is connected between the anode of D and the fat paste, and the power supply voltages Vcc and DI are connected.

Between both anodes of D- is a resistor R, , , R, whose resistance value is equal to 10 kilohms. are connected in series,
A switch barrier diode D for discharging the pace charge is connected between the input terminal IN and the pace of Ql.

Resistance R1,,R,. The common connection point of Mp, , is connected to the gate of a P-channel MO8F.ETMp, , which serves as a charging output transistor, and the ratio W/L of Mp, , is set to 64/3.

The propagation delay time of the level converter shown in FIG. 22 and its output capacitance dependence were confirmed as follows.

t IIHL (However, when C5=QpF)...2.
44nsectpLn (when C5=OpF) ・
・・5.41 n5ecKHL
...1.0nsec/pFKLH=5.3ns
ec/pF' Furthermore, the level converter 201 in FIG. 22 can obtain desired characteristics for the following reason.

(1) The forward voltage vF of the snow barrier diode D is set to 0.35 to 0.41 volts, and the PN
The forward voltage V, of the junction diode D, is 0.75 volts, and the base-emitter voltage vag of the transistor Q,
Since x is 0.75 volts, the voltage and hold voltage Vlth input to the level converter 2010 for turning on the transistor Q is set as follows.

Vith=-VFI +VF5 +VBI11-1.0
9 to 1.15 volts (2) Since the output transistor Q, which discharges the output capacitance Cs, is composed of a bipolar transistor with small output resistance, the switching time or propagation delay time and its dependence on the output capacitance can be reduced. can do.

(3) Since the transistor Q is a double-amplified transistor, its storage time can be reduced.

In the level converter 201 of FIG. 23, Q.

Q is a clamped transistor, D is a level shift barrier diode, and is a resistance horse.

, R, , R, are set to 5 kilohms, 20 kilohms, and 8 kilohms, respectively. Drive transistor Q! The collector signal of CMOS as a voltage amplifier
P-channel MO8FET M that constitutes the inverter
pr+ and N-channel A/MO8FET MnI4 are applied to both gates, and the drain output of both Mp8 PET is connected to the switch P-channel MO8FET Mp,
・A gate voltage is applied. M pH41M n+4,
The local W/L of M pH is 24/3.32/3 respectively.
．． It is set to 64/3.

The drain output of the MOS FE'r Mp, , is applied to the base of the Bibo2 transistor Q3, which serves as a charging output transistor.

The propagation delay time of the level converter shown in FIG. 23 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=OpF)...5.0
7nsectpt, H (however, C5=Qpp's Tokito"5
．． 09 n5ecKHL…
0.4 n5ec/pFKLH...0.4nsec/
pF Furthermore, the level converter 201 in FIG. 23 can obtain desired characteristics for the following reason.

(1) As in the case of Fig. 44, the level converter 2010
Input voltage and hold voltage vtth from 1.09 to 1
．． It can be set to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time in charging and discharging the output capacitance Cs and its dependence on the output capacitance can be reduced.

(3) As in the case of Fig. 14, 1 transistor Qrt
The accumulation time of Q can be reduced.

(4) When the collector potential of the drive transistor Q rises and the charging output transistor Q switches from off to on, the CMOS equalizer M pH4, M
n,4 not only amplifies the collector potential change of Q and transmits it to the base of Q, but also MOS FET M
The extremely large gate impedance of plat MnI prevents a large base current from flowing directly from the collector of Q to the base of Q, thereby improving the switching speed of the output transistor Q.

The level converter 201 in FIG. 24 is a charging output transistor Q, and a 10 kilohm resistor RI for discharging the base charge.
The only difference from the one in FIG. 23 is that 6 is connected between the base and emitter of Qs, and the propagation delay time and output capacitance dependence of the level converter 201 in FIG. street confirmed.

Lpux, (when C5==OpF) "6.2ns
ec' tphH (when C5==opF)...4
．． 9nsecKHL...
・0.4 n5ec/pFKLH-0,4n5ec/p
F Furthermore, the level converter 201 in FIG. 24 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter 201 in FIG. 25 has a base charge discharging circuit of a discharging output transistor Q whose resistance R1 is a resistor RI1. , 3 kiloohm resistance R,,,
A clamped transistor Q is replaced by an active pull-down circuit configured with a shutoff barrier diode for discharging the base charge of the charging output transistor Q, at the base of Q, and at the collector of Q. The only difference from the one shown in FIG. 24 is the connection between the two, and the propagation delay time and its output capacitance dependence in FIG. 25 were confirmed as follows.

t PHL (when C5=-OpFQ) -・5.5
nsectpLH (where C5=QpF time piece"5.3
nsecKHL=0.4
n5ec/pFKLH...0.4 n5ec/pF Furthermore, the level converter 201 in FIG. 25 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter 201 in FIG. 26 is the active pull-down circuit B in FIG. 25. , R3゜? The only difference from the one in Fig. 24 is that the discharge resistor R3° is replaced by the same active pull-down circuit as Q6, and the propagation delay time and its output capacitance dependence in Fig. 26 are as follows. confirmed.

t PHL (However, when C5=OpPO)・-・8.8
2nsectptH (when C5=QpF) ---
4.7nsecKHL…0
．． 4 n5ec/pFKLH...0.4 n5ec/pF Furthermore, the level converter 201 in FIG. 26 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 of FIG. 27, bipolar transistors Q+-QotQa are a discharge output transistor and a drive transistor, respectively.

These are output transistors for charging, and D, , and D are respectively level-shifting Schottky barrier diodes and P.
It is an N-junction diode, and 4. R. .

R1, , R, , are respectively 20k ohm, 8k ohm, 10k ohm, 10k ohm om resistance, and M
P+s #MrsH is each P channel M08
FE'r, N-channel MO8FB'l', and the ratio W/L of both Mp+a l Mnl@ is both set to a value equal to 32/3.

In particular, M I) + s + M nts * Q + s
Qs is characterized in that it is a quasi-CMOS inverter type amplifier with low output resistance.

The propagation delay time of the level converter 201 shown in FIG. 27 and its output capacitance dependence were confirmed as follows.

tPHL (when starting C5=OpP(7))”5.48n
sectrzn (when C5=QpFQ)...5.2
3nsecKHL=0.37
nsec/pPKrH...0.38 nsec/pF Furthermore, the level converter 201 in FIG. 27 can obtain desired characteristics for the following reason.

(1) The forward voltage Vr of the barrier diode D is 0.35 to 0.41 volts, and the transistor Q
The base-emitter voltage Vngz of , is mainly 0.75 volts, and the forward voltage VF8 of PN junction diode D is 0.
．． Since it is set to 75 volts, transistor Q,
The voltage input to the level converter 2010 and the hold voltage with which the on/off operation is performed are set as follows.

Vith=-Vrt+Vngz+Lrs 1.09 to 1.15 volts (2) Since the output capacitance Cs is discharged or charged, the output capacitance Cs is composed of bipolar transistors with small output resistance. Switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Since Q+ -Qs is a clamped transistor, its storage time can be reduced.

(4) Drive transistor Q! The change in collector potential of is quasi-C
MOS inverter Mp+s + Mntal Qs
Since it is amplified by +Q+ and transmitted to the output,
The output waveform change speed can be improved.

In the level converter 201 of FIG. 28, the collector load of the transistor Q is not the resistor RI0 but the PN junction diode D, , D,. and a resistance R of 5 kilohms! s K
It differs from the one in Fig. 27 only in that it is structured as follows.
The propagation delay time of the level converter shown in FIG. 28 and its output capacitance dependence were confirmed as follows.

tpsu, (when Cs2QpF) ---6,66
nsectpt, H (when C5=OpF) -4,
16nseCKHL...0
．． 42nsec/pFKLH・”0.37nsec/p
F Furthermore, the level converter 201 in FIG. 28 can obtain desired characteristics for the same reason as in the case of FIG. 27.

The level converter 201 in FIG. 29 is connected to a PNN junction diode D to ensure that the transistor Q is turned off, and to a shield barrier diode B to discharge the base charge of the transistor Q. The only difference from the level converter 201 shown in FIG. 23 is that the level converter 201 shown in FIG.

tppiL (when C5=OpF)...-1,72
nsectpLH (when C5=OpF)・5.4
4nsecKHL…0.32
nsec/pFKLH---0,29nsec/pF Furthermore, the level converter 201 in FIG. 29 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter in Fig. m30 has the resistance ratio in Fig. 29,
is the resistance ratio of 25 kilohms, and the resistance R of 4 and 5 kilohms
2, and the resistor R15 has a ratio W/'L of 2.
P channel MQ set to 4/3 8 F E
The only difference from the one in FIG. 29 is that T M p+ t K is substituted. MPI? acts as an active load element for Q, so the amplifier Q! 1M p+
The pressure detection gain of t becomes an extremely large value.

Regarding FIG. 30 as well, the propagation delay time and its dependence on output capacitance were confirmed as follows.

t PHL (when C5=QpF)...2.2
nsectpLH (when C5=opF') -5,
2n5ecKHL...0.
4 n5ec/pFKLH...0.3 n5ec/p
F Furthermore, the level converter 201 in FIG. 30 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 of FIG. 31, transistors Ql, Q, are clamped transistors, p=Qx, a charging output transistor, Q, 4, NP emitter, 7
Olowa transistor, D, L' shift barrier diode for bell shift.

D is a PN junction diode for level shifting.

is a PN junction diode to ensure that transistor Q is turned off, and D6 is a Schittky barrier diode to block negative noise at the input terminal. Resistance Rho*R,,,R,. are respectively 5Φ rhohm,
It is set to 8k ohm and 20k ohm. The collector signal of the drive transistor Q is a P-channel MO8PE that constitutes a CMOS inverter as a voltage amplifier.
T Mp,, and Nf Janne/l/MO8PET M
The drain output of both MO8FETs is applied to both gates of MO8F'ET M
p.

is applied to the gate of Mp+4 + Mn1< +
MP! 5 local W/L is 24/3, 32/3, respectively.
It is set to 64/3. M OS k' E T
The drain output of M p+ s is applied to the pace of a bipolar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter 201 shown in FIG. 31 and its output capacitance dependence were confirmed as follows.

tp+n, (when C5=OpF)...1.9
4 to 3.84 n5ectpLn (however, C5=opF
' time piece...4.64~5.44 n5ecKl(L
=-0,38n5ec/pF
KLH...0.30 nsec/pF Furthermore, the level converter 201 in FIG. 31 can obtain more desired characteristics for the following reasons.

(1) The forward voltage Vrt of the shield barrier diode D is 0.35 to 0.41 volts, the forward voltage VF2 of the PN junction diode D is about 0.75 volts, the transistor Q, , Q, , Since the pace-emitter voltage vagt I VBE2 + VBE4 of Q is approximately 0.75 volts, the input threshold voltage Vith at which transistors Q, , Q, turn on is as follows.

V1th=-Vgi++Vrz+Vagz+Vagt=
1.5 volts (2) The output transistors Q, , Q, which discharge or charge the output capacitance Cs, are composed of bipolar transistors with small output resistance, so the switching operation speed or propagation delay time and its output capacitance Dependency can be reduced.

(3) Since Q+ and Q* are clamped transistors, their storage time can be reduced.

(4) When the collector potential of the driving transistor Q rises and the charging bipolar output transistor Qs switches from off to on, the CMOS inverter Mp,
4, Mn! 4 amplifies the collector potential change of Q and
, it just transmits to the base of Hana <, MOS FE
The extremely large gate input impedance of T Mp14 and Mnn prohibits a large pace current from flowing directly from the collector of Q to the base of Q, and also allows the base current to flow into the pace of Q through the small on-resistance of MpIll. is supplied, so the output transistor Q,
switching speed can be improved. In FIG. 3, the dependence of the propagation delay time on the output capacitance of the level converters shown in FIGS. 14, 19, 22, and 33 is shown by a dashed line, and It can be seen that the dependence of either one of the propagation delay times on the output capacitance has been improved.

Next, a plurality of CMOS-
The TT Lv to h converters 221, 222, and 22m will be explained. These level converters 221°222
...The essential features of 22m are as follows.

Margin below (1) Each level f converter 221, 222..."・
22m input threshold voltage Vi th is CM
(It is set between J80-level output voltage 0.6 volts and high level output voltage 4.4 volts.

(2) The output transistor that discharges the output load capacitance CX of each level converter 221, 222...22m in response to the input signal supplied to its input terminal is a bipolar transistor in a V configuration. I'm nestling.

Furthermore, the level converter 221.22 of the output buffer 22
The preferred features of the preferred embodiment of 2...22m are as follows.

(3) Discharge output transistor Q. A high input impedance circuit is connected between the output of the internal memory block 21 and the output of the internal memory block 21, which drives the base of the transistor Q1.

(4) The high input impedance circuit in (3) above has a function of logically processing a plurality of output signals of the internal logic block 21.

(5) The discharging output transistor Qjo and the driving transistor QII are constituted by clamped transistors with a shuttling barrier diode.

(6) Output transistor Q that charges the output load capacity fCX
I! is composed of bipolar transistors.

(Power) Discharge output transistor Q+ in response to control signal
It has a function of controlling the output terminal (JUTl) to a floating state by simultaneously turning off O and charging output transistor Q+t.

(8) Level converter 221.222...22
m has an open collector output format.

32 to 34 and 36 Vi show various circuit examples of the level converter 221 of the output buffer 20 according to an embodiment of the present invention, all of which have the above-mentioned (
It has the essential characteristics of 1) and (2). moreover,
These level converters have at least one of the preferred features (3) to (8) above.

%Ql in the level converter 221 of FIG.

is the ninth output transistor that discharges the output load capacitance 'Ik Cx, Q, 1 is Q,. A drive transistor Ql for driving the output load capacitance Ox is an output transistor Q8 for charging the output load capacitance Ox. is the collector signal change of Qll
Current amplification transistor s Rso e R11s Ql4 is the ninth active pull-down circuit that discharges the base charge of Qto.

QIs is a multi-emitter transistor, Ro is Qu
The collector resistance, R1, is a resistance, D, for discharging the base charge of Qll. is a shuttling barrier diode for discharging the base charge of Q, R34 is Q
The resistor to limit the collector current of ltrQIs, approximately the pace a resistance of the QCs.

Furthermore, P channel M (JS
FB'1' MI, M2 and N channel 7kM (JsFE
TM, 0MO8・N A N co-collected from M4 and K
The output of the D gate 211 is applied to the first emitter of the multi-emitter transistor QIs and is applied to the 1os-N
The output of ANp gate 212 is applied to the second emitter of Q4, and the output of 0MO8-NAND gate 213 is applied to QCs
is applied to the third emitter of Therefore, the level converter 221 not only has a level conversion function but also a logic processing function as a three-man NAND gate.

Furthermore, the level converter 221 in FIG. 32 can obtain desired characteristics for the following reasons.

(1) Transistor Q1. The base-emitter voltage v of
agts is about 0.75 volts, Ql, the vane-collector voltage VBC is about 0955 volts, transistor Q
,. +Q++ base-emitter voltage VBE, 10V
Since BEII is approximately 0.75 volts each, the threshold hold voltage Vi t entering the level converter 2210
The settings are as shown below.

Vl th=-VBEls +VBC15+Vag3,
1 +Vagt.

=-0,75+0.55+0.75+0.75=1.3
Volt (2) Output transistor Q, which discharges or charges the output load capacitance Cx of the level converter 221. .

Since Q,1 is constructed from a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Transistor Q+o + Q++ + QCs
+ Ql4 + Since QCs is a clamped transistor, its storage time can be reduced.

(4) Since the multi-emitter transistor QI8 has a logic processing function, it can be used as a master slice type or gate array type logic semiconductor circuit device.
The degree of freedom in design is improved.

However, the level converter 221K of FIG.
kE C1fi, 0 MO8-NAND When the output of gate 211 is low level VC#i resistance Rss * QCs
0 from the power supply voltage VCC through the base-emitter junction of
Ninth, CN08- where a large current of 0.4 milliampere always flows into the output of MO8-NAND gate 211.
NAND gate 211ON channel MO8FETM,
, M, +7) ratio W/Le is set to a large value of 100/3, and the on-resistance ROM must be set to a small value. This not only reduces the reduction in the integration density of the integrated circuit device gLIC, but also both MO8FETM8. The inventor's study revealed that the switching speed of the 0MO8-NAND gate 211 decreases due to an increase in the gate capacitance of M4.

Figure 33 shows a level converter 22117) circuit diagram developed to solve the above problem, in which the multi-emitter transistor Q4 of Figure 32 is replaced by a high input impedance circuit described below. There is.

That is, such a high input impedance circuit FiPNP input transistor Qlf in FIG.

Q, , NPN emitter 7-lower transistor Q+
s + barrier diode 1), ,D, ,
.

Resistance R,. ,R,,,R,,.

Further, the level converter 221 includes a PNP transistor Q,
,,NPN) transistor Q,. , PN junction diode D
,4. Structured by resistance R,, F! It includes a control circuit for controlling the trap output terminal OU'l'' to the 70-setting state when the output terminal is turned on.

pH') transistor Q of this control circuit. The base of
P-channel MO8FETM in internal logic block 21
, and N-channel MO8FEi'M.

It is driven by the enable signal EN of the 0MO8-NAND gate 21 configured by the 0MO8-NAND gate 21.

In addition, the input KV of such 0MO8-NAND gate 211
i Inversion enable signal EN is applied.

Furthermore, since this control circuit is added to the level converter 221, additional P is added to the high input impedance circuit described above.
An NP input input resistor Qn and a Schitter barrier diode DIil are added.

Therefore, when the enable signal EN becomes low level, the transistor Q+op Qu *Q of the level converter 221
Since the ll e QCs are turned off at the same time, their output terminals OU'r are in a floating state.

On the other hand, when the enable signal EN becomes high level, the level converter 22112 as a manual NAND gate also has a logic processing function, so the degree of freedom in designing the integrated circuit device IC increases.

One more step: Toki Barrier Diode DIl ID
I! l Dlg (D forward voltage Vrxte Vylx
+ Vexs Fio, 35 to 0.41 volts,
PNP input input resistor QB r QCs r QCs
Base-emitter voltage VBK17 * vagxs
+ VBE19 H approx. 0.75 h), N
PN transistor Q+o * Qtt + Qt. The base-emitter voltage VBglG, vQgll e
VBJC16 is set at approximately 0.75 volts, e.g. P
0MO8 applied to the base of NP transistor fIQ□
-NANI) With respect to the output voltage of the gate 211, the input threshold voltage Vi th at which the transistors Q101Q and 11 are turned on is as follows.

VHh=-Vszxt +Vagls +VBK11
+Vng1° = 1.5 volts In addition, the output transistor Q+o* which discharges or charges the output load capacitance CX QCs is composed of a bipolar transistor with small output resistance, so the switching speed or propagation delay time and its output capacitance Dependency can be reduced. 9. Transistor Q1゜+Q+t+QCs+ Qt4+ Q+. Since it is a clamped transistor, its delay time can be reduced.

However, similarly in the level converter 221 of FIG. 33, when the output of the 0MO8-NAND gate 211 is at a low level, the PNP input input transistor
The inventor's studies have revealed that the above-mentioned problem cannot be completely solved because a non-negligible current flows from the base of the device into the output of the device 211.

Figure 34 shows that Kfi is used to almost completely solve this problem.
Finally, the multi-emitter transistor Q□ of FIG. 32 is replaced by a high input impedance circuit constructed from KM08FETs as described below.

That is, the corner input impedance circuit in FIG. 34 is an N-channel MO8FETM.

M,! , M, , is composed of a PN junction diode D14. The drain-source paths of M□, MH, and MB are connected in parallel, and each gate is connected to the internal WaMi block,
10 MO8-NAND gate 211, 212° 213
A PN junction diode DI4 is connected in series to these drain-source paths.

I'm sorry, I don't want to resist. , R□, 几. , R-engineer, ordinary! 4*R
81 are 2k ohm and 4k ohm + 10' respectively
? .

It is set to ohm, 4 kilo ohm, 50-75 ohm, and 16 kilo ohm. Transistor Q. .

Each emitter area of QII + QCs + Q10 is
672prr1.132arrf, 363 respectively
arrl, 187ttrr! .

242μrrfVc is added.

Furthermore, in order to further improve the logic processing function of the level converter 221, the drive transistor QC
a second drive transistor Q having the same emitter plane & as s;
,. is connected in parallel with QII, and KN channel MO8P'HTM, 4.
M,,,M,. , PN junction diode D, , resistance 8
．． The level converter 221 constitutes a second high input impedance circuit of 114hX, and has a logic processing function as a six-person complex gate circuit.

Furthermore, when this level converter 221 Kk-1 is supplied with a low level enable signal EN from the internal logic block 21, its output terminal OUT.

A control circuit for controlling the 70-ting state is also added. This control circuit is an N-channel MO
8FETM... Transistor Q! I+Q*t+
QCs p resistance R6゜, 几, 2.几4! l ”43
m7 barrier diode I) tel 1)
+t e I)ta tDl. It is made up of.

Furthermore, in the level converter 221 of FIG.
M Q S F E T M II...M
, input threshold 1 hold at each gate of 6 [pressure CMOS low level output voltage 0.6 volts and 0M08]
The intermediate value between 1 level output voltage 4° and 4 volts is 2.5
The ratio W/L of the 9th, M, . . . M, 6 is set in the bolt as follows. Furthermore, at this time, MI
The threshold voltage VTH of l...MI is approximately 0.7
5 volts, the forward voltage VF14 of the PN junction diode D,4 is set to 0.75 volts, and Ml
l...Mteo channel conductance β
. It is set to [60X10-'[1/ohm].

Consider the case where only MO8FETM is on, and calculate its gate voltage VX, gate-to-source voltage VG'l+drain relaxation ID+drain voltage VY, etc. At this time, it is assumed that M and Fi are biased in the saturated region.

Vx = Vas + VFI 4
...(1) VY"'VCC'R'ss
'10 From equations (1) and (2), ... (3) Vy=Vam11+Vagx.

From equations (3) and (5), ... (5) From equations (4) and (6), ... (force Vcc is 5 volts * VBE11 and VBEIO are 0.7
5 volts, R5, 16 kohm, β0 60X10
-・[1/Ohmco, Vx is 2.5 volts + ■F14 is 0.75 pol) When the condition of IVTH is 0.75 volts is inserted into the above equation (7), 1 By the way, as Vx increases, Vy increases. The transistor Q, drops. + V who is busy dealing with Qo being turned off
Consider X as the input threshold voltage.

Transistor Q. The drain voltage vY at which +Q++ is turned off is determined as follows.

=7.29-Thus, the ratio W/L of Mll...M, 6 is 22
/3, the input threshold voltage of the level converter 221 can be set to ? 2.5 volts [2 O] In the embodiment of FIG. 34 having the above configuration, #-1,
The present inventor has confirmed that the propagation delay time and its output capacitance dependence are as shown below.

tpHx, (7 and C5=OpFO) - mark 8.8
nsecIpLn (when f/- and C5=OpF)
=--7,8n5ecKHL ==
0; H, n5e6 / pFK LH”'”' 0
:01'n5ee/pF In FIG. 5, the dependence of the propagation delay time of the level converter of the embodiment in FIG.
The propagation delay time jPHL and the output capacitance dependence KHL of 1PLH.

It can be seen that KLH has been improved.

9. The level converter 221Fi shown in FIG. 34 can obtain the desired characteristics for the following reason.

(1) As mentioned above, transistors Q1゜, Q3. Pace-emitter voltage V B 110 * V B B
11, power supply voltage Vcc, resistance hole 8. , I
QI (J S 1;”E 'l'M,,・M,.

By setting the ratio W/L of MO8FBTM, . The input threshold voltage of 221 can be set to 2.5 volts between 0.6 volts) (!: 4.4 volts).

(2) Discharging and charging the output load capacitance Cx 1! The output transistor Q, which performs. , QII is constructed of bipolar transistors with small output resistance, and can reduce switching operation speed or propagation delay time and its dependence on output capacitance.

(3) Between the base of the drive transistor QII and the output of the internal logic block 21 is connected the gate of the MO8FETM, . The current flowing into the output of the 0MO8-NAND gate 211 of the internal logic block 21 can be reduced to a negligible level, and a significant increase in the N-channel MO8 FETO ratio W/L of the 0MO8, NAND gate 211 can be prevented. .

(4) MO8FETM high input impedance circuit,
.

Since Ml, , M, performs the three-man OR&ii+ logic, the logic processing function of the level converter 221 is improved.

(5) Two drive transistors Q+t+Q*. also AND
By executing the logic, the logic processing function of the level converter 221 is further improved.

(6) Transistor Q+o * Qtt + Qu +
Qt4 e Qt.

Since it is a clamped transistor, its storage time can be reduced.

(By setting the enable signal EN to low level, the output transistor Q1 of the level converter 221.

Qtt is turned off at the same time, and the output terminal OUT becomes a floating state. When this output terminal 0UT1 is connected to the output terminal of another logic circuit that does not cause fire or water, and the next parallel operation is performed, the signal level of this output terminal OUT is set within the limit. It can be made unrelated to the output of the W5 logic block 21.

FIG. 36 shows a level converter 22 according to another embodiment of the invention.
An example of circuit No. 1 is shown, and its output terminal u u 'r.

is commonly connected to the output terminal of another open collector output type semiconductor integrated circuit device C' for TTL level logic,
This common connection point is a 2K ohm load resistor hole. . It is connected to a 5 volt power supply voltage Vcc via a power supply voltage Vcc of 5 volts.

The open collector output type T'1' L level circuit device IC' includes, but is not particularly limited to, shuttling barrier diodes D, D, D, multi-emitter transistor Q40 + clamped transistor Q4.
s to Q44. The resistor (2) is also composed of 0 to R4, and a PN junction diode D4VC. However, while the collector of the output transistor Q4S is connected to the 43rd terminal as an output terminal as an open collector output,
Inside the circuit arrangement IC', any circuit element is connected to the power supply voltage Vcc and the output transistor Q4. is not connected to the collector.

In the level converter 221 of FIG. 36, the circuit device I
The level converter 221 is formed exactly the same as the level converter 221 shown in FIG. 34, except that no circuit element is connected between the power supply voltage Vcc and the collector of the output transistor Q+6.

Thus, the output terminal of the circuit device IC and the output terminal of the circuit device IC' are connected in the form of a so-called wired zero-circuit circuit. Furthermore, by setting the enable signal EN to a low level, the output transistor Qso of the level converter 221 is forcibly turned off, and the output terminals 0tJT and
can be made independent of the output of internal logic block 21.

FIG. 37 shows the layout of each circuit block on the surface of a semiconductor chip of a logic semiconductor integrated circuit device IC according to an embodiment of the present invention.

The central part of the semiconductor chip 300 (break1IsloVC1I!
tI area) K is 0M08 circuit (pure CMOS circuit,
The upper side of the semiconductor chip 300 (the area surrounded by the broken line!) K is connected to the input level converter (the inside is shaded inside) of FIG. In addition, a plurality of output level converters (indicated by white triangles) shown in FIG. (area surrounded by line 71), lower side (area surrounded by &1. line 71).

On the left side (area FIJAed by mis), there are a plurality of input level converters shown in Fig. 31, respectively.
! A plurality of output level converters shown in FIG. 34 are arranged alternately.

Upper part! , there are a number of input bonding pads (indicated by thick solid rectangles) corresponding to the number of input level converters, and output bonding pads (indicated by thin solid lines) corresponding to the number of output level converters. (shown as a rectangle) are arranged, the input part of each input level converter faces each input bonding pad, the output part of each input level converter faces the internal logic block 21, and each output level converter The input of each output level converter faces the internal logic block 21, and the output of each output level converter faces a respective output bonding butt.

Multiple human power pounding pads and multiple output pounding pads on the right side of the right side Mlt, lower side! , a plurality of input bonding pads and a plurality of output bonding pads under , and a plurality of input bonding pads and a plurality of output bonding pads of the left if of the left side part 14 are the same as in the case of the upper side part l. are similarly arranged.

Right side part 12e lower side part! 8. The orientation of the input/output part of the input level converter in the left side part 14 and the orientation of the input/output part of the output level converter in the left side part 14 are the upper part l, respectively.

The same is true for .

111, a power supply bonding pad 30 for supplying the source voltage Vcc is arranged on at least one of the four etched portions of the semiconductor chip 300, and a grounding bonding pad 31 for connecting to the ground potential point It is arranged in at least one of the four etched parts.

The semiconductor chip 30 having the layout shown in FIG.
0 is physically and electrically connected to the surface of the tab lead LT of the gold 141J-deframe LP shown in FIG. 38.

In the lead frame L shown in FIG. 38, the lead portion L corresponds to the upper right portion of the lead frame LyF1 semiconductor chip 300. , has a frame portion Lo+a diagonally shaded dam portion LD. However, in reality, the same applies to the parts corresponding to the lower right, lower left, and upper left of the semiconductor chip, so the lead frame LrV'i is the part defined by the diagonally shaded dam part L'+1+ lead part R, ~L64 ．． This is a thin metal plate having a structure in which tab leads LT are connected to each other.

After the back surface of the semiconductor chip 300 is connected to the front surface of the tab leads L, the following bonding wires (for example, gold wires or aluminum wires) are wired.

By using a commercially available wire bonding device, the power supply bonding pad 30 and the lead portion Lts4 are electrically connected by the wire j6, and then the wire Is K, j:v input pad and the lead are connected in sequence. The output pad and the lead part are connected by the wire Is, the input cover is connected by the wire Is, and the output pad and the lead part Is are connected by the wire 1. Input pad and lead part from wire 1IGK,
The grounding bonding pad and the tab lead LT are electrically connected by the wire g++.

Lead frame LT after the above wire wiring is completed
The semiconductor chip 300 and the semiconductor chip 300 are delivered to a mold for resin sealing, and liquid resin is injected into the inside of the time portion LD of the lead frame L. This dam portion LI5 prevents the resin from flowing out.

After the resin has solidified, the lead frame L, the semiconductor tip 300, and the resin, which have an integrated structure, are taken out from the mold, and the dam part LD is removed using a fress machine or the like. , ~La4 can be electrically isolated O. Each lead L, ~L64 protruding to the outside of the anabolic resin can be bent downward as necessary, as shown in the completed diagram of FIG. A logic semiconductor integrated circuit device IC sealed with resin 301 is completed. As shown in the figure, such a circuit device IC does not include a special heat dissipation fin for actively dissipating heat generated from the semiconductor chip 300 to the outside of the sealing structure.

If such heat dissipation fins are installed, the circuit device IC
costs increase undesirably.

In addition to the above-mentioned resin sealing method, there are also ceramic sealing methods and methods using a metal case as a method for sealing a semiconductor chip, but from the point of view of the cost of the circuit device IC, the above-mentioned methods are considered. The resin encapsulation method is the most advantageous.

In the logic semiconductor integrated circuit device IC according to the embodiment using the drawings of FIGS. 37 to 39, the input buffer 2
Input level converter 201 as 0.

202...The total number of 20n is 18 to 50. CMOS gate 211゜212 as internal logic block 21
...The total number of 211 is 200-1530. Output level converter 221゜222 as output buffer 30
...Total number of 22m is 18 to 50 and 3 semiconductor chips
Although 00 is a large-scale semiconductor integrated circuit device, the circuit device IC is not equipped with a heat dissipation fin for the following reasons.
It was possible to create a response structure.

In other words, the power consumption of each 0M08 gate 211, 212...21/ as the internal logic block 21 is extremely small at 0.039 milliwatts; The power consumption of the entire 21 is extremely small at 7.8 to 59.67 milliwatts. W, each input level converter 201, 202 as input buffer 20 according to the embodiment of FIG.
Since the 2On contains many bipolar transistors, the power consumption per each converter is as high as 2.6 milliwatts, and the total power consumption Vi of the input buffer 20 with 18 to 50 converters is 46.8 to 130 milliwatts. It's big.

Since each output level converter 221, 222, . . . 22m as output buffer 20 according to the embodiment of FIG. As large as .8 milliwatts,
The total power consumption of the output buffer 22 having 18 to 50 converters is as large as 68.4 to 190 milliwatts.

From the above data, the input buffer 20. of converters is 18.
21° internal logic block with 200 gates and 18 converters
In the circuit device IC of the output buffer 22, the 37th
In the central part 1o of the semiconductor chip surface in the figure, 6.4% of the total heat is generated, while in the comparative part 18. lx
,ls-A! 4 A total of 93.6 percent of the heat is generated.

Please note that the input buffer 20 of the converter 50. Number of gates: 153
0 internal logic block 21. In an output variable 220 circuit device IC with 50 converters, 15.8% of the total heat is generated at the central portion 1o of the semiconductor chip surface as shown in FIG. 84.2% of the heat is generated.

By the way, as shown in FIG. 37, the internal logic block 21 that generates a small amount of heat is located in the central part of the chip! . The input buffer 20 and the output buffer 2 are located in the
2 means each side of the chip/I11* *Is e 14
K is arranged, so from FIG. 38, each side It, /!
, Is, 14 is transferred to the circuit device I via the tab lead LT and the lead portion Lt' serving as the grounding lead.
The circuit device is not connected to the outside of C (particularly to the earth line of the printed circuit board when a printed circuit board VCIC is mounted), but is connected to a large number of bonding wires and each lead part...L64. Outside the IC (
In particular, when 10 is mounted on a printed circuit board, it can be taken out to the signal line and power supply line of the printed circuit board.

Contrary to the above embodiment, if the input buffer 20 and output buffer 22, which generate a large amount of heat, are placed in the central part to of the chip, and the internal logic block 21 is placed around the central part lo, then the central part! . It has been confirmed through calculations by the inventor that a large amount of heat is not easily extracted to the outside of the circuit device IC.

For the above reasons, since the circuit device IC of the above embodiment has a resin-sealed structure, it has become possible to significantly reduce the cost of the IC.

FIG. 40 shows a logic semiconductor integrated circuit device IC and other TTL level logic semiconductor integrated circuit devices 401.
. . 40n, 501 to 505°600 are mounted on a printed circuit board to form a block diagram of an electronic system.

In the fourth time, a device 401 with TTL level output
, 402...40n are respectively supplied to the inputs IN, , IN,...INnK of the circuit device IC, and the outputs of the circuit device IC are connected to the TTL human power level device 5.
It is supplied to the inputs of 01...505.

Furthermore, by commonly connecting the output o'r of the circuit device IC and the output of the device 600, the output of the circuit device IC, 600
0 executes parallel operation.

A large amount of heat generated in the input buffer 20 and output buffer 22 of the circuit device IC can be dissipated to the ground line, power line, input signal line, and output signal line of the printed circuit board.

Also, an enable signal E supplied to the output buffer 22
When N is set to low level, its output OUT, 0LJ
T,...OUTm is in a floating state, and the input level of devices 1501, 502, and 503 is device 6.
Set by an output level of 00.

Also, input buffer 20! ! ! 401,402...
...High speed is obtained at the interface between the internal logic block 21 and the input buffer 20, and high speed is obtained at the interface between the internal logic block 21 and the input buffer 20, and the output buffer 22
A high speed is obtained at the interface between the internal logic block 21 of the device 1501...505 and the output buffer 2o.

[Effects] According to the above embodiments, favorable effects can be obtained for the following reasons.

(1) By configuring the output transistor that charges or discharges the output capacitor C3 of the input level converter 201 with a bipolar transistor, MO8
Compared to a FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, so that a large charging, current or discharging current can be obtained, which reduces the propagation delay time of the input level converter and its output. Capacity dependence can be reduced.

(2) In the input level converter 201VC, a Schottky barrier diode is connected between the base and the collector of the bipolar transistor driven into the saturation region to perform a multiplicity carrier operation. Since injection of minority carriers from the collector layer into the paste layer can be reduced, the accumulation time can be reduced.

(3) Input level converter 20 according to a preferred embodiment
1, the drive transistor Q is connected via a MOS buffer with high input impedance and voltage amplification function.
By transmitting the pace signal or collector signal of t to the pace of the charging bipolar output transistor Q8, the operating speed of the output transistor Q is improved due to the high input impedance and voltage amplification function of this MO8 buffer.

(4) In the input level converter 201 according to the preferred embodiment, a PNP emitter/7-rower ψ transistor Q and a PN junction diode D4 are connected between the input terminal IN and the drive transistor Q. Not only can the input level converter 201 input level converter 201 and hold voltage be set appropriately, but also the (PNP) transistor Q,
Since the input impedance at that pace improves due to the current amplification effect of P, the T connected to the input terminal INIK
The influence of the output intensity of the TL level signal source can be reduced.

(5) By configuring the output transistor that charges or discharges the output load capacitance Cx of the output level converter 221 with a bipolar transistor,
Compared to FE'l', the Bibo2 transistor has a small output resistance and a large current amplification factor even though the element size is small, and a large charging current or discharging current can be obtained, which reduces the propagation delay time of the output level converter. And its dependence on output capacitance can be reduced.

(6) In the output level converter 221, a barrier diode that performs majority carrier operation is connected between the base and collector of the bipolar transistor driven into the saturation region; Since the injection of minority carriers from the collector layer into the paste layer can be reduced, the accumulation time can be reduced.

(7) In the output level converter 221 according to the preferred embodiment, the output of the internal logic block 21 and the drive transistor Q8. There is a high input impedance between the pace of M
When the O8 circuit is connected, the MO of this MO8 circuit is
Since the current flowing from the gate of the 81i'ET to the output of the internal logic block 21 can be reduced to a negligible level, it is possible to prevent a decrease in the integration density and a decrease in the switching speed of the output circuit of the internal logic block 21. (8) In the output level converter 221 according to the preferred embodiment, the high input impedance MO8 circuit is provided with a function of logically processing a plurality of output signals of the internal logic block 21, so that the output level converter 221 can be implemented using a master slice method or a gate array method. The degree of freedom in designing the logic semiconductor integrated circuit device IC can be improved.

(9) In the output level converter 221 according to the preferred embodiment, Fi is set to the output terminal O by the enable signal ENVC.
Since a control circuit is arranged to control the UT to a 70-setting state, this output terminal 0UT1 and the output terminals of other logic circuits are commonly connected, and in the case of 1, the level of this common output terminal is changed to another. It can be set by the output of the logic circuit.

α1 According to a preferred embodiment, the power consumption is reduced by constructing it with a pure CMOS circuit or a quasi-CMOS circuit, and the internal logic block 21 is placed in the center of the semiconductor chip surface, and a plurality of bivok transistors are arranged. Input level converter 201 with large power consumption
... and the output level converter 221 on the periphery of the semiconductor chip surface, heat dissipation is facilitated. We were able to reduce costs.

αυ According to the preferred embodiment, since the logic semiconductor integrated circuit device IC has a resin-sealed structure, its cost can be reduced.

(On the other hand, the input terminal IN of the input level converter 201,
is not applied to the gate of the MOSFET, but rather to the cathode of the switch barrier diode D, or PN
Since the voltage is applied to the pace of the P transistor Q, it is possible to improve the breakdown strength against the surge voltage applied to the input terminal IN.

Although the nine inventions made by the present inventors have been specifically explained based on Examples, the present invention is not limited to the above-mentioned Examples and does not depart from the gist thereof.

For example, in FIG. 6, the level converters 201, 202...2On of the input buffer 20 are ECL-0
M08 level conversion t- executed, level converter 221,222...22m of output buffer 72 is 0MO8
- It can also be configured to perform ECL level conversion. Therefore, K is input buffer 20. Internal logic block 21. It goes without saying that it is sufficient to operate the output buffer 22 at the ground level and the negative power supply voltage -V. Similarly, in FIG. 6, the level converters 201, 202-...20nt of the input buffer 20
:t i" L -0 MO8 level conversion is executed, and level converters 221, 222""22 of the output buffer 22
It is also possible to configure it to perform mViCMOS-i''L level conversion.

Furthermore, in the embodiments shown in FIGS. 14 to 21, 23 to 26, and 29 to 30, the PNP emitter 7 lower transistor Q, PN
Junction diode D! may be added.

The reason why the ratio W/L of MOIPET is set to 3 per minute is because the channel length of MO8F'ET is 3 μm, and currently, due to improvements in photorinography, this channel length is 2 μm.

As miniaturization progresses to 1.5 μm and below K I Am, the ratio W/L will decrease correspondingly.

Along with this miniaturization, the device dimensions of bipolar transistors will continue to be reduced, and the resistance values of resistors in the circuit will also change.

A large number of leads L, . . . L6 of the sealing resin 301 and
The method of taking out No. 4 is also not limited to the embodiment shown in FIG. 39.

Making the outer shape of the sealing resin 301 almost square rather than rectangular and taking out a large number of leads L1...L, 4 from all four sides is more appropriate for downsizing the lead frame LT and circuit device IC, and is suitable for ToD and printing. The packaging density on the board is improved.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to a logic semiconductor integrated circuit device, but the present invention is not limited thereto.

For example, on a semiconductor chip there is an input buffer 20° and an internal logic block 21. Output buffer 22 as well as bipolar analog circuitry as required.

MOS/analog circuit, P channel 8/108/logic, N channel MO8/logic, 1! L times.

It goes without saying that either the ECL circuit or the ECL circuit can be arranged on a semiconductor chip.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a logic semiconductor integrated circuit device IC that was studied by the inventor of the present invention prior to the present invention. 3 shows the output capacitance dependence of the propagation delay time of the input buffer shown in FIG. 2, and FIG. 5 shows the dependence of the propagation delay time of the output buffer in FIG. 4 on the output load capacitance; FIG. Figures 7 and 8 are 0MO8-NA of the circuit device in Figure 6.
A circuit example of the ND gate 211 is shown, and FIGS. 9 and 10 are the circuit device c st of FIG. 6. 11 and 12 show an example of the circuit of the S, NOR gate 211, and FIG. 11 and FIG.
FIG. 13 shows a circuit example of the 0MO8 gated S clip-flop in the internal logic block 21 of the circuit device of FIG. FIGS. 14 to 31 show the features of the present invention! 11! 32 to 34 and 36 are various circuit diagrams of the level converter 2210 of the output buffer 21 according to the embodiments of the present invention. FIG. 35 shows the first and second propagation delay times of 1 PHL. FIG. 37 shows the layout of each circuit block on the surface of the semiconductor chip of the logic semiconductor integrated circuit device according to the embodiment of the present invention, and FIG. A lead frame L of a semiconductor chip of a logic semiconductor integrated circuit device according to the embodiment. 39 shows a completed diagram of the circuit device according to the embodiment of the present invention after resin sealing, and FIG. 40 shows the state of connection of the circuit device to the tab lead LT and the bonding wire. 1 shows a block diagram of an electronic system configured by mounting the circuit device according to the embodiment and other circuit devices on a printed circuit board. D- Figure Figure ■ Figure Figure Figure 16 Figure Right Figure Figure T Figure ■ Figure zO/ Figure 20 Figure 22 Figure 23 Figure 24 Figure 25 Figure 32 Figure Figure Figure 26 Figure 27 Figure Figure 30 Figure Figure 34 Figure Figure 37 Figure Figure 40

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising an internal logic block having a plurality of logic gate circuits including at least a CMOS circuit, and an input circuit including a bipolar transistor for driving the input of the internal logic block. A device,
A semiconductor integrated circuit device characterized in that the plurality of logic gate circuits are connected to each other by a gate array method. 2. A semiconductor integrated circuit device comprising an internal logic block having a plurality of logic gate circuits including at least a CMOS circuit, and an output circuit including a bipolar transistor and receiving an output of the internal logic block, the semiconductor integrated circuit device comprising: A semiconductor integrated circuit device characterized in that gate circuits are connected to each other by a gate array method. 3. An internal logic block having a plurality of logic gate circuits including at least a CMOS circuit, an input circuit including a bipolar transistor for driving the input of the internal logic block, and an output including the bipolar transistor and receiving the output of the internal logic block. 1. A semiconductor integrated circuit device comprising a circuit, wherein the plurality of logic gate circuits are connected to each other by a gate array method.