JPS59139725A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce both the delay time of transmission and the dependency on capacity for a semiconductor IC device by providing an input buffer for TTL- CMOS level conversion and an input buffer for CMOS-TTL level conversion and using a bipolar transistor to the output of a buffer converter. CONSTITUTION:A semiconductor IC device is provided with an input buffer 20 for TTL-CMOS conversion, an output buffer 22 for CMOS-TTL conversion and an internal logical block 21 which works at the CMOS level. The input signals IN1-IN19 of TTL levels are converted into CMOS levels by level converters 201-20n of the buffer 20. These converted signals of CMOS levels are applied to each logical gate of the block 21. Then bipolar output TRs Q1 and Q2 are used to charge or discharge the output capacity CS of each of converters 201-20n of the buffer 20. This device reduces both the delay time of transmission and the dependency on capacity and increases the working speed of the semiconductor IC device.

Description

Detailed Description of the Invention [Technical Field J° The present invention relates to a semiconductor integrated circuit device, for example, an input/output level is a TTL level and an internal logic level is a CM
The present invention relates to a technology that is effective for use in OS-level logic semiconductor integrated circuit devices.

[Background Art 1 Figure 1 shows that the input/output level is TTL level, which was studied by the inventor of the present invention prior to the present invention.
1 shows a block diagram of a logic semiconductor integrated circuit device IC whose internal logic level is CMOS level.

Such a circuit device IC receives a TTL level input signal I N=
, I N2 ---- Input buffer 10 for level converting I Nn to a CMOS level signal. Internal logic block 11 for performing logical arithmetic operations at CMOS level. It includes an output buffer 12 for level converting the CMOS level output signal of this internal logic block 11 to a TTL level output signal, and each circuit 10, 11, 12 is supplied with a power supply voltage Vcc of 5 volts and , properly grounded.

Input terminals IN, lN2 of the input buffer 10---I
High level input voltage V supplied to Nn! H16 is 2
．． This low level input voltage ViL, which is higher than 0 volts.

(It is set to 0.8 volts or less. Therefore, the input threshold voltage V+tll+o regarding the input terminals IN, , IN2--INn of the input buffer 10 is 0.8 volts or less.
It is set at 1.3-1.5 volts between 8 volts and 2.0 volts.

On the other hand, a high level output voltage VOH+ obtained from the output of the input buffer 10. is set equal to the high-level input voltage V in, + h of the internal logic block 11, and the low-level input voltage VO obtained from the output of the input buffer 10
L.I. is the low level input voltage V of the internal logic block 11
it, ++. Therefore, the threshold voltage of the P-channel MO8FET constituting the CMOS inverter in the internal logic block 11 is set to Vtp,
If the threshold voltage VTNI power supply voltage of N-channel MO3FET is Vcc, the above voltage VO)1
101 V; HllT VOLIOIV it, + +
are set as follows.

Vou+o=Vin mouth >Vcc-IVtpl
---(1) Vot, +o=ViL++<Vt
N ----(2) Vcc to 5 volts II
If VTPI is set to 0.6 volts and IVTN is set to 0.6 volts, Von+o and V io+ + are set to 4.4 volts or less, and VOLIO and V iL+ + are set to 0.6 volts or more.

Therefore, the input logic threshold voltage Vith++ of the CMOS inverter within the internal logic block 11
is set at approximately 2.5 volts between 0.6 volts and 4.4 volts.

Similarly, the high level output voltage V of the internal logic block 11
High level input voltage of ou++ and output buffer 12■1
H12 is set to 4.4 volts or more, and the low level output voltage of the internal logic block 11 is set to voL8. and the low level input of the output buffer 12 is the voltage V i L12 which is 0.6
The input logic threshold of output buffer 12 is set below volts.

2 is set at approximately 2.5 volts between 0.6 volts and 4.4 volts.

The high level output voltage VOH of the output buffer 7712 is set so that the output rose 7712 generates a TTL level output signal.
+2 is 2.7 volts or more, its low level output voltage V
OLI2 is set to 0.5 volts or less.

FIG. 2 is a circuit diagram showing one of the input buffers 7T10 studied by the inventor of the present invention prior to the present invention.
It is constituted by O8FETMn+*Mn2+ Mnzt resistor Rp. The gate, source and drain of each MO8FET are respectively designated by the symbol g+ Std.

The first stage CMOS inverter made up of Mp+ and Mn and the second stage CMOS inverter made up of M112 and Mn2 are connected in cascade, and Rp and Mn3 connect the gate insulating films of Mpl and Mn+. Configure a gate protection circuit for protection. The output capacitance Cs connected to the drains of Mp2 and Mn2 of the second stage CMOS inverter is actually the drain capacitance of M+)2 and Mn2,
Its value is determined by the open wiring stray capacitance between the output of the input buffer 10 and the input of the internal logic block 11, and the input capacitance of the internal logic block 11.

Each MO8FET M+)+t Mp21 Mn1l M
The ratios W/L of channel width W and channel length of n21 Mn are 27/3, 5.42/3, and 126/, respectively.
3.5.42/3.15/3, and the resistance Rp is 2
It is set to a value in kiloohms.

FIG. 3 shows the propagation delay time tp of the input buffer 10 in FIG.
The dependence of oL, tpt, and H on the output capacitance Cs is shown, the vertical axis shows the propagation delay time, and the horizontal axis shows the output capacitance Cs.

As shown in FIG. 35, the first propagation delay time tpML changes from the 50% value of the input INPUT to the 50% value when the output 0UTPUT changes from high level to low level. The second propagation delay time tpLH is defined as the time from input INPU to
Output 0UTPUT after T changes around 50% value
It is defined as the time it takes for the signal to change from a low level to a high level with the 50% value as the boundary. still,
In FIG. 35, tr is defined as fall time, and tr is defined as rise time.

Thus, as can be understood from FIG. 3, the output capacitance dependence KHL (=Δtput, /ΔCs) of the first propagation delay time tpHL of the input buffer 10 in FIG. 2 is approximately 0°8.
Output capacitance dependence KLH (=Δtpu+/ΔCs) of nsec/pF+second propagation delay time tpLo is approximately 1.4ns
Both ec/pF become large.

For input buffer 7710 of FIG. 2, its input threshold voltage Vith+. MI of the first stage CMOS inverter to set the voltage to approximately 1.3 to 1.5 volts)
Ratio of channel width and channel length of I and Mnl W/
L is greatly different, and the propagation delay time tp+n,...
Mo2 and M of the second stage CMOS inverter are
Mo
The channel length fundance of Mn2 and Mn2 is increased.

In order to reduce the dependence of both output capacitances KHL and KLH, the ratio W/L of Ml)2 and Mn2 in the second stage CMOS inverter can be increased rapidly, but this is because the This results in a significant increase in the area occupied by the input buffer 10, which hinders improvement in integration density.

In other words, although miniaturization is currently being vigorously promoted in the manufacturing technology of integrated circuits, the lower limit of the channel length of MOS FET is 3 μm in the current photolithography using ultraviolet exposure, and the ratio W/L of MOS FET is In order to make the value extremely large, the channel width W must be made extremely large, and ultimately the MO
This is because the area of the S FET element region is significantly increased.

On the other hand, FIG. 4 is a circuit showing one of the output power 7712 studied by the inventor of the present invention prior to the present invention, and is a P-channel MO8FET M, 4. N channel M
It is composed of OS FET Mn4. Each MO
The gate, source, and drain of the 8FET are each marked with the symbol g.
* Indicated by sg d.

CMOS of internal logic block 11 in integrated circuit device IC
The level output signal is MD4 and Mns of the output buffer 12.
A power supply voltage Vcc of 5 volts is supplied to terminal No. 30, which is applied to the gate of the .

Therefore, in order to set the input logic threshold voltage Vith+2 of the output buffer 12 to approximately 2.5 volts, the ratio W/L of M+)4 and Mn4 is set equal to each other.

In Figure 4, the TTL circuit 14 is shown as in 1.
This circuit 14 is supplied with a power supply voltage Vcc of 5 volts through a terminal No. 35. The output signal of the output buffer 12 at the TTL level is obtained from the 20th terminal, and is supplied to one emitter of the multi-emitter transistor Q1 of the TTL circuit 14 via the 32nd terminal.

On the other hand, as a TTL circuit, it is a standard type TTL circuit.

Schottky TTL circuit, low power Schmitt*TT
IJIfl, Advanced Low Power Schottky TTL circuits have been announced, and their characteristics are, of course, somewhat different from each other.

In addition, the output of the output rose 7712 is transmitted to a large number of TTL circuits 14.
inputs must be driven simultaneously and in parallel. One measure of this driving ability is that it is possible to drive 20i inputs of a low power switchboard TTL circuit in parallel.

When the output of the output rose 7712 is low level, the low level
0.0 from one input of the power Schottky TTL circuit.
The low level input current IIL of 4mA is output from the output buffer 12.
The current flows into the drain-source path of the N-channel MOS FET Mn4. Therefore, in order for the output buffer 12 to drive the 20 inputs to low level as described above,
Mn4 requires a total of 8 mA to flow.

On the other hand, the low level output voltage VOL1 of the output buffer 12
As explained above, 2 must be less than 0.5 volts! 1, so the N-channel MOS of the output buffer 12
On-resistance ROM of FET Mn4 is 0°5 volts/8
It must be set to a small value, such as milliampere = 62.5 ohm.

In this way, in order to make the on-resistance ROM of Mn4 a small value, the ratio W/, L of Mn is set to 700/3 to 100.
It must be set to an extremely large value of 0/3. On the other hand, as described above, in order to set the input logic threshold voltage Vith+2 of the output buffer 12 to approximately 2.5 volts, Mp4 and Mn.

Since the ratios W/L of both must be equal, the ratio W/L of the P-channel MO8FET MI 14 of the output buffer 12 must also be an extremely large value of 700/3 to 1000/3.

This also results in a drastic increase in the area occupied by the output buffer 12 on the surface of the integrated circuit chip, which only hinders the improvement of integration density, but also reduces the switching speed of the internal logic block 11 for the following reasons. This results in a significant decline.

In other words, both MO8FETMp4v of the output rose 7712
If the ratio W/L of Mn4 is both set to a large value, both MO
The date capacitance of 8FET Mp<s Mn4 also becomes a proportionally large value. Since these date capacitances of M+)41Mn4 become the output load capacitance of the internal logic block 11, the output resistance of the internal logic block 11 and these date capacitances cause a reduction in the switching speed of the internal logic block 11.

On the other hand, the output of the output buffer 12 is not only led out as an external output terminal (terminal 20) of the integrated circuit device IC, but also connected to the input terminals of a large number of TTL circuits 14 via external wiring. Output load capacity Cx
is often an extremely large value.

Figure 5 shows the output load capacitance Cx of the output buffer 12 in Figure 4.
The graph shows the dependence of propagation delay times tpot, tpLo on , the vertical axis shows the propagation delay time, and the horizontal axis shows the output load capacitance.

As can be understood from FIG. 5, the capacitance dependence KHL (=Δtpnt/ΔCx) of the first propagation delay time tpo+ of the output buffer 12 in FIG. 4 is approximately 0.3 ns.
The capacitance dependence Kto (=ΔtpLu/ΔCx) of ee/pF, second propagation delay opening tpt, and o is approximately 0.17 nsec
/pF, both become large.

Therefore, the input power 7 in FIG. 2, which is the background art of the present invention,
The problems of 710 can be summarized as follows.

(1) In order to reduce the dependence of the propagation delay time of the input rose 7710 on the output capacitance, both MO3FETs Mp2@Mn of the second stage CMOS inverter of the input cover 7A10 must be
The ratio W/L of 2 must be increased, which is an obstacle to improving the integration density. In particular, if the integrated circuit device IC is of the master slice type or semi-custom gate array type, there is a possibility that an extremely large number of data input terminals in the internal logic block 11 are connected to the output of the input buffer 10. , when the output capacitance Cs of the input pin 7a 10 becomes extremely large, the above problem becomes extremely serious.

(2) Furthermore, since the first stage of the input terminal 7a 10 is composed of CMOS inverters Mp1+Mnl, even if a gate protection circuit composed of Rp and Mns is connected, the voltage applied to the input terminal IN is The breakdown strength of the gate insulating films of both MO8FETs against surge voltage is not sufficient.

In addition, output para 77 in FIG. 4, which is the background art of the present invention.
The 12 problems can be summarized as follows.

(3) In order to set the input logic threshold voltage VitTo□ of the l buffer 12 to approximately 2.5 volts and to increase the current sinking ability of the output buffer 12 during low level output, both MO8FET M+)41
The ratio W/L of Mn4 must be both equal and large, which hinders the improvement of the integration density.

(4) Both MO3FETs of the output buffer 12 Mp=.

When the ratio W/L of Mn< is increased, both Mp<r Mn
.

The dating capacity of will also increase. Therefore, the output resistance of the internal logic block and these date capacitances result in a reduction in the switching speed of the internal buried block 11. In particular, the output stage of the internal logic block 1j is a MOS with a large output resistance.
In the case of a FET, this reduction in switching speed becomes a significant problem.

(5) The output buffer 12 is a MOS FET Mp.

Mn, the propagation delay time has a large dependence on the output load capacitance C×. This problem becomes particularly important when the output of the output buffer 12 is connected to the input terminals of a large number of TTL circuits 14.

[Objective of the Invention 1 The object of the present invention is to provide an internal logic block that generates a CMOS level output signal by applying a CMOS level input signal, and a TTL-CMOS level conversion for this internal logic block. In a semiconductor integrated circuit device having a human cover sofa for level conversion such as 77 and/or an output buffer 7 for level conversion such as CMO3-TTL level conversion, it is possible to improve the integration density, and the above-mentioned human cover 77 and/or the above Output bag 7
The object of the present invention is to reduce the dependence of the operating speed of the motor on the output capacitance and to improve the operating speed.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, in a level converter for a TTL-CMOT level converter cover for an internal logic block operating at a CMOS level, the output transistor that charges or discharges the output capacitance of the level converter is a bipolar transistor. By configuring M
Compared to an OS FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of the input buffer and its capacitance dependence It becomes lighter by achieving the purpose of making it smaller.

In addition, in a CMO3-TTL level conversion output converter for an internal logic block that operates at the CMOS level, the output transistor that charges or discharges the output load capacitance of the level converter is a bipolar transistor. By configuring M
Compared to an OS FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of the input buffer and its capacitance dependence It is possible to achieve the purpose of reducing the

[Example J Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 shows a block diagram of a logic semiconductor integrated circuit device IC according to an embodiment of the present invention, in which the input buffer 10 of FIG.
Internal logic block 1 in FIG. 1
An internal logic block 21.1 which operates at the CMOS level as in 21.1. Each circuit 20, 21, 22 includes an output output 7722 for 0MO8-TTL level conversion that performs an operation similar to that of the output buffer 7 in FIG.
It is supplied with a power supply voltage Vcc of volts and is properly grounded via terminal No. 31.

The input buffer 20 has a plurality of TTL-CMOS level converters 201, 202---2On, and each input has a terminal No. 1, ? Each output is connected to the internal logic block 21 and the circuit device IC by an aluminum wiring layer.

Internal logic block 21 is 0MO8-NAND game) 21
1,212,213,214 and CMO3-NOR game) 21 (#-1), 21 i et al: 0M as necessary
O8 Exclusage OR Day), 0MO8 Transmission Date.

Contains CMOS inverters, etc.

For example, as shown in FIG. 7, the 0MO8-NAND date 211 includes P-channel MO3FETs Ml, M2 and N-channel MO3PET M3. Pure CMO3 containing M, and
It is made up of circuits. Also, CMO, 5-NAN
D? -)211, as shown in FIG.
Since the output stage of such a quasi-CMO8 circuit is constituted by bipolar transistors Q, Q2, the output driving ability is improved and the dependence of the propagation delay time on the output load capacitance can be reduced.

*Ta0MO8-NORr-) 21111 example +rs9
As shown in the figure, P-channel MO8FETM, ,M2
and N-channel MO8FET M,,M.

It is composed of 8 pure CMO circuits including.

Further, as another example of the CMO3-NOR date 21A, as shown in FIG.
It can also be configured by a quasi-CMO8 circuit that further includes resistors R, , R2, and since the output stage of such a quasi-CMO8 circuit is composed of bipolar transistors Q, , Q2, the output drive capability is improved and the propagation The dependence of the delay time on the output load capacity can be reduced.

In the internal logic block 21, these CMO3-N
AND data), 0MO8-NOR date are connected in various configurations according to a master slice method or a semi-custom date array method.

For example, as shown in Figure 11, two CMO8NAND
R by combining the dates or by matching the two CMO3-NOR dates as shown in Figure 12.
The gated R-87 is configured with -87 rip and 70 lub and is controlled by clock signal C by combining four 0MO8-NOR dates as shown in FIG.
It consists of 7-70 tubes.

In this way, in the master slice type or gate array type logic semiconductor integrated circuit device IC that meets customer needs, the level converters 201 and 2 of the input buffer 70 can be changed by changing only the wiring pattern.
The output of 02----2On and the various dates or inputs of the inverter of the internal logic block 21 are connected in various forms, and the outputs of the various dates or inverter of the internal logic block 2-1 are connected in various ways. The terminals of the rose 7722 and the inputs of the level converters 221, 222--22m are connected in various ways.

The output buffer 22 has a plurality of 0MO8-TTL level converters 221, 222---"22To, and each output has two
No. 0 terminal, No. 21 terminal --- Connected to No. 29 terminal.

Level conversion of input buffer 720 201, 202--
The essential features of 2on are as follows.

(1) The input long-term hold voltage Vith of each level converter 201, 202--2On is set between the TTL low level input voltage of 0.8 volts and the TTL, 1 level input voltage of 2.0 volts. Do 1.

(2) The output transistor that performs charging or discharging of the output capacitance Os of each level converter 201=202--20n in response to the input signal supplied to its input terminal is constituted by a bipolar transistor. .

Furthermore, the level converter 201.20 of the input buffer 70
Preferred features of preferred embodiments of 2--=2On are as follows.

(3) A Schottky transistor Y is connected between the base and collector of the bipolar output transistor Q, which discharges the output capacitance O3 in (2) above.

(4) A drive for driving the base of the bipolar output transistor Q1 with its output in response to the input signal supplied to the input terminal of each level converter 201, 202---20n, and the base and collector of the transistor Q2. A second rear diode is connected between and becomes 1.

(5) Each level converter 201 = 202---2On
The six-output transistor for charging the output capacitance Cs of is also constituted by a bipolar transistor Q.

(6) The base signal or collector signal of the drive transistor Q2 is supplied for charging via the MOS buffer 7 having a high input impedance and an amplification effect. is transmitted to the base of the Ibora output transistor Q.

(7) A Schottky barrier diode D1 for level shifting is connected between the input terminal of each level converter 201, 202---20n and the base of the drive transistor Q2.
is connected.

(8) The connection between the input terminal of each level converter 201, 202-"-2On and the base of the drive transistor Q2 is PN.
A P emitter 7-lower transistor Q4 and a PN junction diode D2 for level shifting are connected.

Figures 14-31 show various circuit diagrams of the level converter 201 of the input buffer 20 according to embodiments of the invention, all of which are shown in (1) and (2) above.
) has the essential characteristics of Furthermore, these level converters have at least one of the preferable features (3) to (8) above.6 Level converters 20 in FIG. 14
1, the input terminal IN is connected to the cathode of a Schottky barrier diode D for level shifting, and its 7 node is connected to the base of the drive transistor Q2. The forward voltage Vp of this diode D1 is 0
．． The type of barrier metal and barrier area are determined so that the voltage is set between 35 volts and 0.41 volts. Similarly, the forward voltage Vp of the level converter Schottky barrier diode D in FIGS. 15 to 31 is O, '35.
Volts to 0.41 volts.

Furthermore, in FIG. 14, the drive transistor Q2 and the discharge output transistor Q1 have a Schottky barrier diode D connected between their bases and collectors, as shown by the key-shaped base electrode signals. There is. Clamped transistors with Schottky barrier diodes thus have a very short integration time, as is well known. In the examples below,
A transistor with a hook-shaped base electrode signal is indicative of such a clamped transistor.

The base of the discharging output transistor Q1 is connected to the ground potential point via a 5 kilohm resistor R1° for base tp discharging.

Further, in FIG. 14, an 18 kilohm resistor R1+ and a 2 kilohm C resistor R12 are connected in series between the power supply voltage Vcc and the anode of the Schottky barrier diode D. The common connection point of both resistors R11tR12 is a P channel MOS F E as a phase inverter.
T Ml)+. , and its drain is connected to the charging output transistor Q, in total.

Further, a diode D3 is connected to ensure that the transistor Q is turned off when the level converter 201 generates a low level output.

The output of the level converter 201 at the emitter of the charging output transistor Q is connected to the output capacitor Cs and also to the CMO8/NAND gate 2 of the internal logic block 21.
11 inputs.

Also, bipolar transistors Q, , Q2 . The area of each emitter Q is set to 100 .mu.m2 to 144 .mu.m2, and it is also possible to make the area smaller than this. Furthermore, the ratio W/L of MOS FET is 32/3 to 6.
The value is said to be 4/3.

The inventor has confirmed that the embodiment shown in FIG. 14 having the above configuration has the following propagation delay time and its output capacitance dependence.

tpnt, (when C5=OpF) '----1
．． 6nsectpLo (when C5=OpF) −
---5,7nsecK ML
-----0,4nsec/p FKLH---0
, 4nsec/pF The above propagation delay time tpnL, tpu+ and the output capacitance dependence KoL*KL, )l are the input buffer 7T in FIG.
Compared to the characteristics of 10, I can understand that it is superior.

Furthermore, the level converter 201 in FIG. 14 can obtain desired characteristics for the following reasons.

(1) The forward voltage Vp of the Schottky barrier diode D is set to 0.35 to 0.41 volts, and the base-emitter voltage of the transistor Q, Q2 is E1B.
Since VlIE2 is approximately 0.75 volts, the input threshold voltage Vith of level converter 201 is set as follows.

Vith=-VF+VB[lI+VB):2=1.09
to 1.15 volts (2) Since the output transistor QllQ3 that discharges or charges the output capacitance Cs of the level converter 201 is composed of a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its Output capacitance dependence can be reduced.

(3) A Schottky conductor is connected between each base and each collector of the transistor QllQ2 driven to the saturation region.
Since the barrier diode is connected, the storage time when both transistors Q, , Q, switch from on to off can be reduced.

(4) When the potential at the common connection point of resistors R111RI2 rises and the phase inversion MO8FET Mp+o+ charge output transistor turns off, the MOSFET Mp
,. Because the human power impedance of dating is very high,
M P + from the above common connection point. The current flowing into the gate of is very small. Therefore, MOS FET Mp
,. Compared to the case where the phase inverter is configured by a bipolar transistor instead, the operating speed for switching the charging output transistor Q from OFF to ON is improved.

The level converter 201 in FIG. 15 differs from the one in FIG. 14 only in that another PN junction diode D is added, and the addition of D4 further reduces the low level output voltage of the level converter. can do.

Regarding the level converter 201 shown in FIG. 15, the propagation delay time and its output capacitance dependence were confirmed by the inventor as follows.

tput (when C5=OpF) -----1,8
9nsectpLu (when C5=OpF) --
--6,37nsecKHL
---0,4nsec/pFKLM
----0,4nsec/pF Furthermore, the 15th
In the level converter 201 shown in the figure as well, desired characteristics can be obtained for the same reason as in the case of FIG.

The level converter 201 in FIG. 16 is a drive transistor Q2.
Only the collector connection method in FIG. 14 is different from that in FIG. 14, and the propagation delay time of the level converter in FIG. 16 and its output capacitance dependence were confirmed as follows.

tpuL (when C5=OpF) -----1,8
1nsectpu+ (when C5=OpF) --
--5,08nsecK ML
-----0,4nsec/p FKLII
-----0,4nsec/pFAlso,
In the level converter 201 of FIG. 16, desired characteristics can be obtained for the same reason as in the case of FIG. 14.

Each level converter 201 in FIG. 17 is a phase inversion MOS.
The only difference from the one in FIG. 15 is that another NPN transistor Q is connected between the drain of F E T M p 1o and the base of the charging output transistor Q. The propagation delay time of the level converter and its output capacitance dependence were confirmed as follows.

tpot, (when C5=OpF) -----2,
01nsec pL)+(However, when C5=OpF)
---7,30nsecK HL
-----0,4nsec/ p FK L14-
---0.4nsec/p
Clamped with rear diode in cytoki/
The base of the discharging output transistor Q1 is a 5 kilohm resistor RIO for discharging the base charge.
is connected to the ground potential point via. Further, a 20 kilohm resistor R1ff for collector current limitation is connected to the collector of the transistor Q2.

Power supply voltage Vcc and Schottky barrier diode DI
18N ohm resistors R11 and 2 are connected between the anode and the anode.
A kilohm resistor Rl 2 is connected in series.

The common connection point of both resistors R11t and R+2 is a P-channel MOs FET Mp+ as a charging output transistor.
It is connected to the + gate and becomes -. Further, the ratio W/L of this MJI is 64/3.

The propagation delay time of the level converter 201 shown in FIG. 18 and its output capacitance dependence were confirmed as follows.

tpnt, (when Cs: OpF) ------1
, 9nsec pL) + (However, when C5=OpF)
-----2,9nsecKIIL
-----0,4nsec/pFKLH----1
, 3 nsec/pF Furthermore, the level converter 201 in FIG. 18 can obtain desired characteristics for the following reason.

(1) As in the case of FIG. 14, the input threshold voltage Vith of the level converter 201 is set to 1.09 to 1.
．． It can be set to 15 volts.

(2) Since the output transistor Q that discharges the output capacitance Cs of the level converter 201 is composed of a bipolar transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacity dependence can be reduced.

(3) As in the case of Fig. 14, transistors Q1 and Q
The accumulation time of 2 can be reduced.

In the level converter 201 of FIG. 19, transistors Q, Q2 are clamped transistors with Schottky barrier diodes, and the base of the discharging output transistor Q1 is connected to a 5 kilohm resistor R+o for discharging the base charge. connected to ground potential point via. An 8 kilohm load resistor RI5 is connected to the collector of the transistor Q2, and a 20 kilohm resistor Rl4 is connected between the power supply voltage Vcc and the anode of the automatic barrier diode D. The collector signal of the drive transistor Q2 is connected to the date of an N-channel MO3FET Mn,2 as a charging output transistor. , *The ratio W/L of this Mn, 2 is 64/3
is set to .

The propagation delay time of the level converter 201 shown in FIG. 19 and its output capacitance dependence were confirmed as follows.

tpoL (when C5=OpF) -----1, 1
nsectpLo (when C5=OpF) ---
-8,6nsecK)IL-
---0,3nsec/pFKLM
---2.0 nsec/pF Furthermore, the level converter 201 in FIG. 19 can obtain desired characteristics for the same reason as in the case of FIG. 7 and FIG.

In the level converter 201 shown in FIG. 20, the transistors Q, Q2 are similarly clamped transistors, and the base of the discharge output transistor Q1 is connected to the ground potential through a 5 kilohm resistor R3 for discharging the base charge. Connected to the dots. 1 at the collector of transistor Q2
A load resistor R4 of 0 kilohms is connected, and the power supply voltage Vc
A 20 kilohm resistor R14 is connected between C and the anode of the Schottky barrier diode D.

The collector signal of the drive transistor Q2 is applied to the date of an N-channel MO8FETMMnlj as an amplification transistor, and the collector signal of the driving transistor Q2 is applied to the date of the N-channel MO8FETMMnlj as an amplification transistor. The ratio W/L is set to 32/3, and a load resistor R17 of 20 kilohms is connected to the drain of Mn+3. The drain signal of Mnl is a P-channel MO8FET as an amplification transistor.
Applied to the gate of Mpl-, the ratio W/L of Ml)+,
is set to 64/3, and the drain of Mp+'3 is set to 10
RIB is connected to the base of the kilo-ohm load resistance and charging bipolar output transistor Q as a charge discharging resistor.7 The propagation delay time of the level converter 201 in FIG. 20 and its output capacitance dependency are as follows. confirmed.

tpuL (when C5=OpF) ---"2.2
nsectpLH (when C5=OpF) ---
-7,5nsecKHL
---0,4nsec/pFK
LH'---0.4 nsec/pF Furthermore, the level converter 201 in FIG. 20 can obtain desired characteristics for the following reason.

(1) As in the case of FIG. 14, the input threshold voltage Vith of the level converter 201 is set to 1.09 to 1.
．． It can be removed by setting it to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time in charging and discharging the output capacitance Cs and its dependence on the output capacitance can be reduced.

(3) As in the case of FIG. 14, transistor Q3. Q
The accumulation time of 2 can be reduced.

(4) When the flefter potential of the drive transistor Q2 rises and the charging output transistor Q switches from off to on, the amplifying MO8FET Mn13 and MDI2 amplify the change in the collector potential of Q2, It not only transmits information to the base of MOS F E
The very large date input immunity of T Mn + y prevents a large base current from flowing directly from the collector of Q2 to the base of Q3, thereby increasing the switching speed of output transistor Q3.

In the level converter 201 of FIG. 21, Ql, Q2
is a clamped transistor ID+ is a Schottky barrier diode for level shifting, and a resistor R+ o
*R+ 4t RIs are each 5kOhm, 2
It is set to 0 kilo ohm and 8 kilo ohm. The collector signal of the drive transistor Q2 is C as a voltage amplifier.
O8FET between P channels that constitutes a MOS inverter
ml is added to both dates of Mp, and N-channel MO8FET Mn14, and both MO8FET Mp,. Mn
A drain signal of +< is applied to the gates of the P-channel O8FETs Mp, , as charging output transistors. The local W/Ls of Mp and 4°Mn+4+M+)+'l are set to 24/3°22/3 and 64/3, respectively.

The propagation delay time of the level converter 201 shown in FIG. 21 and its output capacitance dependence were confirmed as follows.

tpnL (when C5=OpF)---2,'0
2nsectpu+ (however, when C5=OpF) ---
-4,27nsecK ML
-----0,42nsecy'p FKLH---1
, 32 nsec/pF Furthermore, each level converter 201 in FIG. 21 can obtain desired characteristics for the following reasons.

(1), as in the case of FIG. 14, the level converter 201
The input threshold voltage Vith can be set between 1.09 and 1.15 volts.

(2) Since the output transistor Q that discharges the output capacitance Cs of the level converter 201 is composed of a bipolar transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacity dependence can be reduced.

(3) As in the case of Fig. 14, transistors Q1 and Q
The accumulation time of 2 can be reduced.

In the level converter 201 of FIG. 22, Q is a clamped transistor as an output transistor for discharging, and the input terminal IN is connected to the cathode of a Schittke barrier diode D1 for level shifting. A level shift P1 combination diode D5 is connected between the 7th node of Q and the base of Q, and the power supply voltage V
Between the anodes of cc and DIID, there is a resistor Rl with a resistance value equal to 10 kilohms! lt
R20 are connected in series, and a Schittky barrier diode D6 for base charge discharge is connected between the bases of the input terminals IN and Q.

The common connection point of *R2° to the resistor is connected to the gate of a P-channel O8FET M+)++ as a charging output transistor, and the ratio W/L of Mp, , is set to 64/3.

The propagation delay time of the level converter shown in FIG. 22 and its output capacitance dependence were confirmed as follows.

p) IL (when Cs = Op F) ---
-2,44nsecpu+(when C5=OpF) ---5,41nsecK)IL
---1,0nsec/pFKLH--
--5.3 nsec/pF Furthermore, the level converter 201 in FIG. 22 can obtain desired characteristics for the following reason.

(1) The forward voltage Vp of the Schottky barrier diode D is set to 0.35 to 0.41 volts, and the PN
The forward voltage Vp of the junction diode D, is 0.75 volts, and the base-emitter open circuit voltage VII of the transistor Q,
Since E is 0.75 volts, the input threshold voltage Vith of the level converter 201 for turning on the transistor Q is set as follows.

Vith=VFl+VP5+Vl]El=1.09
to 1.15 volts (2) Since the output transistor Q, which discharges the output capacitance Cs, is composed of a bipolar transistor with small output resistance, the switching time or propagation delay time and its dependence on the output capacitance are reduced. be able to.

(3) Since the transistor Q is a clamped transistor, it is possible to reduce its storage time.

In the level converter 201 of FIG. 23, Q3. Q2
The clamped transistor fDl is a Schottky barrier diode for level shifting, and the resistor R1゜t
R141RI5 is set to 5 kilo ohms, 20 kilo ohms, and 8 kilo ohms, respectively. The collector signal of the drive transistor Q2 is a P-channel MO8F'ET Mp that constitutes a CMOS inverter as a voltage amplifier.
z and the gates of an N-channel Mn8 FET Mnz, and the drain outputs of both MO8FETs are applied to the gate of a P-channel MO8F'ET Mplg for switching. Mp14y Mn14y Mp+s ratio W
Each region is set to 24/3.32/3.64/3.

The drain output of the MOS FET Mp,5 is applied to the base of a bipolar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter shown in FIG. 23 and its output capacitance dependence were confirmed as follows.

tpnL (when es=OpF) -----5,0
7nsectpLn (when C5=OpF) --
--5,09nsecK Ht,
---0,4nsec/p FK+-u
---0.4 nsec/pF Furthermore, the level converter 201 in FIG. 23 can obtain desired characteristics for the following reasons.

(1) As in the case of FIG. 14, the input threshold voltage Vith of the level converter 201 is 1.09 to 1.
．． It can be set to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time in charging and discharging the output capacitance Cs and its dependence on the output capacitance are reduced.

(3) As in the case of Fig. 14, transistors Q1 and Q
This can be achieved by reducing the accumulation time of .

(4) When the flip-flop potential of the drive transistor Q rises and the charging output transistor Q switches from off to on, the CMOS inverter Mρ. , Mn+
4 not only amplifies the collector potential change of Q2 and transmits it to the base of Q, but also Mn8 FET Mp+4t
The switching speed of the output transistor Q is improved because the input and input impedance of , Mnz is extremely large, and the collector force of Q2 prohibits a large base current from directly flowing into the base of Q. I can do it.

The level shift 201 in FIG. 24 is a 10 kilohm resistor R2 for discharging the base charge of the charging output transistor Q.
The only difference from the level converter 201 in FIG. 23 is that 8 is connected between the base and emitter of Q, and the propagation delay time and output capacitance dependence of the level converter 201 in FIG. 24 are as follows. It was confirmed as follows.

tpoL (when C5=OpF) -----6, 2
nsectpLn (when C5=OpF) ---
−4,9nsecKHL --
--0,4nsec/pFK LM
---0.4 nsec/p F Furthermore, the level converter 201 in FIG. 24 can obtain the desired characteristics for the same reason as in the case of FIG. 23.

In the 2.5I level converter 201, the resistance R3° of the base charge discharging circuit of the discharging output transistor Q is 1.5°.
Kilohm resistance R,,,3 kiloohm resistance R20t
It is replaced by an active pull-down circuit constituted by a clamped transistor Q6, and a Schottky barrier diode for discharging the base charge of the charging output transistor Q is connected between the base of Q and the collector of Q2. The only difference from that shown in FIG. 24 is that the propagation delay time and its output capacitance dependence in FIG. 25 were confirmed as follows.

pHL (when C5=OpF) -----6,6
nsecLpu+ (when C5=OpF) ---
-5,3nsecKHL -1--0,4nsec/ pFKLH---0,4ns
ec/pF Furthermore, the level converter 201 in FIG. 25 ends up obtaining desired characteristics for the same reason as in the case of FIG. 23.

The level converter 201 in FIG. 26 differs from the one in FIG. 24 only in that the discharge resistor R5° is replaced by the same active pull-down circuit as the active pull-down circuit RB, s+ R201Qe in FIG. 25, Regarding FIG. 26 as well, the propagation delay time and its output capacitance dependence were confirmed as follows.

tpHt (when C5=OpF) -----8,6
2nsectpt, n (when C5==OpF)
-----4,7nsecKot,
-----0,4nsec/pFKLH---0,
4 nsec/pF Furthermore, the level converter 201 in FIG. 26 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 of FIG. 27, bipolar transistors Q, , Q2 . Q is a discharge output transistor and a drive transistor, respectively.

These are output transistors for charging, and D, , D' are Schottky barrier diodes for level shifting, respectively.
It is a PN junction diode, Rl 4 t Rl 6
fR, , R22 are resistances of 20 kOhm, 8 kohm, 10 kohm, and 10 kohm, respectively,
MplsrMn+s is O8FE between P channels, respectively.
T, N channel MO8FET, both Mp+st
The ratio W/L of Mn+s is both set to a value equal to 32/3.

In particular, Mfl+s+ Mn'lGI Qll Q3 is characterized in that it is a quasi-CMOS inverter type amplifier with low output resistance.

The propagation delay time of the level converter 201 in FIG. 27 and its output capacitance dependence are confirmed as follows.

tpoL (when C5=OpF)---5,48
nsectpLu (when C5=OpF) -----
5,23nsecKHL --
--0,37nsec/pFKLH---0,38n
sec/pF Furthermore, the level converter 201 in FIG. 27 can obtain desired characteristics for the following reasons.

(1) Forward voltage Vp of Schottky barrier diode D1 is 0.35 to 0.41 volts, transistor Q
The base-emitter voltage Vep2 of 2 is 0°75pol)
, the forward voltage of the F'N junction diode D8 is 0.
Since it is set to 75 volts, transistor Q2
The input threshold voltage Vitb of the level 1 converter 201 regarding the on/off operation of is set as follows.

Vith= Vp, +V'ea2+VF@=1.09
to 1.15 volts (2) Since the output transistors Q, , Q, which discharge or charge the output capacitance Cs are composed of bipolar transistors with small output resistance, the switching operation speed or propagation delay time and its output Capacity dependence can be reduced.

(3) Since QllQ2 is a clamped transistor, the 1141 time can be reduced.

(4) The collector potential change of drive transistor Q2 is quasi-C
MOS inverter Mp16t M n + 6+ Q
* + Q + is amplified and transmitted to the output.
Therefore, the output waveform change speed can be improved.

In the level converter 201 of FIG. 28, the collector load of the transistor Q2 is a resistor R1. Then (, PN junction diode Ds=D,
) The only difference from the level converter shown in FIG. 27 is the structure, and the propagation delay time and output capacitance dependence of the level converter shown in FIG. 28 were confirmed as follows.

p) It, (when C5=OpF)---6,
66nsectpLn (when C5=OpF) --
--4,16nsecKHL
-----0,42nsec/pFKL)I
----0.37 nsec/pF Furthermore, the level converter 201 in FIG. 28 can obtain desired characteristics for the same reason as in the case of FIG. 27.

The level converter 201 in FIG. 29 is connected to a PN junction diode D for reliably turning off the transistor Q, and to a Schottky barrier diode D7 for discharging the base charge of the transistor Q3. The level converter 201 shown in FIG. 29 differs only in this point from that shown in FIG. 23, and its propagation delay time and its output capacitance dependence were confirmed as follows.

tp+n, (when C5=OpF)---1,7
2nsectpLn (1--- when C5=OpF
5.44nsecKIIL --
--0,32nsec/pFKLH---0,29n
sec/pF Furthermore, the level converter 201 in FIG. 29 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter of FIG. 30 has a resistor R1 in FIG.
is a resistance R24 of 25 kilohms and a resistor R24 of 5 kilohms.
25 and the resistor RI 5 has a ratio W/L of 2
P channel MOS FET set to 4/3
The only difference from the one in FIG. 29 is that it is replaced by Mplt. Since Mfht operates as an active load element for Q2, the voltage gain of amplifier Q21Mp17 is extremely large.For FIG. 30, the propagation delay time and its output capacitance dependence were confirmed as follows.

tp+u, (when C5=OpF) ------2,
2nsectpLH (when C5=OpF) --
--5,2nsecKML ---
-0,4nsec/pFKLH---0,3nsec
/pF Furthermore, the level converter 201 in FIG. 30 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 of FIG. 31, transistors Q, Q2 are clamped transistors.

Q3 is a charge output transistor 104 is a PNP emitter/7-lower transistor, DI is a Schottky barrier diode for level shifting, D2 is a PN junction diode for level shifting, and 1Dff is a PN transistor to ensure that the transistor Q is turned off. The junction diode fDs is a switchboard for clamping the negative noise on the input terminal.
It is a barrier diode. Resistance R3゜r RISI
Ro is set to 5 kilo ohms, 8 kilo ohms, and 20 kilo ohms, respectively. The collector signal of the drive transistor Q2 is applied to both the dates of the P-channel MO8FET Mpl- and the N-channel MOS FET Mn1- that constitute the CMOS inverter as a voltage amplifier, and the drain output of both MO8FETs is applied to the gate of the P-channel MO8FET Mp+s for the switch. is applied to

The local W/L of Mpzt Mn+ns Mp+s is set to 24/3.32/3.64/3, respectively. M
The drain output of the OS FET Mp, , is applied to the base of a bipolar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter 201 shown in FIG. 31 and its output capacitance dependence were confirmed as follows.

tpuL (when C5=OpF)---1,94
-3,84nsec pLn (when C5=OpF) -, -4,64-5,44nsecK)IL
---0+38nsec/pFK
L11 ----0.30ns
ec/pF Furthermore, the level converter 201 in FIG.
) Schottky barrier diode D, forward voltage Vp10.35 to 0.41 volts, PNN junction diode 2 forward voltage VF2 about 0.75 volts, transistors Q, , Q2 . Base-emitter voltage VR of Q
RI? VBE! 21 Vns4ha approx. 0.75. if
Due to the presence of silt, the input threshold voltage Vith at which transistors Q, Q2 are turned on is as follows.

Vith= VeE4+Vp2+VBE2+VnE+
= 1.5 volts (2) Since the output transistors Q, Q3, which discharge or charge the output capacitance Cs, are composed of bipolar transistors with small output resistance, the switching operation speed or propagation delay time and its output capacitance Dependency can be reduced.

(3) Since Ql and Q2 are clamped transistors, their storage time can be reduced.

(4) When the collector potential of the drive transistor Q2 rises and the charging bipolar output transistor Q3 switches from off to on, the CMOS ear/(-event Mp
14. Mnz amplifies the change in the converter potential of Q2 and becomes Q,
In addition to transmitting data to the base of the MOS FET
The date input impedance of Mp, , Mnz is extremely large, which prohibits a large base current from directly flowing from the collector of Q2 to the base of Q.
Since the base current is supplied to the base of Q through the small on-resistance of 15, the switching speed of the output transistor Q can be improved. Figure 3 shows the first
The dependence of the propagation delay time of the level converters in Figures 4, 19, 22, and 33 on the output capacitance is shown by the dashed-dotted line. It can be seen that the output capacitance dependence on the other hand has been improved.

Next, a plurality of 0MO8-Ts of the output buffer 722 in FIG.
The TL level converters 221, 222---22m will be explained. These level converters 221, 222--
--The essential features of 22m are as follows.

(1) Input threshold voltage of each level converter 221.222--22m VithlICMOS low level output voltage 0.6 volt high level output voltage 4.
It is set between 4 volts.

(2) The output transistor that discharges the output load capacitance Cx of each level converter 221, 222-11-22m in response to the input signal supplied to its input terminal is constituted by a bipolar transistor.

Furthermore, the level converters 221 and 2 of the output buffer 22
Preferred features of the preferred embodiment of 22-=-22m are as follows.

(3) A high input immunity circuit is connected between the base of the drive transistor Q+1 that drives the base of the discharge output transistor QIO and the output of the internal logic block 21.

(4) The high input impedance circuit in (3) above is internally
It has a function of logically processing a plurality of output signals of the ring block 21.

(5) The discharging output transistor Qto and the drive transistor Q are constituted by a clamped transistor with a Schottky barrier diode.

(6) Output transistor Q charging output load capacitance C×
1□ is constituted by a bipolar transistor.

(7) Output transistor QI for discharging in response to a control signal
By simultaneously turning off O and the charging output transistor Q+2, the output terminal OUT is brought into a 70-ting state.
It has the function of controlling.

(8) The level converters 221, 222---22m have an open collector output format.

32 to 34 and 36 show various circuit examples of the level converter 221 of the output buffer 20 according to embodiments of the present invention, and all of these level converters are shown in (1) above.
) and (2). Furthermore, these level converters have at least one of the preferred features (3) to (8) above.

In the level converter 221 of FIG. 32, Q.

is the output transistor IQII for discharging the output load capacitance C×. Drive transistor y to drive
Q+□ is an output transistor for charging the output load capacitance Cx, Q, 3 is a current amplification transistor tR3 for transmitting the collector signal change of Q++ to the base of Q12.
01Rfflt Q14 is an active pull-down circuit for discharging the base charge of Q10.

QCs is a multi-emitter transistor, R32 is a Q
, the collector resistance R1, is a resistance ID+ for discharging the base charge of Q12. is a sitatchi barrier diode for discharging the base charge of Q l 2, R
1 is a resistance for limiting the collector current of Q1□tQl+, and R3 is a base resistance of QCs.

Furthermore, P channel MO3 of internal logic block "21"
FET M,, M2 and N-channel MO8FET M3
．． M, and t: The output of the 1ic MO9-NAND gate 211 is a multi-emitter transistor QIS.
The output of 0MO6-NAND date 212 is applied to the second emitter of Q10, 0M
The output of O8-NAND data) 213 is applied to the third emitter of Q+s. Therefore, the level converter 221 not only has a level conversion function but also a logic processing function as a three-man NAND date.

Furthermore, the level converter 221 in FIG. 32 can obtain desired characteristics for the following reason.

(1)) The base-emitter voltage Vst+s of transistor QC5 is approximately 0.75 volts, Q4. The base-collector voltage MBC of the transistors is approximately 0.55 volts, and the base-emitter voltage VeF of the transistors Q+o and Q++ is approximately 0.55 volts.
ot VBR ports are each about 0.75 volts, so the input threshold voltage V of level i converter 221
ith is set as follows.

Vitl+=-VIIIg+5+Vac1g+Veg+
++Vep+.

=-0,75+0.55+0.75+0.75=1.3
Volt (2) Output transistor Q10tQ that discharges or charges the output load capacitance Cx of the level converter 221
Since +□ is constituted by a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Transistor QI OI Q I I t Q
I :l I Q + 41 Ql, is clamped
- Since it is a transistor, its storage time can be reduced.

(4) Since the multi-emitter transistor QIS has a logic processing function, the degree of freedom in designing a master slice type or gate array type logic semiconductor integrated circuit device IC is improved.

However, in the level converter 221 of FIG. 32, when the output of the CMO3-NAND date 211 is low level, the power supply voltage Vcc is converted to 0MO8- through the base-emitter junction of the resistors R, Ql. Since a large current of 0°4 milliamps always flows into the output of the NAND gate 211, the 0MO8-NAND gate 21
1 N-channel MO8FET M,, M4 ratio W/L
The on-resistance ROM must be set to a small value by taking a large value of 100/3. This not only causes a decrease in the integration density of the integrated circuit device IC, but also
T M3. Since the gate capacitance of M also increases, 0MO8
- The inventor's studies have revealed a problem in which the switching speed of the NAND gate 211 decreases.

FIG. 33 shows a circuit diagram of a level converter 221 developed to solve the above problem, in which the multi-emitter transistor Q+s of FIG. 32 is replaced by a high input impedance circuit as described below.

That is, such a high input impedance circuit in FIG.
N-emitter 7-lower transistor Q16. Schottky barrier diode D, D12, resistor Rz
It is composed of s t R* y + R3a.
Ru.

Furthermore, the level converter 221 is PNP) Lannostar Q2
．． ．． NPN) transistor Q2゜, PN junction diode D
It is constituted by an I4y resistor RHI and includes a control circuit for controlling the output terminal OUT to a 70-ting state.

This control [ffl II PNP) transistor Q20
The base of is driven by the enable signal EN of the 0MO8-NAND data) 211 formed by the P-channel inter-channel O3FET Ms and the N-channel MO9FETM6 in the internal logic block 21. In addition, such commercials
An inverted enable signal EN is applied to the input of the O3-NAND gate 211.

Furthermore, this control circuit is attached to the level converter 221.
Due to the high input immunity circuit described above, a PNP input input resistor Q2. and a Schottky barrier diode DI3 are added.

Therefore, when the enable signal EN becomes low level, the transistors Q, ..., Qz+Q1 of the level converter 221
2t Ql3 turns off at the same time, so its output terminal O
UT is in a 70-ting state.

On the other hand, when the enable signal EN becomes high level, the level converter 221 also has a logic processing function as a two-man NAND gate, so the degree of freedom in designing the integrated circuit device IC is improved.

Furthermore, the Sittke barrier diode D I l
tDptr D,, forward voltage Vp+++ Vp+2
v VF13 is 0.35 to 0.41 volts, PNP input input resistor Ql? ; Q l 8 r Q l
9 base-emitter voltage Vsa+yy Vaa+
at VtaEl, approximately 0.75 pol), NPN) transistor Q,. + Q+++ QCs bass Emi yj
' Voltage veElol vBR+ If VFIE1s
CMO3-NAN is about 0.75 volts, so applied to the base of transistor Ql7 (for example PNP)
Regarding the output voltage of the D gate) 211, the transistor QI
Input threshold voltage at which OIQ11 turns on■
ith is as follows.

Vith=-V8s17+ VIIE+6 +VBE+
1 + VBEIG = 1.5 volts Furthermore, since the output transistor QIOtQ+2 that discharges or charges the output load capacitance Cx is composed of a bipolar transistor with small output resistance, the switching speed or propagation delay time and its output are Capacity dependence can be reduced. Also, transistor Q. ,Q.

Q 13 * Q l 4 s Q ls is clamped
Since it is a transistor, its delay time can be reduced.

However, when the output of the level converter 221+ in FIG.
The inventor's studies have revealed that the above-mentioned problem is not completely solved because a non-negligible current flows from the base of the date 211 into the output of the date 211.

Figure 34 shows the level converter 211 finally solved to almost completely solve the problem, and the multi-emitter transistor QI5 of Figure 32 is replaced by a MOS FET as explained below. It has been replaced by a commercial impedance circuit constructed as follows.

That is, the high input inheatance circuit shown in FIG. 34 is an N-channel MO8FET M++t Ma2
y M+it Consists of a PN junction diode DI4. The drain-source paths of Ml lHM l 2 t M + 3 are connected in parallel, and each date is 0MO8-NAND date 211. of internal logic block 21.
212 and 213, respectively, and a PN junction diode D I 4 is connected in series to these drain-source paths.

Also, resistor R3゜l Rjl R321R331R34
1R15 is 2k ohm, 4k ohm, 1
0k ohm, 4k ohm, 50-75 ohm.

It is set to 16 kilohms. Transistor Q+
Each emitter area of 01 Q I I I Q + 3 I Q + 4 is 672 μm2.132 μ
It is set to rn2.363μ12°187μm2,242μμm2.

Furthermore, in order to further improve the logic processing function of the level converter 221, the drive transistor Q,
a second drive transistor Q2 having the same emitter area as
0 is connected in parallel with Ql+, and N-channel MO8FETs M, , M
,9. M, 6. PN junction guide, ord D13. Resistance R+
9 constitutes a second high input impedance circuit, and this level converter 221 has a logic processing function as a six-person complex date circuit.

Furthermore, when the level converter 221 is supplied with a low-level enable signal EN from the internal logic block 21, its output terminal OUT.

A control circuit for controlling the floating state is also added. This control circuit is an N-channel MO
8FET M,,,) transistor Q2. .

Q221Q23? Resistance R4゜, R,, R4□tR43
t switch barrier diode D' 161 D
+ 71 D + e + Dl.

Furthermore, in the level converter 221 of FIG.
The input threshold voltage at each date of the two MOS FETs M, -=-M, 6 is set to an intermediate value of 2.5 between the CMOS low level output voltage of 0.6 volts and the CMOS high level output voltage of 4.4 volts. volt, the ratio W/L of pJi, . . . pA, 6 is set as follows. Incidentally, at this time, Ml H---
The threshold voltage of M16) FEVtuJ is approximately 0,75
The forward voltage V p , 4 of the PN junction diode, rD, is set to 0.75 volts, and the M
l---M, channel conductance β of 6. is set to 60×10-6 [1/ohm].

Considering the case where only MOS FET M, is on, its date voltage VX, gate-source voltage Vasg
Drain current In, l-rain voltage Vy, etc. are calculated. It is assumed that M is biased in the saturated region at this time.

vx=”GS+Vp14 --
- From (1)=”'-° (VGS-VTR) 2----
(2) VY□vcc-R35・ko
-, - (3) From formula (1) and formula (2>, 1βQW ID----, (Vx-vF14-VTH) 2
--- (4) L By the way, as ■× increases, ')vY decreases,
Vx, which corresponds to turning off transistor QlotQ++, can be considered as the input threshold voltage.

The drain voltage VY at which the transistor QIOtQI+ is turned off is determined as follows.

vY"'BELL+vBEIO-(5)(3) and (5
) formula, Vcc is 5 volts, VBEII and VBEIO are 0.
75 volts, R85 is 16 kilohms, R0 is 60 x 1
0-6 [1/ohm], v; is 2.5 volts 1VF14
Inserting the conditions of 0.75 volts and 0.75 volts into the above equation (7), = -x 103 60 -7. With i9ζλ and the comb, the ratio W/L of M,,---M,, is 22/3
By setting the level converter 221 to 2.5 volts, the input threshold voltage of the level converter 221 can be set to 2.5 volts.

The present inventor has confirmed that the embodiment shown in FIG. 34 having the above configuration has the following propagation delay time and its output capacitance dependence.

tpnL (when C5=OpF)---8,8n
sectpLu (when C5=OpF) ---7
,8nsecKHL ----0
,11nsec/pFKLH---0,01nsec
/pF In FIG. 5, the output load capacitance dependence of the propagation delay time of the level converter of the embodiment of FIG.
Output capacitance dependence KHL, KLH of pt and u, respectively
It can be seen that this has been improved.

Further, the level converter 221 shown in FIG. 34 is easy to obtain desired characteristics for the following reason.

(1) As mentioned above, regarding the base-emitter voltage ■BE, o, vI111:ll of the transistor Q1゜IQll, the power supply voltage Vcc + resistor R, 5, MO8FET M
, 1---channel conductance β of M2O. and threshold voltage Vtu, forward voltage of diode DI4 8. Corresponding to MOS FET M,,---
By setting the ratio W/L4 of M, , the input threshold iK pressure of the level converter 221 can be set to 2.5 volts between 0.6 volts and 4.4 volts.

(2) Since the output transistor QIOIQ11 that discharges and charges the output load capacitance Cx is composed of a bipolar transistor with small output resistance, it is possible to reduce the switching operation speed or propagation delay time and its dependence on the output capacitance. It ends with

(3) Since a high input impedance circuit constituted by the MOS FET Ml is connected between the base of the drive transistor Ql+ and the output of the internal logic block 21, the internal logic block 21 is The end result is to reduce the current flowing into the output of the 0MO8-NAND date 211 to a level where it can be ignored. -4211+7) It is difficult to prevent the ratio W/L of the Nf-+n* MO8FET from increasing.

(4) MOS FET M with high input impedance circuit
,,,M,2. Since the M+31i3 manual OR logic is executed, the logic processing function of the level converter 221 is improved.

(5) Two drive transistors QIIQ2゜ are also ANDed.
To perform the logic, the logic processing capabilities of the level converter/221 are further enhanced.

(6) Transistor QI OI Q I l I Q
l 3 j Q l 4 t Q2o is clamped
Since it is a transistor, its storage time can be reduced.

(7) The output transistor Q of the level converter 221 by setting the enable signal EN to a low level. ,Q,
2 are turned off at the same time, and the output terminal OUT becomes a floating state, and during parallel operation in which this output terminal OUT and the output terminal of another logic circuit (not shown) are connected, this output terminal OUT.

The signal level of the internal logic block 21 can be made independent of the output of the internal logic block 21.

FIG. 36 shows a level converter 22 according to another embodiment of the invention.
1 is shown, and its output terminal 0UT1 is open.
It is commonly connected to the output terminal of another collector output type semiconductor integrated circuit device IC' for TTL level logic, and this common connection point is connected to a 5 volt power supply voltage Vcc via a 2 kilohm load resistor RIOQ.

Open collector output type TTL level circuit device II
c' is, but is not limited to, a Schottky barrier diode D++D2tDit multi-emitter transistor Q40? Clamped transistors Q4+ to Q, 4. Resistance R4° to R1, PN junction diode D
4. However, the output transistor Q
The collector of No. 43 is connected to the No. 43 terminal as an output terminal as an open collector output, while the collector of circuit device IC
' Any circuit element inside the power supply voltage Vcc
and the collector of equal output transistor Q43.

In the level converter 221 of FIG. 36, the circuit device I
The level converter 221 is formed exactly the same as the level converter 221 shown in FIG. 34, except that no circuit element is connected between the power supply voltage Vcc and the collector of the output transistor QIO.

In this way, the output terminal of the circuit device IC and the output terminal of the circuit device IC'' are connected in the form of a so-called wired OR circuit.Furthermore, by setting the enable signal EN to a low level, the output terminal of the level converter 221 is Transistor QIO can be forcibly turned off to make the level of output terminal 0UTl independent of the output of internal logic block 21.

FIG. 37 shows the layout of each circuit block on the surface of the semiconductor chip of the logic semiconductor integrated circuit device IC according to the embodiment of the present invention.

A 0M03 circuit (pure CMO3 circuit or quasi-CMO8
An internal logic block 21 configured by a circuit) is wired, and an input level converter (inside a hatched triangle) shown in FIG. ) is the 34th
A plurality of output level converters shown in the figure (indicated by white triangles) are arranged alternately, and the semiconductor chip 30 is similarly arranged.
0's right side (area surrounded by broken line 12), lower side (area surrounded by broken line l), left side (broken line ρ,
A plurality of input level converters shown in FIG. 31 and a plurality of output level converters shown in FIG. 34 are alternately arranged in each of the areas (enclosed by).

Above the upper side Q1, there are a number of input bonding pads (indicated by thick solid rectangles) corresponding to the number of input level converters, and a number of output bonding pads (indicated by thin rectangles) corresponding to the number of output level converters. ) are arranged, the input part of each input level converter faces each input bonding pad, the output part of each input level converter faces the internal logic block 21, and each output level The input of the converter faces the internal logic block 21, and the output of each output level converter faces the respective output bonding pad.

A plurality of input padding pads and a plurality of output padding pads on the right side of the right side part l, a plurality of input padding pads and a plurality of output padding pads under the lower side part 13, and a plurality of input padding pads and a plurality of output padding pads on the left side of the left side part a4. The plurality of input padding pads and the plurality of output padding pads are located on the upper side 1.
They are arranged in the same way as in case 1.

Right side part 12. The orientation of the input/output part of the input level converter in the left side part 14 of the lower side part 13 and the orientation of the input/output part of the output level converter are respectively the upper part l.

The same is true for .

A power supply bonding pad 30 for supplying the power supply voltage Vcc is disposed on at least one of the four edges of the semiconductor chip 300, and a grounding pad 31 for connecting to the ground potential point is located at one of the four edges. It is arranged in at least one of the edge parts.

A semiconductor chip 30 having the layout shown in FIG.
The back surface of 0 is physically and electrically closely connected to the surface of tab lead L of metal lead frame Lp in FIG. 38.

In the lead frame Lp shown in FIG. 38, this lead frame Lp has a lead portion corresponding to the upper right portion of the semiconductor chip 300, a dam portion Lo marked with diagonal lines, and a frame portion Lot. However, in reality, the same applies to the portions corresponding to the lower right, lower left, and upper left portions of the semiconductor chip, so the lead frame Lp is framed by the diagonally shaded dam portions. , lead part,
~L64° Tab lead ↑ is a metal workpiece thin plate with a structure in which they are connected to each other.

After the back surface of the semiconductor chip 300 is connected to the front surface of the tab lead Lt, the following bonding wire (for example, gold wire or aluminum wire) is wired.

By using a commercially available wire bonding device, the power supply bonding pad 30 and the lead portion Ls< are electrically connected by the wire 15, and the input pad and the lead portion Ls< are sequentially connected by the wire 16. The wire I17 connects the output pad to the lead portion L7, the wire I connects the input pad to the lead portion L7, the wire L connects the output pad to the lead portion L, and the wire 11° connects the input pad to the lead portion L7. The pad and lead portion, or the wire ff111, electrically connects the grounding pad and the tab lead T, respectively.

Lead frame Lr after the above wire wiring is completed
The semiconductor chip 300 is delivered to a mold for resin sealing, and is placed in the dam portion of the lead frame Lp.

Liquid resin is injected inside. This dam portion Lo prevents the resin from flowing out to the outside. After the resin solidifies, the lead frame L becomes an integral structure.
F, the semiconductor chip 300, and the resin are taken out from the mold, and the dam part Lo is removed by a fress machine or the like, thereby electrically separating the lead parts L, -L, and the like. Ru.

Each lead L I-L s − protruding from the solidified resin
1. The logic semiconductor integrated circuit device IC is completed, which is folded downward as necessary and sealed by the ileum 301 as shown in the completed view of FIG. As shown in the figure, this circuit device IC does not have a special heat dissipation fin for actively dissipating heat generated from the semiconductor chip 300 to the outside of the sealing structure.

If such heat dissipation fins are installed, the circuit device 11
The cost of c increases undesirably.

Further, as a method for sealing the semiconductor chip, in addition to the above-mentioned resin sealing method, a ceramic sealing method and a method using a metal case can be considered, but from the viewpoint of the cost of the circuit device 11c, the above-mentioned resin sealing method is considered. The sealing method is the most advantageous.

In the logic semiconductor integrated circuit device IC according to the embodiment using the drawings of FIGS. 37 to 39, the input buffer 2
Input level converter 201 e 202-X- as 0
--2On,") Total number is 18-50. CMOS game as internal logic block 21) Goo 1゜212----2
The total number of 11 is 200-1530. Output level converter 221゜222 as output rose 7y30---Even though the total number of 22 wheels is 18 to 50 and the semiconductor chip 300 is a large-scale semiconductor integrated circuit device, the circuit device is not suitable for the following reasons. The power consumption per gate of each CMOS data (211, 212) 211, 212 (211) as the internal logic block 21 is extremely small at 0.039 milliwatts. The power consumption of the entire internal logic block 21 with 200 to 1530 gates is 7.8 to 59°67 milliwatts/2F.
and extremely small. Input buffer 77 according to the embodiment of FIG.
Each input level converter 201, 202 as 20...
-2On contains many bipolar transistors, so the power consumption per converter is as high as 2.6 milliwatts, and the total power consumption of the input buffer 20 with 18 to 50 converters is 46.8 to It is large at 130 milliwatts.

Since each output level converter 221, 222--22m as an output buffer 20 according to the embodiment of FIG. 34 also includes many bipolar transistors, the power consumption per each converter is 3. .8 milliwatts, large output buffer 7 with 18 to 5 converters 22, consumption type cover 6
8.4 to 190 S +7 watts, which is large.

Input buffer 720 with the above data, 18 converters,
21° internal logic block with 200 gates and 18 converters
In the circuit device (c) of the output buffer 22, the 37th
In the central part 1o of the semiconductor chip surface in the figure, 6.4% of the total heat is generated, whereas in the comparative part j2+t'
A total of 93.6 percent of the heat is generated.

Also, the input buffer 20 . of the converter 50 . Number of dates: 153
0 internal logic block 21. Output rose 7 with 50 converters
In the circuit device IC of No. 722, 15.8% of the total heat is generated in the central portion 10 of the semiconductor chip surface shown in FIG.
．． Two percent heat is generated.

By the way, as shown in FIG. 37, the internal logic block 21 that generates a small amount of heat is located in the central portion β of the chip. The input bag 7720 and the output cover 27a 22, which are placed on the sides and generate a large amount of heat, are located on each side of the chip. 112.1. , L, so each side 11., as shown in FIG. A large amount of heat from L and L-L is transferred to the outside of the circuit device IC (especially when the IC is mounted on a printed circuit board, the ground line of the printed circuit board) via the tab lead LT and the lead part as a grounding lead. Instead of a gap that is taken out, the external part of the circuit device IC (especially when the IC is mounted on a printed circuit board, the signal line of the printed circuit board and power line)
can be taken out.

In contrast to the above embodiments, the central part l of the chip. If the input bag 7a 20 and the output bag 7a 22, which generate a large amount of heat, are arranged in the central part 12o, and the internal logic block 21 is arranged around the central part 12o, a large amount of heat in the central part 10 will be transferred to the circuit device IC. It has been confirmed through calculations by the inventor that it is not easily taken out.

For the above reasons, the circuit device IC of the above embodiment was able to have a structure without heat dissipation fins. In addition, since the circuit device IC has a resin-sealed structure, it has become possible to significantly reduce the cost of the IC.

FIG. 40 shows a logic semiconductor integrated circuit device IC according to an embodiment using the drawings of FIGS. 37 to 39 and other TTL level logic semiconductor integrated circuit devices 401, 402 ---
-4On, 501 to 505°600 are mounted on a printed circuit board to form a block diagram of an electronic system.

In the figure, a device 401 having TTL level output
, 402-=4On, each output is the input IN of the circuit device IC.
, , IN, ---INn, respectively, and the output of the circuit device IC is the TTL input level position 501 ---
505 input.

Furthermore, by commonly connecting the output OUT of the circuit device IC and the output of the device 600, the device IC, 600
executes parallel operation.

A large amount of heat generated in the input buffer 20 and output buffer 22 of the circuit device IC can be dissipated to the ground line, power supply line, input signal line, and output signal line of the printed circuit board.

Also, the enable signal E supplied to the output rose 7722
When N is set to low level, its output.

UTl-0UT2---OUTII+ is in the 70-ting state, and the input levels of devices 501, 502, 503 are set by the output level of device 600.

In addition, the input buffer 7 2o and the device 401.402---
40n provides a high speed, an interface between the internal logic block 21 and the input buffer 7y20 provides a high speed, and an open interface with the internal logic block 21 of the output buffer 22 provides a high speed. Thus, even with an open interface between the devices 5o1--505 and the output buffer 20, high speeds can be obtained.

[Effects] According to the above embodiments, favorable effects can be obtained for the following reasons.

(1) The output transistor that charges or discharges the output capacitance Cs of the input level converter 201 is a bipolar transistor.
By configuring with transistors, MOS
Compared to a FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging current or 1. Due to the effect that a discharge current can be obtained, the propagation delay time of the input level converter and its output capacitance dependence can be reduced.

(2) In the input level converter 201, a Schottky transistor that performs majority carrier operation is used to connect the base and collector of the bipolar transistor driven into the saturation region.
Since the barrier diode is connected, the injection of minority carriers from the collector layer into the base layer can be reduced, so that the accumulation time can be shortened. (3) In the input level converter 201 according to the preferred embodiment, the base signal or collector signal of the drive transistor Q2 is connected to the charging pipette τ of the output transistor via the MOS buffer 1 having a high input impedance and a voltage amplification function. , the operating speed of the output transistor Q is improved due to the high input impedance and voltage amplification function of this MOS buffer.

(4) In the preferred embodiment of the input level converter 20, the connection between the input terminal IN and the drive transistor Q2 is a PNP emitter transistor Q.
By connecting , and the PN junction diode D4,
Not only can the input threshold voltage of the input level converter 201 be appropriately set, but also the input impedance at the base of the PNP transistor Q is improved due to the current amplification effect of the transistor Q, so that the TTL level voltage connected to the input terminal IN is improved. It is possible to reduce the influence of the output impedance of the signal source.

(5) MOS
Compared to a FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of an output level converter and its output capacitance. Dependency can be reduced.

(6) In the output level converter 221, a Schottky transistor that performs multiple carrier operation is connected between the base and collector of the bipolar transistor driven into the saturation region.
Since the barrier diode is connected, the injection of minority carriers from the collector layer into the base layer can be reduced, so that the accumulation time can be reduced.

(7) In the output level converter 221 according to the preferred embodiment, by connecting a high input impedance MO8 circuit between the output of the internal logic block 21 and the base of the drive transistor Q I +, the MOS of this MO8 circuit is Since the current flowing from the gate of the FET to the output of the internal logic block 21 can be reduced to a negligible level, it is possible to prevent a reduction in the integration density and switching speed of the output circuit of the internal logic block 21.

(8) In the output level converter 221 according to the preferred embodiment, the high input impedance MO8 circuit is provided with a function of logically processing a plurality of output signals of the internal logic block 21. The degree of freedom in designing the semiconductor integrated circuit device IC can be improved.

(9) In the output level converter 221 according to the preferred embodiment, the output terminal OUT is
, is arranged in a 70-ting state, so when this output terminal OUT and the output terminal of another logic circuit are commonly connected, the level of this common output terminal is can be set by the output of the logic circuit.

(10) According to a preferred embodiment, the internal logic block 21, whose power consumption is reduced by being configured with a pure CMOS circuit or quasi-CMO8 circuit, is arranged in the center of the semiconductor chip surface, and a plurality of bipolar transistors are arranged in the center of the semiconductor chip surface. Input level converter 201- with high power consumption
-- By arranging the output level converter 221 and the output level converter 221 at the periphery of the semiconductor chip surface, heat dissipation is facilitated, so the logic semiconductor integrated circuit device IC is made to have a discharge finless structure to reduce its cost. I was able to do that.

(11) According to the preferred embodiment, since the logic semiconductor integrated circuit device IC has a resin-sealed structure, its cost can be reduced.

(12) On the other hand, the input terminal IN of the input level converter 201
, is not applied to the date of the MOS FET, but is applied to the cathode of the Siratchi barrier gate D1 or the base of the PNP transistor Q, so that the breakdown strength against the surge voltage applied to the input terminal IN, I was able to improve.

Although the invention made by the present inventor has been specifically explained above based on examples, it should be noted that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist of the invention. Not even.

For example, in FIG. 6, the level converters 201, 202--1-2On of the input buffer 20 are ECL-CMO
It is also possible to perform S level conversion and the level converters 221.222-=22m of output buffer 22 to perform 0MO8-ECL level conversion. For this purpose, an input buffer 20. Internal logic block 21.
The output buffer 22 is connected to the ground level and the negative power supply voltage -V.
Needless to say, it is better to operate with EE. Similarly, in FIG. 6, the level converters 201 and 202=-2On of the input buffer 20 perform i2L-CMOS level conversion, and the level converters 201 and 202 of the output buffer 22 perform i2L-CMOS level conversion.
21.222--22m can also be configured to perform 0MO8-i2L level conversion.

Furthermore, in the embodiments of FIGS. 14 to 21, FIGS. 23 to 26, and FIGS. 29 to 30, the PNP emitter seven-lower transistor Q4 of FIG. P.N.
A junction diode D2 may be added.

In addition, the reason why the ratio W/L ratio of MOS FET is set to 3 is because the channel length of MOS FET is 3 μm.Currently, with improvements in photolithography, this channel length can be increased to 2 μm, 1.5 μm, and even more. 1μ
As miniaturization progresses to the next level, the difference in the ratio W/L will become smaller.

Further, along with this miniaturization, the element dimensions of bipolar transistors will continue to be reduced, and the resistance values of resistors in the circuit will also change.

Also, a large number of leads L, ----L from the sealing resin 301
The method for taking out s4 is also not limited to the embodiment shown in FIG. 39. It is more suitable for miniaturizing the lead frame LT and the circuit device IC to make the outer shape of the sealing resin 301 almost square rather than rectangular and to take out a large number of lead cracks - L-s4 from all four sides. The packaging density will be improved.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to a logic semiconductor integrated circuit device, but the present invention is not limited thereto.

For example, on a semiconductor chip there may be an input buffer 20° internal logic block 21 . Not only the output buffer 7 but also the bipolar analog circuit as required.

It goes without saying that any one of the MOS/analog circuit, the P-channel MO8-logic circuit, the N-channel MO8-logic circuit, and the ECL circuit can be arranged on the semiconductor chip.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a logic semiconductor integrated circuit device IC that was studied by the inventor of the present invention prior to the present invention, and FIG. 3 shows the output capacitance dependence of the propagation delay time of the input buffer shown in FIG. 2, and FIG. 5 shows the output load capacitance dependence of the propagation delay time of the output para7T in FIG. 4, and FIG. 6 shows a block diagram of a logic semiconductor integrated circuit device according to an embodiment of the present invention. , Figures 7 and 8 are CMO8-NA of the circuit device in Figure 6.
9 and 10 show circuit examples of the circuit device CMO8- and NOR gate 21Q shown in FIG. 6, and FIGS. 11 and 12 show the circuit example of the circuit shown in FIG. FIG. 13 shows a circuit example of a CMO8-R-37 lip-70 flip-flop in the internal logic block 21 of the device, and FIG. 14 to 31 show various circuit diagrams of the level converter 201 of the input buffer 20 according to embodiments of the present invention, and FIGS. Various circuit diagrams of the level converter 221 of the output rose 7721 according to the embodiment are shown, and FIG. 35 shows the first and second propagation delay times tp) It, y
The third section shows the input/output waveform diagram for defining tpLll.
FIG. 7 shows the layerer F of each circuit block on the surface of the semiconductor chip of the semiconductor integrated circuit device for logic according to the embodiment of the present invention, and FIG. 38 shows the lead of the semiconductor chip of the semiconductor integrated circuit device for logic according to the embodiment of the present invention. A structural diagram showing the connection of the frame LF to the tab lead Lt and the connection of the bonding wire is shown, FIG. 39 shows a completed diagram of the circuit device according to the embodiment of the present invention after being sealed with resin, and FIG. 7 shows a block diagram of an electronic system configured by mounting a circuit device according to an embodiment of the invention and other circuit devices on a printed circuit board. Fig. 14 Fig. 16 Fig. 2 and Fig. 18 Fig. 15, it is impossible Fig. 17 Fig. 19 Fig. 20 32 Figure 2ad Figure 33 Figure 34 Figure 35 Inside the Takasaki factory

Claims (1)

[Claims] 1. A semiconductor integrated circuit device includes: (1) an internal logic block (2) that operates at a CMOS level;
1) and (2) CMO as an input signal of the internal logic block (21) at its output terminal by supplying an input signal of another logic level such as TTL level to its input terminal.
(3) an output capacitance (C) of the input level converter (201);
8) for performing charging or discharging of the converter (2).
A semiconductor integrated circuit device characterized in that the output transistor of item 01) is constituted by a bipolar transistor.