JPH02220276A - 0 track detector for floppy disk device - Google Patents

Abstract

PURPOSE:To prevent erroneous detection without complicating the constitution by generating a 0 track signal at the time when a track counter to be reset at the time of initialization and a 0 track sensor indicate the 0 track together for a certain time. CONSTITUTION:At the time of initialization for power-on or the like, a track counter 3 is reset by the Q output of a D type FF to which the reset pulse is supplied from a reset pulse output circuit 1, and the output of a NAND gate 7 goes to the high level, and the output of a NAND gate 14 goes to the high level through a NOR gate 9 when a 0 track sensor input terminal 8 detects the 0 track. When the counter 3 and the 0 track sensor indicate the 0 track together for a certain time, the 0 track is detected by a shift register 15 controlled by a timer circuit 16, and the 0 track indication signal is outputted from the NAND circuit 19. Thus, the 0 track signal is not outputted for erroneous detection of the 0 track sensor without complicating the constitution, and the 0 track is accurately detected without erroneous detection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to the 0 track of a floppy disk device that detects the 0 track during a seek operation of the floppy disk device.
The present invention relates to a track detection device.

[Prior Art] Conventionally, O-track detection in a floppy disk device has been performed only by an O-track sensor.

[Problems to be Solved by the Invention] However, in the conventional O-track detection method described above, when the head seeks to a track near the O-track, the sensor is momentarily turned on due to damping, and the 0-track detection signal is erroneously output. Sometimes it would output . Therefore, conventionally, there has been a problem in that the motor control section must take measures against damping during seek.

The present invention has been devised in view of these problems, and is a floppy disk device that can prevent false detection of zero track and perform accurate zero track detection without requiring any special damping measures. An object of the present invention is to provide a track detection device.

[Means for Solving the Problems] A 0 track detection device for a floppy disk device according to the present invention includes means for generating a reset pulse when initializing the floppy disk device, and means for generating a stepping motor when reset by the reset pulse. a track counter that counts up or down with a driving step pulse and displays the current track position; a 0 track sensor that detects the 0 track;
The present invention is characterized in that it includes means for outputting an O-track signal when both the 0-track sensor and the track counter display an O-track for a certain period of time.

[Operation] In the present invention, a track counter is reset when a floppy disk is initialized, and the current track position is displayed by counting up or down by a step pulse. Then, on condition that the output of this track counter and the output of the 0 track sensor both indicate 0 track for a certain period of time, a 0 track signal is output.

Therefore, in the present invention, compared to the conventional method which outputs the 0 track signal based only on the output of the 0 track sensor,
The reliability of 0 track detection is increased, erroneous detection of 0 track can be prevented, and accurate 0 track detection can be performed without requiring any special measures against damping.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing a 0 track detection device for a floppy disk device according to an embodiment of the present invention.

The reset pulse output circuit 1 is a circuit that outputs a reset pulse during initialization such as when power is turned on. A reset pulse output from the reset pulse output circuit 1 is input to a set terminal of a D-type flip-flop 2. This D-type flip-flop 2 inputs a 0 track signal, which will be described later, to a clock input terminal, and outputs its output Q to a reset terminal of a track counter 3.

The track counter 3 receives a step pulse inputted through a step pulse input terminal 11 through a NAND gate 12.
is input as a clock signal via the stepping motor, and the count value is counted up or down depending on the direction of movement of the stepping motor. In addition, the above NAND gate 1
The step pulse outputted from 2 is also supplied to a stepping motor excitation pulse output circuit 4. The stepping motor excitation pulse output circuit 4 is an output circuit that outputs an excitation pattern to the two-phase stepping motor. A two-phase stepping motor has four excitation patterns, and during continuous seek operation, the stepping motor excitation pulse output circuit 4 repeatedly outputs these four excitation patterns.

The output of the track counter 3 is input to the NOR gate 5, where the output of all bits of the track counter 3 at "L" level, i.e., the o-track display output, is detected. Further, the output of the stepping motor excitation pulse output circuit 4 is input to the NOR gate 6, where the excitation pattern that excites the o track among the four excitation patterns output from the output circuit 4 is detected. ing. The outputs of these NOR gates 5 and 6 are N
It is input to AND gate 7. The NAND gate 7 outputs a signal if both of these two track detection means indicate the possibility of detecting a 0 track.

On the other hand, the detection output from the 0 track sensor (not shown) is
The signal is input from the 0 track sensor input terminal 8, and this input signal and the output of the NAND gate 7 are input to the NOR gate 9. The NOR gate 9 sets its output to the "H" level when any of these input signals indicates the possibility of detecting the O track.

The output of this NOR gate 9 is input to one input of a NAND gate 10. The output Q of the D-type flip-flop 2, which is set at the time of initialization, is input to the other input of the NAND gate 10. This N
The output of the AND gate 1o is input to one input of the NAND gate 12, and prevents the step pulse from being input to the track counter 3 and the stepping motor excitation pulse output circuit 4.

Further, the output of the NOR gate 9 is applied to one input of a NAND gate 14 via an inverter 13.

The output Q of the flip-flop 2 described above is applied to the other input of the NAND gate 14. The output of the NAND gate 14 is input to the reset terminal of the shift register 15. This shift register 15 sequentially shifts in the contents of the data terminal, that is, the "HIT level" using the shift clock output from the timer circuit 16.

The output of this shift register 15 is input to an AND gate 18, where it is detected that all bits are at the "H" level. The output of this AND gate 18 is input to a NOR gate 17 and a NAND gate 19. NO
In the R gate 17, all bits of the shift register 15 are “H”
After outputting , block the subsequent shift clock. Further, the NAND gate 19 outputs the output of the NOR gate 9, that is, the track counter 3, the excitation pulse output circuit 4, and the output of the NOR gate 9.
When all the track sensors detect O-tracks and when the shift register 15 counts a certain period of time, a 0-track signal is output to the outside via the O-track signal output terminal 20.

Next, the operation of the 0 track detection device according to this embodiment configured as described above will be explained.

First, at the time of initialization such as when the power is turned on, a reset pulse is output from the reset pulse output circuit 1 to the D-type flip-flop 2, and the output Q of the D-type flip-flop 2 becomes "HI+ level" and the track counter 3 is reset. Counter 3 is set to 0 during initialization.

Therefore, the output of NOR gate 5 becomes "H" level. Furthermore, when the excitation pattern output from the stepping motor excitation pulse output circuit 4 becomes the same as the output pattern that excites the 0 track, the output of the NOR gate 6 becomes the °"HI+ level, and thereby the output of the NAND gate 7 becomes "L".
Since the signal is at the ゛° level, the input signal from the 0 track sensor input terminal 8 appears inverted at the output of the NOR gate 9.

In this embodiment, the input signal from the 0 track sensor input terminal 8 outputs the "L" level when the 0 track is detected. At this time, the output of the D-type flip-flop 2 is at the H level, so when the input signal of the 0 track sensor input terminal 8 detects the O track, the output of the NAND gate 10 becomes the L level and the NAND gate 12 output is “H”
Therefore, the step pulse input from the step pulse input terminal 11 is not input to the stepping motor excitation pulse output circuit 4, and the stepping motor is in a stopped state.

At this time, the output of the NAND gate 14 becomes "H" level, and the reset of the shift register 15 is released. The period of the shift clock output from the timer circuit 16 is set to a time that takes into account damping during seek. The shift register 15 remains in the reset state until the 0 track sensor detects the 0 track, but the NAND gate 14
When the output reaches the HIT level, the shift register 15 latches the HII level using the shift clock from the timer circuit 16 while detecting the 0 track.
When all the outputs of the
The supply of the shift clock to 5 is stopped by the NOR gate 17.

From then on, shift register 1 is used until it is initialized again.
5 does not work.

On the other hand, if the 0 track sensor stops detecting the 0 track before all of the shift registers 15 reach the "lH+" level, the shift register 15 is reset.

At this time, since the output of the NAND gate 10 becomes "H" level, a step pulse is supplied from the step pulse input terminal 11 to the stepping motor excitation pulse output circuit 4, and the stepping motor is operated.

The above operation causes all the outputs of the shift register 15 to be “
This is performed until the shift register 15 reaches the "H" level.
becomes "H" level, and the output from the NAND gate 19 and the NOR gate 9 is output as a 0 track signal, which is output from the O track signal output terminal 20. With this signal, the D-type flip-flop 2 latches the "L I+ level" and the NAND gate 10 and the NAND gate 1
4 and releases the reset of the track counter 3.

Next, the operation of the 0 track detection device of this embodiment during normal operation will be explained.

At this time, since the output of the NAND gate 10 is fixed at the "H" level, the step pulse input from the step pulse input terminal 11 is always sent to the track counter 3 and the stepping motor excitation pulse output circuit 4 via the NAND gate 12. Supplied. The track counter 3 receives data in the theta direction from the stepping motor excitation pulse output circuit 4, counts up when seeking to the outer circumference, and counts down when seeking to the inner circumference.
Data from the track sensor input terminal 8 is inverted and output from the NOR gate 9 when the track counter 3 is 0 and the output of the stepping motor excitation pulse output circuit 4 is the same as the output pattern that excites the 0 track. Ru. Since all the data in the shift register 15 is stopped at the "HIT" level, the AND gate 18 becomes "H" level, and the output of the NOR gate 9 is output from the NAND gate 19.
The signal is inverted by 0 and output from the 0 track signal output terminal 20.

As described above, in the normal mode, when the track counter 3, stepping motor excitation pulse output circuit 4, and 0 track sensor output all indicate O track detection, 0
A 0 track signal is output from the track signal output terminal 20.

[Effects of the Invention] As explained above, the present invention outputs a 0 track signal when the output of the track counter and the output of the 0 track sensor both indicate 0 track for a certain period of time. Even if the track sensor makes an erroneous detection, the zero track signal will not be output, and there is an effect that the reliability of O track detection can be improved without taking any special damping measures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an O-track detection device for a floppy disk device according to an embodiment of the present invention. 1; Reset pulse output circuit, 2; D-type flip-flop, 3; Track counter, 4; Stepping motor excitation pulse output circuit, 5, 6, 9° 17; NOR gate,
7, 10, 12.14.19; NADA Gate, 8
;0 track sensor input terminal, 11;step pulse input terminal, 13:inverter, 15;shift register, 1
6; timer circuit, 18; AND gate, 20; 0 track signal output terminal

Claims (1)

[Claims] (1) means for generating a reset pulse when initializing a floppy disk device; a track counter that is reset by the reset pulse and counts up or down by a step pulse that drives a stepping motor to display the current track position; The present invention is characterized by comprising a 0 track sensor for detecting a 0 track, and means for outputting a 0 track signal when both the 0 track sensor and the track counter display the 0 track for a certain period of time. Zero track detection device for floppy disk drive.