JPH02220203A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To surely correct a reproducing signal and to prevent bit errors from occurring by extracting a specified signal component from output signals from plural signal processing circuits and switching the delay time of plural delay circuits so that the signal level of the corresponding signal component may be made low. CONSTITUTION:Specified data is recorded and reproduced by a magnetic recording and reproducing device by utilizing a partial response system. The reproducing signal SRF outputted from a magnetic tape 5 of the device by magnetic heads 6A and 6B is delayed by the delay circuits 31A-31E of an arithmetic processing circuit 29. The output obtained by detecting the signal level of the output which is processed to be delayed and the reproducing signal SRF are added and outputted from an output adder 35. The signal level of the signal component is extracted from the output signal Sr which is processed to be added by a signal level detection circuit 38. On the basis of the signal level of the signal component, the delay circuits 31A-31E are controlled to be switched by the signal level detection circuits 33A-33E so that the signal level may become small so as to demodulate the output signal Sr.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Problems to be solved by the conventional technical invention (Fig. 7 to 11) E. Means for solving the problem (Fig. 1) F. Effect (Fig. 1) 1
Figure) G Example (Figures 1 to 6) (G1) First Example (Figures 1 to 5) (G2) Second
Embodiment (Fig. 6) (G3) Third embodiment (G4) Other embodiments H Effects of the invention A Industrial application field The present invention relates to a magnetic recording/reproducing device, for example, converting a video signal into a digital signal. The present invention is suitable for application to a magnetic recording/reproducing device configured to record and reproduce data.

B. Summary of the Invention The present invention extracts a predetermined signal component from the output signal of a signal processing circuit in a magnetic recording/reproducing device, and switches the delay time so that the signal level of the signal component becomes small, thereby eliminating bit errors. It is possible to effectively avoid this and obtain playback data.

C. Prior Art Conventionally, in a general video tape recorder as this type of magnetic recording/reproducing device, for example, a video signal is frequency modulated and recorded as an analog signal on a magnetic tape.

D Problems to be Solved by the Invention By the way, by converting the video signal into a digital signal and recording it on a magnetic tape, it is possible to obtain a reproduced video image that does not deteriorate in image quality no matter how many times it is dubbed.

However, as shown in Figure 7, when recording and reproducing signals on a magnetic tape, the CN ratio deteriorates at lower frequencies because the electromagnetic conversion system such as the magnetic head has differential characteristics. As the frequency increases, the CN ratio similarly deteriorates due to the magnetization characteristics of the magnetic tape.

Therefore, in a magnetic recording/reproducing system, a digitized video signal (hereinafter referred to as a digital video signal) has a characteristic that the frequency band in which a good CN ratio can be obtained is narrow.

Therefore, when recording digital video signals, select a recording method that concentrates the signal spectrum near the maximum CN ratio.This effectively avoids deterioration of the CN ratio of the reproduced signal, and Video signals must be efficiently recorded and reproduced.

In this case, a method of recording and reproducing digital video signals using a class ① partial response method, which is one of high-efficiency encoding methods, may be considered.

In other words, in magnetic recording and reproduction, the CN ratio deteriorates at low and high frequencies, so the frequency characteristics are expressed by the class ■ partial response ( 1-D”) can be approximated and expressed as the frequency characteristic H(ω).

By the way, the frequency ω at which the response is minimum. For the delay time T expressed by the delay operator D, there is a relationship as shown in the following equation (1).

Therefore, select the amount of delay represented by delay operator D,
It is thought that if the signal spectrum is concentrated in the vicinity where the CN ratio is maximum, the frequency characteristics of the magnetic recording and reproducing thread can be effectively used to efficiently record and reproduce digital biosignals.

That is, as shown in FIG.
The recording data D*xc is supplied to the precoat circuit 2, and the arithmetic processing expressed by the following formula (2) is sequentially performed on the recording data DIEc. Here, MOD2 represents the remainder of 2.

As a result, as shown in FIG. 10, the recorded data D□, (
FIG. 10(A)) is converted into precoat data DP11 (FIG. 10(B)) by using the correlation with the preceding and succeeding data.

Further, the precoat data DPII is amplified via the amplifier circuit 3 and then recorded on the magnetic tape 5 via the magnetic head 4.

During reproduction, the reproduction signal S□ (FIG. 10(C)) with differential characteristics obtained through the magnetic head 6 is amplified through the amplifier circuit 8, and then the frequency characteristics are corrected and calculated by the equalizer circuit 9. It is applied to the processing circuit 10.

Here, since the electromagnetic conversion system has differential characteristics, the reproduced signal S□ is expressed as (1-D) using the delay operator D, and is expressed by the frequency characteristic shown by the broken line in Figure 8. Ru.

On the other hand, as shown in FIG.
is composed of an adder circuit 11 and a delay circuit 12, and performs (1+D) arithmetic processing on the reproduced signal SIF.

Therefore, during playback, the precoat data D during recording is
The following equation % equation % (1) is applied as a whole to the PI, and as a result, for the calculation processing of the precoat circuit 2, the reproduced signal S to correct.

As a result, the transfer function of the entire recording and reproducing system can be set to 1, and the output signal S whose amplitude rises to a predetermined value or more according to the logic level of the recording data D□0.

(FIG. 10(D)) is obtained.

Thus, in the comparison circuit 13, the predetermined signal level Vl
lKFl and ■□. If the signal level of the output signal SF is detected based on
E)) can be decoded.

By the way, when correcting the playback signal S□ and decoding the playback data D□ in this way, if the correction is not performed correctly for the arithmetic processing of the precoat circuit 2, the playback data DP
There is a possibility that a bit error may occur in I.

In particular, if the amount of delay represented by the delay operator D changes between recording and reproduction, it becomes difficult to obtain correct reproduction data DPI.

In this case, in the calculation process of equation (2), the recorded data D
Since the IIC can be subjected to digital signal processing, changes in the amount of delay can be kept within a practically sufficient range during recording.

However, in the correction of the arithmetic processing circuit 10 expressed by equation (3), since the delay circuit 12 having an analog circuit configuration is used, the amount of delay can avoid temperature fluctuations, thereby obtaining correct reproduction data DP. There are problems that make it difficult.

Furthermore, in a delay circuit having an analog circuit configuration of this kind, the amount of delay itself inevitably varies, and in this case as well, there is a problem that it becomes difficult to obtain correct reproduced data D□.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a magnetic recording and reproducing apparatus that can obtain correct reproduced data.

Means for Solving EvI 11 Points In order to solve this problem, the present invention utilizes a partial response method to
. A magnetic recording and reproducing device 20 configured to record and reproduce
, the reproduction signal S□ output from the magnetic heads 6A, 6B is transmitted to delay circuits 31A, 3.1B, 31C, 31D,
signal processing circuits 31A, 31B, and 31C that perform addition/subtraction processing on the delayed reproduction signal S□ and the reproduction signal S□ output from the magnetic heads 6A and 6B;
131D, 31E, 35 and signal processing circuits 31A, 31
A signal level detection circuit 33A, 3 extracts a predetermined signal component from the output signal S output from the IC, 31D, 31E, 35 and detects the signal level of the signal component.
3B, 33C133D, 33E, 36.38 and signal level detection circuit 33A, 33B, 33C, 33D, 33E
, 36.38, the delay circuits 31A, 31B, 31 are arranged so that the signal levels of the signal components are reduced.
C.

The signal processing circuits 31A, 31B, 31C, 31D are equipped with delay time switching circuits 33A, 33B, 33C133D, 33E, and 36 for switching the delay times of 31D and 31E.
Based on the output signals S2 of 31E and 35, the recorded data DPI is decoded.

F action signal processing circuit 31A, 31B, 31C1310, 31E
, 35, and extracts a predetermined signal component from the output signal SF output from the delay circuits 31A, 31B, 31C, 31D, 31E so that the signal level of the signal component is small (
By switching the delay time of the delay circuit 31A,
, 31B, 31C, 131D, and 31E, or the delay time varies, it is possible to reliably correct the reproduced signal S□ and prevent bit errors.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) In FIG. 1, in which parts corresponding to those in FIG. 9 of the first embodiment are denoted by the same reference numerals, 20 indicates a video tape recorder as a whole;
The video signal Sv is applied to an analog-to-digital conversion circuit 22 configured to operate with a clock signal Sct that is four times as large as the subcarrier signal.

2, an 8-bit digital video signal Dv is obtained, and the data is compressed by a data compression circuit 24 and converted into data DI of about 25 (MBPS).

On the other hand, the error correction circuit (ECC) 26 receives the data-compressed digital video signal DI together with the digitally processed audio signal D.
Shittering, code addition for error correction, etc. are performed, and as a result, approximately 30 (MBPS) of recording data D-0 is output.

As shown in FIG. 2, the precoat circuit 2 receives recording data I)ate from an exclusive OR circuit 2A, and converts the output data of the exclusive OR circuit 2A into recording data D□. The signal is fed back to the input terminal via two-stage delay circuits 2D1 and 2D2 that operate at a repetition frequency of 30 (MHz).

As a result, it is possible to obtain precoat data DPI through the precoat circuit 2, which has been subjected to the arithmetic processing of equation (2).

Furthermore, in this embodiment, an adder circuit 28 is inserted between the precoat circuit 2 and the amplifier circuit 3,
As a result, as shown in FIG. 3, the precoat data D□ output from the precoat circuit 2 is divided into predetermined blocks, and predetermined data Dp is added before and after each block to form a preamble and a postamble. is being done.

In the preamble, the frequency 15 (MH
z) is recorded, and the frequency of the reference signal is (
1) Frequency ω that satisfies the formula. has been selected to be.

Additionally, in this embodiment, a rotating drum (not shown)
The output signal of the amplifier circuit 3 is sequentially and alternately outputted to the magnetic heads 4A and 4B which are arranged at an angular interval of 180 degrees above, thereby generating precoat data D□ to which a postamble and a preamble have been added. , are recorded on the recording track in block units.

Therefore, as shown in FIG. 4, during the heating period, the switching pulse signal SW
Precoat data DP sandwiched between preamble and postamble data in synchronization with P (Fig. 4 (A))
The reproduction signal S of t. (Fig. 4(B)) can be obtained.

The reference signal generation circuit 28 having a PLL circuit configuration receives the reproduced signal S□ output from the equalizer circuit 9, and thereby creates a reference clock signal SC1+1 based on the reference signal recorded in the preamble.

On the other hand, the arithmetic processing circuit 29 has delay circuits 3IA, 3
1B, 3 IC, 31D, and 31E, and output signals of the delay circuits 31A to 31E to switch circuits 33A, 33B, 33C, and 33D, respectively.
The signal is output to the adder circuit 35 via 33E.

The delay circuits 31A to 31E have a repetition period T (i.e. a repetition frequency of 30 (MHz) of the precoat data DPI).
), the delay times are 30 (nssc) and 32, respectively.
(nsec), 33 (nsac), 34 (ns
ec), 36 (nsec).

On the other hand, in switch circuits 33A to 33H,
The contacts are switched based on the control signal S output from the control circuit 36, and thereby the delay circuit 31
Select the desired delay circuit from A to 31E and add the adder circuit 3.
The delay time of the reproduced signal S□ outputted to the circuit 5 can be switched.

Therefore, as shown in FIG. 5, the arithmetic processing circuit 29 executes the arithmetic processing of (1+D), and as a result, the differential characteristic of the electromagnetic conversion system and the arithmetic processing circuit 29 perform the arithmetic processing of (1+D). The reproduced signal 5IIF can be corrected.

Furthermore, according to the switching of the switch circuits 33A to 33H, the minimum response frequency ω determined by the delay operator D
・are frequencies ω1, ω1, ω determined by the delay times of the delay circuits 31A to 31H. , ω1, ω.

By the way, the delay circuit 31A having this kind of analog circuit configuration
31B has a feature that when the delay time of one delay circuit changes due to temperature, the delay time of the other delay circuits changes similarly.

Therefore, for example, when the delay circuit 31C is selected and the delay time of the delay circuit 31C changes from 33 (nsec) to 34 (nsec), the original delay time is 1 (nsec) shorter than that of the delay circuit 31C. Delay circuit 3
1B, the arithmetic processing circuit 29
It is possible to prevent temperature fluctuations in the frequency characteristics in advance.

That is, the signal level detection circuit 3B is configured to detect the signal level of the output signal SF output from the adder circuit 35 at the timing of the preamble, and output the detection result to the control circuit 36.

In contrast, the control circuit 36 uses the reference clock signal scg
+, a control signal Sc is output to the switch circuits 33A to 33E, and the switch circuit 33 is sequentially output for each preamble.
It is designed to switch the contacts A to 33E (Fig. 4 (C1), (C2), (C3), (C4) and (C
5)).

As a result, the frequency characteristics in the arithmetic processing circuit 29 are sequentially switched to the frequency characteristics determined by the delay circuits 33A to 33E for each preamplule. It is possible to detect the signal level of the reference signal recorded in the preamble when .about.33B is selected.

Further, the control circuit 36 includes each switch circuit 31A to 31E.
Each circuit has a memory circuit configured to store the detection results of the signal level detection circuit 38, and the contents of the memory circuit are stored in the signal level detection circuit 38 in synchronization with the switching operation of the contacts of the switch circuits 33A to 33E. The information is updated with 38 detection results.

Furthermore, the control circuit 36 compares the contents of the memory circuits, selects the switch circuits 33A to 33E so that the signal level of the reference signal is the minimum, and closes the contacts of the switch circuits during a period other than the preamble. (In the case of Fig. 4, the switch circuit 31D
).

In the reference signal thus recorded in the preamble, the frequency is equal to the repetition frequency 30 of the precoat data D□.
The frequency 15 [M7] is selected as 1/2 of [M7], and (
1) Frequency ω that satisfies the formula. Therefore, by switching the contacts of the switch circuit so that the signal level of the reference signal output from the adder circuit 35 is minimized, the reproduced signal is S□ can be corrected accurately.

In practice, delay circuits with this type of analog circuit configuration have a characteristic that the delay time fluctuates slowly, and as in this embodiment, the signal level of the reference signal is detected for each preamble and the delay circuit is switched. However, fluctuations in frequency characteristics can be prevented within a practically sufficient range.

Furthermore, even when the delay times of the delay circuits 31A to 31H vary, the calculation processing of the precoat circuit 2
The reproduced signal SIF can be corrected accurately.

In this way, it is possible to effectively avoid fluctuations in frequency characteristics due to fluctuations in delay time, etc., and thereby, based on the output signal S of the arithmetic processing circuit 29, reproduced data D□ can be decoded while preventing bit errors. be able to.

Incidentally, in a magnetic recording/reproducing apparatus using the magnetic tape 5 as a recording medium, fluctuations in the time axis of the reproduced signal SIF are unavoidable, and the frequency of the reproduced signal S□ may change with respect to the time of recording.

In this case, even if the delay time of the reproduction system is accurately maintained at a predetermined time, the frequency of the reproduction signal S□ changes, so that bit errors eventually occur in the decoded reproduction data D□.

However, in the case of this embodiment, the frequency characteristics of the arithmetic processing circuit 29 are set so that the signal level of the reference signal output from the adder circuit 35 is minimized, so the frequency of the reproduced signal S is changed. Even if the magnetic tape 5 is used, it is possible to follow this and make accurate corrections, thereby preventing bit errors even when using the magnetic tape 5.

The error detection and correction circuit 40 receives the reproduced data DPI output from the comparison circuit 13, detects bit errors, corrects the bit errors, and then outputs the audio signal 30-
and video signal data.

The data expansion circuit 41 receives the data of the video signal separated by the error detection and correction circuit 40, and expands the data in the opposite manner to the data compression circuit 24.

In this way, the video signal SVF■ can be obtained via the digital-to-analog conversion circuit 42.

Incidentally, in this embodiment, the delay circuits 31A to 31E
The adder circuit 35 delays the reproduction signal S□ output from the magnetic heads 6A, 6B with the delay circuits 31A to 31B, and the delayed reproduction signal S□ and the reproduction signal S output from the magnetic heads 6A, 6B. The control circuit 36, switch circuits 33A to 33E, and signal level detection circuit 38 constitute a signal processing circuit that adds and outputs □.
A signal level detection circuit is configured to extract a predetermined signal component that is a reference signal from the output signal S output from the signal processing circuit (31A to 31E, 35) and detect the signal level of the signal component.

Further, the control circuit 36 and the switch circuits 33A to 33E include signal level detection circuits (33A to 33E136.38).
Based on the detection result, a delay time switching circuit is configured to switch the delay times of the delay circuits 31A to 31E so that the signal level of the reference signal becomes small.

In the above configuration, the video signal Sv is converted into a digital video signal Dv by the analog-to-digital conversion circuit 22, and then compressed into data Da of about 25 (MBPS) by the data compression circuit 24.

The compressed data D is sent to the error correction circuit 26.
Along with the audio signal, processing such as shunting and addition of codes for error correction is performed, and the processing speed is approximately 30 [M'BPS].
Recorded data D□. is converted to

The recording data DRtc is subjected to the arithmetic processing of equation (2) in the precoat circuit 2 and converted into precoat data D, which is then divided into blocks and recorded on the magnetic tape 5, and at the same time, the frequency 15 (M) A preamble is formed in which the reference signal of tz) is recorded.

On the other hand, the reproduction signal 5IIF output from the magnetic heads 6A and 6B is given to the reference signal generation circuit 28,
A reference clock signal 5cot is created based on the reference signal obtained from the preamble.

Furthermore, the reproduction signal 5IIF is generated by sequentially switching the contacts of the switch circuits 31A to 31H in the arithmetic processing circuit 29, so that the reference signal recorded in the preamble is extracted from the output signal SF of the arithmetic processing circuit 29, and its signal level is is detected.

As a result, the signal level of the reference signal output from the adder circuit 35 is minimized by the delay circuits 31A, 31B, 31C,
31D or 31E is selected, and the reproduction signal S□ is corrected for the arithmetic processing of the precoat circuit 2.

The corrected output signal S is decoded into reproduced data D□ by the comparator circuit 13, and then sequentially passed through an error detection and correction circuit 40, a data expansion circuit 41, and a digital-to-analog conversion circuit 42, in the opposite manner to that during recording. It is converted into a video signal S□.

According to the above configuration, the switch circuits 33A to 33E are switched at the timing of the preamble, and the arithmetic processing circuit 2
detect the signal level of the reference signal from the output signal SF of 9;
The delay circuits 31A to 31A are configured to minimize the signal level.
By switching 31E, it is possible to accurately correct the reproduced signal S□ and obtain reproduced data D□ in which bit errors are effectively reduced even if the delay time varies due to temperature, variations, etc.

(G2) Second Embodiment In FIG. 6, in which parts corresponding to those in FIG. 25B, 52C, 52D
, 52E are provided.

That is, the main delay circuit 51 has a delay time of, for example, 2B (
naec), whereas the sub delay circuits 52A~
52E has a delay time of 2 (nsec) and 4
(naac), 5 (nsec), 6 (nsec),
13 (nsec).

As a result, when the switch circuits 33A to 33E are sequentially turned on, it takes 30 (nsec), respectively.
32 (nssc), 33 (nsec), 34
(nsec), the reproduced signal S□ delayed by 36 (nsec) is output to the adder circuit 35.

Therefore, by selecting the sub-delay circuits 52A to 52E, the temperature
Even if the delay time changes due to variations etc., the reproduced signal SI
It is possible to accurately correct F and obtain reproduced data D□ in which bit errors are effectively reduced.

Furthermore, if a plurality of sub-delay circuits 52A to 52E are selected for the main delay circuit 51 in this way,
The delay time is 30 (nsec) and 32 (nsec), respectively.
c) , 33 (nsec) , 34 (nsec)
, 36 (nsec) delay circuits are independently provided, the entire arithmetic processing circuit 50 can be made smaller.

According to the configuration of FIG. 6, even if the sub-delay circuits 52A to 52E are selected, the same effects as in the first embodiment can be obtained.

(G3) Other Embodiments In the above embodiment, a case was described in which a reference signal recorded in a preamble was extracted from an output signal of an arithmetic processing circuit and the signal level of the reference signal was detected. The invention is not limited to this, and a reference signal may be recorded in the postamble and the signal level of the reference signal may be detected.

Furthermore, in the above-described embodiment, the reference signal is extracted from the output signal S of the arithmetic processing circuit by switching the switch circuit at the preamble timing, and the signal level is detected. Not limited to the reference signal, for example, a signal component that is provided in a bandpass filter circuit and has a frequency that is 1/2 of the repetition frequency of the precoat data D□ is used as the output signal SF of the adder circuit 35.
, and the delay circuit may be switched so that the signal level of the signal component is minimized.

Furthermore, in the above-described embodiment, a case was described in which a plurality of delay circuits were switched, but the present invention is not limited to this.
For example, the delay time may be changed by using a delay circuit having a plurality of taps and switching the taps of the delay circuit.

Further, in the above-described embodiment, a case has been described in which the five delay circuits are sequentially switched at the preamble timing, but the present invention is not limited to this, and the switching order may be changed as necessary.

Further, in the above-described embodiment, a case was described in which the output signal of the arithmetic processing circuit was decoded by the comparator circuit, but the present invention is not limited to this.
It can also be widely applied to decoding using algorithms such as ON).

Furthermore, in the above embodiment, a case was described in which a digital video signal is recorded and played back by applying a class ■ partial response method, but the present invention is not limited to this, and for example, a case where a class ■ partial response method is applied is described. It can also be widely applied to recording and reproducing digital video signals.

Further, in the above-described embodiments, the case where digital video signals are recorded and reproduced has been described, but the present invention is not limited to this, and can be widely applied to cases where various digital signals are recorded and reproduced.

Further, in the above-described embodiment, a case was described in which desired data was recorded and reproduced on a magnetic tape, but the present invention is not limited to magnetic tapes, but is applicable to a wide range of magnetic recording and reproducing apparatuses that record and reproduce data on magnetic recording media. be able to.

Effects of the Invention As described above, according to the present invention, by extracting a predetermined signal component from the output signal of the signal processing circuit and switching the delay time so that the signal level of the signal component is minimized, Even if the delay time varies due to variations or the like, it is possible to accurately correct the reproduced signal, and thus it is possible to obtain a magnetic recording and reproducing apparatus that can effectively reduce bit errors in reproduced data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video tape recorder according to an embodiment of the present invention, FIG. 2 is a block diagram showing its precoat circuit, FIG. 3 is a route map showing the structure of data recorded on a magnetic tape, and FIG. 4 is a signal waveform diagram explaining the operation of the switch circuit, FIG. 5 is a characteristic curve diagram showing the frequency characteristics of the arithmetic processing circuit, and FIG. 6 is a block diagram showing the arithmetic processing circuit according to the second embodiment. Figure 7 is a characteristic curve diagram showing the frequency characteristics of the magnetic recording and reproducing system, Figure 8 is a characteristic curve diagram used to explain the partial response method of class ■, and Figure 9 is a characteristic curve diagram showing the frequency characteristics of the magnetic recording and reproducing system.
FIG. 10 is a block diagram showing a video tape recorder to which the partial response method is applied, FIG. 10 is a signal waveform diagram for explaining its operation, and FIG. 11 is a block diagram showing an arithmetic processing circuit. 1.20...Video tape recorder, 2...
... Precoat circuit, 5 ... Magnetic tape, 1
0.29.50... Arithmetic processing circuit, 2DI, 2
D2.12.31A-31B, 51.52A-52E・
...Delay circuit.

Claims (1)

[Claims] In a magnetic recording and reproducing device that records and reproduces predetermined data using a partial response method, a reproduction signal output from a magnetic head is delayed by a delay circuit, and the delayed reproduction a signal processing circuit that performs addition/subtraction processing on the signal and the reproduced signal output from the magnetic head; and a signal processing circuit that extracts a predetermined signal component from the output signal output from the signal processing circuit, and a signal level of the signal component. a signal level detection circuit that detects the signal level, and a delay time switching circuit that switches the delay time of the delay circuit so that the signal level of the signal component is reduced based on the detection result of the signal level detection circuit, A magnetic recording/reproducing device characterized in that recorded data is decoded based on an output signal of a processing circuit.