KR100202209B1 - Digital signal reproducing apparatus - Google Patents

Abstract

The present invention relates to a magnetic recording and reproducing apparatus suitable for application to a magnetic recording and reproducing apparatus adapted to convert a video signal into a digital signal for recording and reproducing.

k)가 소정값 D_REF1와 D_REF2사이에 들어갈 때, 재생 신호(S_RF)의 신호 레벨을 검출하는 신호 레벨 검출 수단(70,71,72)과, 상기 신호 레벨 검출 수단(70,71,72)의 검출 결과에 의하여, 재생 신호(S_RF)의 신호 레벨을 보정하는 신호 레벨 보정 수단(31, 73)을 제공한다.In the present invention, by using a partial response method, the predetermined data D _REC is recorded on the magnetic recording medium 5, and the reproduction signal S _RF obtained from the magnetic recording medium 5 is Viterbi. In the magnetic recording and reproducing apparatus 20, which is decoded by the decoding circuits 40 and 41, the decode output of the Viterbi decoding circuits 40 and 41 causes reliable data of a decode value corresponding to the reproduction signal level H (

signal level detecting means 70, 71, 72 for detecting a signal level of a reproduction signal S _RF when k) falls between a predetermined value D _REF1 and D _REF2 , and the signal level detecting means 70, 71, By the detection result of 72, signal level correction means 31, 73 for correcting the signal level of the reproduction signal S _RF is provided.

Description

Magnetic recording and playback device

1 is a block diagram showing a video tape recorder according to an embodiment of the present invention.

2A to 2E are signal waveform diagrams for explaining the operation thereof.

3 is a block diagram showing a precode circuit.

4 is a characteristic curve diagram showing frequency characteristics of a magnetic recording and reproducing system.

5 is a characteristic curve diagram that provides a description of the partial response scheme of class IV.

6 is a schematic diagram showing free code data.

7 is a block diagram showing an arithmetic processing circuit.

8 and 9 are diagrams for providing an explanation of the operation of the arithmetic processing circuit.

10 and 11 are block diagrams showing equivalent circuits of the magnetic recording and reproducing system.

12 is a block diagram showing a Viterbi decoding circuit.

13A to 13D, 14A and 14B, 15, 16, 17, 18A and 18B are diagrams provided in the operation description thereof.

19 is a block diagram provided for explanation of the problem.

* Explanation of symbols for main parts of the drawings

1,20: video tape recorder 5: magnetic tape

28: precode circuit 31: variable gain amplifier circuit

32: arithmetic processing circuit 37: analog digital conversion circuit

40, 41: Viterbi decoding circuit 53, 55, 70: comparison circuit

71: switch circuit 72: digital analog conversion circuit

73: sample hold capacitor

The present invention relates to a magnetic recording and reproducing apparatus, and is suitable for application to, for example, a magnetic recording and reproducing apparatus configured to convert a video signal into a digital signal for recording and reproducing.

In the magnetic recording and reproducing apparatus, the signal level of the reproduction signal is detected only when certain data of the Viterbi decoding circuit falls within a predetermined range, and the signal level of the reproduction signal is corrected as a result of the detection so that the noise of the reproduction signal is reduced. Even when mixed, the bit error can be reduced.

Conventionally, as a kind of magnetic recording reproduction of this kind, in general video tape recorders, video signals are frequency-modulated and recorded as analog signals on magnetic tape.

However, if the video signal is converted into a digital signal and recorded on a magnetic tape, it is considered that the image quality can be effectively avoided even if dubbed several times.

In this case, for example, a video tape recorder 1 of the configuration as shown in FIG. 19 is considered.

That is, during recording, predetermined recording data D _REC is recorded on the magnetic tape 5 via the amplifier circuit 3 and the magnetic head 4.

On the other hand, at the time of reproduction, the reproduction signal S _RF output from the magnetic head 6 is applied to the equalizer circuit 9 via the amplification circuit 8, and the frequency characteristic is corrected, and then to the decoding circuit 10. Grant.

The reproduction signal S _RF is applied to the clock signal generation circuit 12, whereby the clock signal S _CK is generated based on the reproduction signal S _RF .

The decoding circuit 10 detects the signal level of the reproduction signal S _RF based on a predetermined threshold value at the timing of the clock signal S _CK , thereby obtaining reproduction data D _PB , The digitalized video signal (hereinafter referred to as digital video signal) is decoded.

By the way, in the magnetic recording / reproduction system using this kind of magnetic tape, fluctuations in the signal level of the reproduction signal S _RF cannot be avoided due to the traveling system of the magnetic tape, the deformation of the magnetic tape itself, and the like.

Thus, for example, by using an automatic gain control circuit varying the threshold value of the decoding circuit 10 in accordance with the signal level of the corrected signal level of the reproduced signal (S _RF), or the reproduced signal (S _RF), the reproduction data (D _It is necessary to prevent the bit error of _PB ) in advance.

However, because of the way they relate to the signal level of the reproduced signal (S _RF),, there is a fear that bit error occurs, such as when the noise in the reproduced signal (S _RF) incorporation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and proposes a magnetic recording and reproducing apparatus which can effectively avoid bit errors by correcting a signal level of a reproduction signal to a predetermined level even when noise is mixed in the reproduction signal. .

k)가 소정값 D_REF1와 D_REF2사이에 들어갈 때, 재생 신호(S_RF)의 신호 레벨을 검출하는 신호 레벨 검출 수단(70,71,72)과, 상기 신호 레벨 검출 수단(70,71,72)의 검출 결과에 의하여, 재생 신호(S_RF)의 신호 레벨을 보정하는 신호 레벨 보정 수단(31, 73)을 갖추도록 한다.In order to solve this problem, in the present invention, by using a partial response method, a predetermined signal (D _REC ) is recorded on the magnetic recording medium 5, and at the same time, a reproduction signal obtained from the magnetic recording medium 5 ( In the magnetic recording and reproducing apparatus 20 in which the S _RF ) is decoded by the Viterbi decoding circuits 40 and 41, the decode output of the Viterbi decoding circuits 40 and 41 ensures that the decode value corresponding to the reproduction signal level H is high. Data (

signal level detecting means 70, 71, 72 for detecting a signal level of a reproduction signal S _RF when k) falls between a predetermined value D _REF1 and D _REF2 , and the signal level detecting means 70, 71, According to the detection result of 72, signal level correction means 31, 73 for correcting the signal level of the reproduction signal S _RF is provided.

k)가 소정값 D_REF1과 D_REF2사이에 들어 갈 때, 재생 신호(S_RF)의 신호 레벨을 검출하도록 하면, 재생 신호(S_RF)에 노이즈가 혼입되어 있는 경우에서도, 해당 노이즈의 영향을 회피하여 재생 신호(S_RF)의 신호 레벨을 검출할 수 있다.When the decode output corresponds to the H of the reproduction signal, certain data (

in k) is a predetermined value D _REF1 and D presented when the between _REF2, when to detect a signal level of the reproduced signal (S _RF), if a noise is mixed in the reproduced signal (S _RF), the influence of the noise By avoiding this, the signal level of the reproduction signal S _RF can be detected.

Therefore, by correcting the signal level of the reproduction signal S _RF according to the detection result, the signal level of the reproduction signal S _RF can be kept at a predetermined level, and the bit error can be reduced.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment]

In FIG. 1, in which the corresponding parts in FIG. 19 are denoted by the same reference numerals, 20 denotes a video tape recorder as a whole, and the analog digital conversion circuit 22 is adapted to operate with a clock signal S _CK four times the subcarrier signal. and a video signal (S _V).

As a result, in the analog digital conversion circuit 22, an 8-bit digital video signal D _v is obtained, and the data is compressed by the data compression circuit 24, so that the data D of about 25 [MBPS] is obtained. _R ).

On the other hand, the error correction circuit (ECC) 26 receives the data-compressed digital video signal D _{R together} with the digital signal-processed audio signal D _A to perform surfing, code addition for error correction, and the like. As a result, about 30 [MBPS] of recording data D _REC (FIG. 2a) is outputted as shown in FIG.

(1-1) precode circuit

On the other hand, as shown in FIG. 3, the precode circuit 28 receives the write data D _REC from the exclusive OR circuit 28a, and operates the output data of the exclusive OR circuit 28a at the write clock. It is to return to the input terminal of the exclusive OR circuit 28a via the two-stage delay circuits 28b and 28c.

As a result, the precode circuit 28 performs the following equation with respect to the recording data D _REC .

A sequential arithmetic process expressed by < RTI ID = 0.0 > is executed, and the recorded data D _REC is converted into _precoded data D _PR (FIG. 2b) < / RTI >

MOD 2 here represents the surplus of two.

That is, as shown in FIG. 4, when recording and reproducing a signal on a magnetic tape, an electromagnetic conversion system such as a magnetic head has a differential characteristic. Therefore, the magnetization of the magnetic tape is increased when the frequency is increased while the CN ratio is lowered at the lower frequency. The CN ratio decreases due to the characteristics.

Therefore, in the magnetic recording and reproducing system, when recording and reproducing a digital video signal, there is a characteristic that the frequency band at which a good CN ratio is obtained is narrow.

For this reason, in the case of recording a digital video signal, a recording method is selected in which the spectrum of the signal is concentrated around the maximal CN ratio, thereby effectively avoiding a decrease in the CN ratio of the reproduced signal, thereby making the digital video signal more efficient. You need to play well to record.

Therefore, in the present embodiment, the digital video signal is recorded and reproduced using the class IV partial response method.

)에 근사하여 표현할 수 있다.That is, in the magnetic recording reproduction, since the CN ratio is lowered at the lower and higher frequencies, the frequency characteristics are as follows in the class IV partial response (1-D ² ) represented by the delay operator D as shown in FIG. Frequency characteristic H (

Can be approximated to

₀)는 지연 오퍼레이터(D)로 나타내는 지연 시간(T)에 대하여, 다음식For this reason, each frequency at which the response is

₀ ) is the following equation for the delay time T represented by the delay operator D.

There is a relationship.

Therefore, by selecting the delay amount indicated by the delay operator D to a predetermined value, it is possible to concentrate the spectrum of the signal around the maximum CN ratio.

On the other hand, the transfer function of the whole regeneration system is

In this case, the transfer function can be set to 1 as a whole of the recording / reproduction system for the arithmetic processing of the pre-code circuit 28, and the digital video signal can be efficiently recorded and reproduced by effectively utilizing the frequency characteristics of the magnetic recording / reproduction system. have.

In this way, as shown in FIG. 6, the pre code circuit 28 divides the pre code data D _PR for each predetermined block and outputs it to the addition circuit 29. FIG.

Addition circuit 29 is the pre-code data (D _PR) on to add a predetermined data (D _P) before and after each block, and adds the post-amble and data of the preamble to the pre-code data (D _PR) In this way It is.

Here, the pre-code data D _PR which is continuous of 0.1 is written by the recording amplifier 3 into a recording signal D _R having a value of -1, 1, for example, and recorded on the tape.

On the other hand, the magnetic heads 4A and 4B are arranged on the rotating drum (not shown) at intervals of 180 degrees, thereby preloading the precode data D _PR with the postamble and preamble added thereto. In this case, the recording track is recorded in units of one block.

₀)로 되도록 선정되어 있다.For this reason, in the preamble, a reference signal of frequency 15 [MHz] of the recording clock 1/2 is recorded, and the frequency of the reference signal satisfies the expression (2) (

₀ ).

Therefore, in the present embodiment, a clock signal is formed on the basis of a reference signal having a frequency of 15 [MHz] obtained from the preamble, and the reproduction signal S _RF is processed by the clock signal.

(1-2) Regenerator

On the other hand, the magnetic heads 6a and 6b use the amplification circuit 8 and the equalizer circuit (A) for the reproduction signal S _RF (Fig. 2C) of the precode data D _PR inserted in the preamble and postamble data. 9) and the variable gain amplifier circuit 31 to the arithmetic processing circuit 32.

As shown in FIG. 7, the arithmetic processing circuit 32 is composed of an addition circuit 34 and a delay circuit 35, thereby executing arithmetic processing of (1 + D) on the reproduction signal S _RF . do.

On the other hand, since the electron conversion system has a differential characteristic, the reproduction signal S _RF is represented as (1-D) using the delay operator D, and is represented by the frequency characteristic as shown by the broken line in FIG. .

Therefore, during reproduction, the correction of the equation (3) is performed as a whole on the precode data D _PR at the time of recording, and the digital video signal can be efficiently recorded and reproduced by effectively utilizing the frequency characteristics of the magnetic recording reproduction system. have.

In this way, through the arithmetic processing circuit 32, the output signal S _F (FIG. 2d) whose amplitude changes according to the logic level of the recording data D _REC can be obtained.

In contrast, the analog digital conversion circuit 37 converts the signal level of the output signal S _F , which is a reproduction clock obtained from the reproduction signal S _RF , into a digital value, and converts the resulting input data y _k into a selection circuit. Output to (39).

Selection circuit 39 switches the sequential contact points in synchronism with the input data (y _k), and by dividing the input data (y _k) In this way a data D _YO and D _YE of the even sequence and the odd number sequence, the Viterbi decoding Output to circuits 40 and 41.

(1-3) Viterbi decoding circuit

As shown in Figs. 8 and 9, the calculation processing of (1-D ² ) on the reproduction signal S _RF is performed by successive recording signals of values b _n , b _{n + 1} , ... This means that D _R ) is delayed by two clock cycles, so that if the input data y _k is separated for each of the even and the odd series of the recording signal, it is applied to the recording signal (D _R ) of the even and the odd series, respectively. The input data y _k which has performed the arithmetic processing of (1-D) can be obtained.

On the other hand, in the magnetic recording and reproducing system, noise is mixed in the electronic conversion system composed of the magnetic heads 4A, 4B, 6A, and 6B and the magnetic tape 5, so that the recording signal D _R as shown in FIG. and a calculation processing circuit 45 of the treating (1-D ^2), the noise on the output signal (S _F) of the arithmetic processing circuit 45 (S _N) for adding the adding circuit 46 to equivalently express the Can be.

Therefore, if the output signal S _F is separated for each of the even series and the odd series, as shown in FIG. 11, the arithmetic processing circuit 47 of (1-D) with respect to the recording signal D _R , and the arithmetic processing. to the addition circuit 48 which adds the noise _(N S) to the output signal (S _F) of the circuit 47 it can be represented equivalently.

When in this by decoding the recording signal (D _R) y _k data inputs by dividing each solid line and odd line of the correlation of the write data signal input to the _{D R y k, y k +} 1, ... ( By using 1-D), by detecting the recording signal D _R before the noise is mixed, it is possible to reduce the bit error and decode the reproduction data D _PB .

By virtue of this premise, the Viterbi decoding technique is applied using the Viterbi decoding circuits 41 and 40 to which the algorithm of FURGUSON'S ALGOLITHM is applied, as shown in FIG. 12 in this embodiment. Decode the input data y _k , y _{k + 1} , ...

In other words, when the arithmetic processing of (1-D ² ) is performed on the recording signal D _R in the reproducing process, the recording signals of values 1 and -1 are obtained as data taking the values of 2, 0 and -2 on the reproduction side. Therefore, in the output signal S _R (Fig. 13a) where noise is mixed as shown in Fig. 13, the amplitude value fluctuates around the values 2 and -2, and as shown in the signal P1, the pulse Mold noise is mixed.

As a result, in the Viterbi decoding circuits 41 and 40, the input data y _k , y _{k + 1} ... (Fig. 13b) of the values 1.8, 1.2, -1.7, 0, 0.8, ... are sequentially, for example. Is input, and the corresponding input data y _k , y _{k + 1} ... are output to the sequential addition circuits 50 and 51.

)를 저장하도록 된 메모리 수단(57)과 스위치 수단(58)을 가지고, 비교 회로(53)에서 값 1 및 -1의 데이타(D₃)가 출력되면 스위치 수단(58)을 닫음으로써, 가산 회로 (51)에서 출력되는 데이타를 취하여 확실한 데이타(

)를 갱신하도록 되어 있다.The latch circuit 54 stores reliable data of the data D1 (i.e., corresponding to the input data y _k ) of the decoding result output from the comparing circuit 55 (

). The addition circuit has a memory means 57 and a switch means 58, which are configured to store _c ), and closes the switch means 58 when the data D ₃ having values 1 and -1 are output from the comparison circuit 53, Take the data output from (51)

) Is to be updated.

는 트렐리스 선도상의 각각의 출발점에서의 거리의 차이고, 이 때문에, 이 경우 확실한 데이타(

)의 초기 값으로서는 값 0의 데이타가 저장되어 있다.here,

Is the difference between the distances at each starting point on the trellis plot, and in this case

As an initial value of), data having a value of 0 is stored.

(1클럭 주기전의 입력 데이타 y_k에 대응한다)와, 입력 데이타 y_k+1의 감산 데이타(D₂)를 비교 회로(53)에 출력하도록 되어 있다.On the other hand, the addition circuit 50 stores reliable data stored in the latch circuit 54.

(Corresponding to the input data y _k before one clock cycle) and the subtracted data D ₂ of the input data y _{k + 1} are output to the comparison circuit 53.

1의 임계 레벨로, 값 1, 0, -1의 데이타 D₃(이하 예측 입력치라 한다)로 변환하고, 해당 예측 입력치(D₃)를 가산 회로(51)로 제공한다.The comparison circuit 53 values the subtraction data D ₂ .

At a threshold level of 1, the data 1 is converted into data D ₃ (hereinafter, referred to as a predictive input value) having a value of 1, 0, -1, and the predicted input value D _{3 is} provided to the adder circuit 51.

) 및 입력 데이타 y_k+1에 대하여, 다음식That is, reliable data (

) And input data y _{k + 1} ,

When the relation is satisfied, the predictive input value D ₃ is set to the value 1, whereby the addition circuit 51 gives the following equation.

The data *** (k + 1) expressed by " " is outputted, and the reliable data *** k stored in the memory means 51 is updated with the data *** (k + 1).

On this, the following formula

)를, 다음식When the relation is established, the predictive input value D ₃ is set to the value -1, whereby the reliable data stored in the memory means 51 (

),

Update to the reliable data *** (k + 1).

Also,

)를 다음식When the relationship is established, the predictive input value (D ₃ ) is set to the value 0, and solid data (

)

(k+1)로 갱신한다.Reliable data expressed in

Update to (k + 1).

)에 대하여 입력 데이타(y_k+1)값이 값 1이상 변동하면(제14a도), 그 변동 방향과 역방향으로 예측 입력치(D₃)를 값 -1 또는 1로 설정하고, 입력 데이타(y_k+1)의 값에서 값 1만큼 0에 가까운 값을 새로운 확실한 데이타

(k+1)로 갱신하는 것을 의미한다(제14b도).This is shown in Figure 14, with the

), If the value of the input data y _{k + 1} fluctuates by more than one value (Fig. 14A), the predictive input value D ₃ is set to the value -1 or 1 in the opposite direction to the change direction, and the input data ( new data with a value close to 0 from the value of y _{k + 1} )

It means updating to (k + 1) (FIG. 14b).

(k+1)로 갱신시키는 것에 대하여, 사선으로 나타내는 영역 이상으로 변화하지 않는 경우는 값 0의 예측 입력치(D₃)가 출력되고, 확실한 데이타

(k+1)가 그대로 유지된다.Therefore, when the value of the input data y _{k + 1} changes significantly beyond the area indicated by the oblique line, the predicted input value D ₃ of the value 1 or the value −1 is obtained, and the corresponding input data y _{k + 1} is obtained. Data according to value

In the case of updating to (k + 1), if it does not change beyond the area indicated by the diagonal line, the predicted input value D ₃ of the value 0 is output, and the reliable data

(k + 1) remains the same.

As a result, as shown in FIG. 15, when the predicted input value D ₃ of the value +1 is obtained, the input data y _{k + 1} value is received, and the recording signal D _R before at least one block period is received. ) Can be judged to be largely prized toward the positive side.

Therefore, even when large noise is mixed at the timing of the input data y _{k + 1} , it can be seen that the value of the recording signal exhibits a transition other than the transition maintained at the value -1 to the value 1 and the transition maintained at the value -1. .

Conversely, as shown in FIG. 16, when the predicted input value D ₃ of the value -1 is obtained, the input data y _{k + 1} value is prized, and the recording signal value at least one block period before is negative ( It can be judged that the stock was largely delivered to i).

Therefore, even when large noise is mixed in the timing of the input data y _{k + 1} , it can be seen that the recording signal values show a change other than the transition held by the value 1 to the value −1 and the transition held by the value 1.

On the other hand, as shown in FIG. 17, when the predicted input value D ₃ of the value 0 is obtained (FIG. 18a), it means that the change of the input data y _{k + 1} is small, and large noise is mixed. Even in the case, it can be seen that the recording signal value represents a change other than the transition from the value -1 to the value 1 and the transition from the value 1 to the value -1.

Therefore, as shown in FIG. 18, when the predicted input value D ₃ of the value 1 and the value 0 is obtained continuously, the value of the recording signal D _R is received from the value 1 to the value −1, and then the value 1 is increased. It can be known whether the continuous transition or the value 1 is a continuous transition.

On the other hand, it continues to a value of -1 when the predicted input value (D ₃₎ is obtained, it is possible to know where the transition from the granular to the value -1 to the value 1, and represents the change in the non-shift is maintained at the value -1 The value 1 is determined to be a continuous transition after the continuous value before 2 clock cycles is received from the value 1 to the value -1.

Similarly, the time to continue the prediction input value (D ₃₎ of value -1 1 prediction input value (D ₃₎ is obtained when, where a value of -1 prediction input value (D ₃₎ that is obtained as in the recording signal ( It can be seen that the value of D _R ) has risen from the value −1 to the value 1.

In this way, it is possible to determine the transition of the recording signal D _R with respect to the continuous predictive input value D ₃ , thereby demodulating the recording data D _REC .

k)는, (4) 내지 (9)식에 나타나듯이, 입력 데이타(y_k)가 값 1이상 변화했을 때, 입력 데이타(y_k)의 값에 따라 갱신되므로, 그 값의 절대값이 크게 되면 큰 만큼, 예측 입력치(D₃)로 판단되는 기록 신호(D_R)의 천이가 보다 확실하게 판단될 수 있다.At this point

k) is (4) to (9) as shown in formula, when the input data (y _k) has been greater than the value 1 changes, are updated according to the value of the input data (y _k), the absolute value of that value significantly As large as possible, the transition of the recording signal D _R , which is determined as the predictive input value D ₃ , can be determined more reliably.

k)를 갱신하고, 갱신된 확실한 데이타(

k)에 의하여, 입력 데이타(y_k)값의 천이를 검출한다.According to this detection principle, the Viterbi decoding circuits 40 and 41 sequentially store reliable data (

k) and update the updated data (

k) detects a transition of the input data y _k value.

k)에 대하여 값 1.8의 입력 데이타(y_k+1)가 입력되면, 값 -1.8의 감산 데이타가 얻어짐으로써, 값 -1의 예측 입력치(D₃)가 출력되고(제13b도), 확실한 데이타(

k)가 값 0.8로 갱신된다(제13d도).I.e., a solid data of value 0

When input data y _{k + 1} having a value of 1.8 is input to k), subtractive data having a value of -1.8 is obtained, so that a predictive input value D ₃ having a value of -1 is output (Fig. 13B), Solid data (

k) is updated to the value 0.8 (Fig. 13D).

k)가 래치 회로(54)에 유지된다.Subsequently, when input data y _{k + 1} having a value of 1.2 is input, subtracted data having a value of -0.4 is obtained, and a predictive input value D ₃ having a value of 0 is output, in which case the switch means 58 is turned off. State, so you get a solid data value of 0.8

k is held in the latch circuit 54.

k)가 값 -0.7 로 갱신된다.When On the other hand, continues to a value of -1.7 input data (y _{k + 1)} is input, a subtraction of the data value 2.5 is obtained, and a predicted input value (D ₃₎ of the first output value, certain data (

k) is updated to the value -0.7.

In this way, between the write signal (D _R) to the input data of the input data value 1.8 of the value of 1.2 in _{(y k + 1) (y} k + 1) is the value 1, to detect that the series of value 1 Can be.

In this way, the predictive input value D ₃ can detect the progressive recording signal D _R.

k)가 값 0 이상일 때, 값 1의 복호 결과의 데이타(D₁)를 출력하는 것에 대해, 확실한 데이타(

k)가 부(負) 값을 취할 때, 값 -1의 복호 결과의 데이타(D₁)를 출력함으로써, 확실한 데이타(

k)를 기준으로 하여 기록 신호(D_R)를 검출한다.The comparison circuit 55 is a reliable data (

When k) is greater than or equal to the value 0, the data (reliable) for outputting the data D ₁ of the decoding result of the value 1

When k) takes a negative value, by outputting the data D ₁ of the decoding result of the value -1, the reliable data (

The recording signal D _R is detected on the basis of k).

The data memory circuit 60 is connected in series with a 20-step shift register circuit, whereby the data D ₁ of the decoding result is once stored.

The data memory circuit 60 converts the data D ₁ of the decoding result of the logic levels 1 and -1 into the data of the logic levels 1 and 0, respectively, and then outputs the control signal Sc output from the control circuit 61. To reverse the logic level.

The control circuit 61 detects the transition (figure 13d) of the recording signal based on the multiplication result of the data D ₁ of the decoding result output from the multiplication circuit 62 and the predictive input value D ₃ . The control signal Sc is output in accordance with the detection result.

This inverts the data D ₁ of the decoding result as necessary, and decodes the pre code data.

The data memory circuit 60 connects an exclusive OR circuit to the output terminal, thereby arithmetic processing of the decoded precode data 1-D, and decodes the reproduction data D _PB .

In this way, the Viterbi decoding circuits 41 and 40 decode the input data by using the relationship between the data before and after (1-D), so that the case of decoding the input data having a low CN ratio containing noise Even in the case where the input data is simply decoded on the basis of a predetermined threshold value, data having fewer bit errors can be decoded rapidly.

Therefore, the present invention can be reliably reproduced by applying to a digital video tape recorder.

(1-4) Control of the Variable Gain Amplifying Circuit 31

k) 및 예측 입력치(D₃)를 기준으로 하여 입력 데이타(y_k)를 복호함으로써 노이즈 등의 영향을 유효하게 회피하여 비트 오류가 적은 데이터를 복호할 수 있다.However, as described above, in the Viterbi decoding circuits 41 and 40, reliable data (

By decoding the input data y _k on the basis of k) and the predicted input value D ₃ , it is possible to effectively avoid the influence of noise and the like and to decode the data with less bit error.

k)가 소정값 이상, 동시에 소정값 이하일 때만 재생 신호(S_RF)의 신호 레벨을 검출하면, 재생 신호(S_RF)에 노이즈가 혼입하고 있는 경우에서도, 노이즈의 영향을 저감하여 신호 레벨을 검출할 수 있다.Therefore, certain data indicating the certainty of the data D ₁ (

k) is a predetermined value or more, at the same time a predetermined value or less only when detecting the signal level of the reproduced signal (S _RF), even if the noise is mixed in the reproduced signal (S _RF), to reduce the influence of the noise detection signal level can do.

k가 거기에 영향받아 통상 범위를 초과하는 것을 방지하기 위함이다.Here, if the input data y _k is very large due to noise,

This is to prevent k from being affected by it and exceeding the normal range.

If the gain of the variable gain amplifier circuit 31 is controlled based on the detection result, it is possible to effectively avoid the influence of noise and to control the gain of the variable gain amplifier circuit 31.

Therefore, even when noise is mixed in the reproduced signal (S _RF) and to correct the signal level of the reproduced signal (S _RF) to signal a desired level, thereby reducing bit error in accordance with the variation of the signal level have.

k)를 가한다.For this reason, in the present embodiment, in the Viterbi decoding circuits 40 and 41, the comparator circuit 70 alternately reliably replaces the reliable data (in synchronization with the input data y _k ).

k) is added.

k)의 값을 비교하도록 되고, 이것에 의하여 확실한 데이타(

k)가 소정 범위내일 때, 스위치 회로(71)를 온 상태로 전환된다.The comparison circuit 70 provides reliable data when the decoded values of the predetermined reference data D _REF1 and D _REF2 and the Viterbi decoding circuits 40 and 41 are decoded values corresponding to the H level of the reproduction signal (1 in this case).

the value of k) is compared, thereby ensuring that

When k) is within a predetermined range, the switch circuit 71 is turned on.

k)에 대응한 입력 데이타(y_k)를 아날로그 신호로 변환하도록 되어 있다.On the other hand, the digital analog conversion circuit 72 has a shift register circuit at the input stage, thereby delaying the input data y _k by a predetermined clock period, thereby ensuring reliable data (which is input to the comparison circuit 70).

The input data y _k corresponding to _k ) is converted into an analog signal.

k)가 기준 데이타 D_REF1과 D_REF2의 범위로 들어갈 때, 그 데이타(

k)에 대응하는 입력 데이타(y_k)의 아날로그 신호를 샘플 홀드 콘덴서(73)에 가하도록 되어 있다.On the other hand, the switch circuit 71 receives the output signal of the digital analog conversion circuit 72 as a contact point, whereby reliable data (

When k) falls within the range of the reference data D _REF1 and D _REF2 , the data (

The analog signal of the input data y _k corresponding to k) is applied to the sample hold capacitor 73.

k)가 기준 데이타 D_REF1과 D_REF2사이에 들어갈 때, 재생 신호(S_RF)의 신호 레벨에 비례한 전압이 홀드되도록 되고, 이것에 의하여 재생 신호(S_RF)에 노이즈가 혼입하고 있는 경우에서도, 그 영향을 저감하여 신호 레벨을 검출할 수 있다.In this way, the sample hold capacitor 73 provides reliable data (

When k) enters between the reference data D _REF1 and D _REF2 , a voltage proportional to the signal level of the reproduction signal S _RF is held, so that even when noise is mixed in the reproduction signal S _RF . Therefore, the signal level can be detected by reducing the influence.

The variable gain amplifier circuit 31 is configured to vary the gain in accordance with the hold voltage of the sample hold capacitor 73.

As a result, the variable gain amplifier circuit 31, together with the arithmetic processing circuit 32, the analog digital conversion circuit 37, the digital analog conversion circuit 72, the switch circuit 71, and the sample hold capacitor 73, is provided with AGC. An automatic gain control loop is formed, whereby the signal level of the reproduction signal S _RF is maintained at a predetermined signal level.

k)가 기준 데이타 D_REF1와 D_REF2사이로 들어갈 때, 재생 신호(S_RF)의 신호 레벨을 검출하고, 해당 검출 결과에 따라 재생 신호(S_RF)의 신호 레벨을 보정할 수 있고, 이것에 의하여 노이즈 등의 영향을 유효하게 회피하여 비트 오류를 저감할 수 있다.In this way, when the decode value of the Viterbi decoder is 1,

When k) go between the reference data D _REF1 and D _REF2, detecting the signal level of the reproduced signal (S _RF), and it is possible to correct the signal level of the reproduced signal (S _RF) in accordance with the detection result, by this By effectively avoiding the influence of noise and the like, the bit error can be reduced.

k)는 입력 데이타(y_k) 값에 따라 순차 갱신되므로, 이와같이 확실한 데이타(

k)를 기준으로 하여 가변 이득 증폭 회로(31)의 이득을 제어하면, 재생 신호(S_RF)의 신호 레벨이 순간적으로 변동하여도, 해당 변동에 추종하여 가변 이득 증폭 회로(31)의 이득을 제어할 수 있다.Also, certain data (

k) is updated sequentially according to the value of the input data (y _k ).

If the gain of the variable gain amplifier circuit 31 is controlled based on k), even if the signal level of the reproduction signal S _RF changes instantaneously, the gain of the variable gain amplifier circuit 31 is adjusted in accordance with the variation. Can be controlled.

Therefore, the characteristics of the Viterbi decoding circuits 40 and 41 which decode the data with few bit errors can be effectively utilized by using the correlation between the data before and after, and the bit error of the end and the reproduction data D _PB can be effectively used. Can be reduced.

k)가 기준 데이타 D_REF1과 D_REF2사이에 들어갈 때, 재생 신호(S_RF)의 신호 레벨을 검출하는 신호 레벨 검출 수단을 구성하는데 대해, 샘플 홀드 콘덴서(73) 및 가변 이득 증폭 회로(31)는 그 검출 결과에 따라 재생 신호(S_RF)의 신호 레벨을 보정하는 신호 레벨 보정 수단을 구성한다.For this reason, in the present embodiment, the comparison circuit 70, the switch circuit 71, and the digital analog conversion circuit 72 provide reliable data (

When k) enters between the reference data D _REF1 and D _REF2 , the sample hold capacitor 73 and the variable gain amplifying circuit 31 are provided for configuring the signal level detecting means for detecting the signal level of the reproduction signal S _RF . Configures signal level correction means for correcting the signal level of the reproduction signal S _RF according to the detection result.

(1-5) Processing of Reproduction Data D _PBO and D _PBE

The selection circuit 80 receives the reproduction data D _PBE and D _PBO output from the Viterbi decoding circuits 40 and 41, and switches the sequential contacts to retrieve data divided into even series and odd series. It is supposed to return to an array.

On the other hand, the error detection correction circuit 81 receives the reproduction data D _PBO (Fig. 2e) output from the selection circuit 80, detects a bit error and corrects the bit error, and then the audio signal S _APB. ) And video data.

The data decompression circuit 82 receives the data of the video signal separated by the error detection and correction circuit 81, and decompresses the data in reverse with the data compression circuit 24.

In this way, the video signal S _VPB can be obtained via the digital analog conversion circuit 83.

(1-6) Operation of the Example

In the above configuration, the video signal Sv is converted into the digital video signal Dv by the analog digital conversion circuit 22 and then compressed by the data compression circuit 24 into about 25 [MBPS] of data D _R. .

The compressed data D _R is processed by the error correction circuit 26 together with the audio signal D _A , such as surfing, adding a code for error correction, and the like to record data D _REC of 30 [MBPS]. Is converted.

The recording data D _REC is subjected to the arithmetic processing of formula (2) in the precode circuit 28, converted into the precode data D _PR , divided into blocks, and recorded on the magnetic tape 5 at the same time. A preamble is recorded which records a reference signal of frequency 15 [MHz].

On the other hand, the reproduction signal S _RF output from the magnetic heads 6A and 6B passes through the equalizer circuit 9, the variable gain amplifier circuit 31, and the arithmetic processing circuit 32, and the analog digital conversion circuit ( 37), thereby converting the signal level of the reproduction signal S _{RF into} input data y _k in a period of winning and falling.

The input data y _k is divided into even series and odd series, and then applied to the Viterbi decoding circuits 40 and 41, whereby the input data y _k is decoded into the reproduction data D _PBO (D _PBE ). do.

k) 중에서 디코더 출력이 1 에 대한 데이타가 비교 회로(70)에서 소정의 기준 데이타 D_REF1및 D_REF2와 비교되고, 확실한 데이타(

k)가 해당 기준 데이타 D_REF1과 D_REF2사이에 들어갈 때, 아날로그 신호로 변환된 입력 데이타(y_k)가 샘플 홀드 콘덴서(73)에 출력된다.At this time, the reliable data updated according to the input data (y _k )

k) The data for decoder output 1 is compared with predetermined reference data D _REF1 and D _REF2 in comparison circuit 70, and the reliable data (

When k) enters between the corresponding reference data D _REF1 and D _REF2 , the input data y _k converted into an analog signal is output to the sample hold capacitor 73.

k 가 비터비 디코드 출력이 1에 대응하고, 동시에 기준 데이타 D_REF1와 D_REF2사이에 들어갈 때만, 재생 신호(S_RF)의 신호 레벨이 검출되도록 되며, 샘플 홀드 콘덴서(73)의 홀드 전압에서 가변 이득 증폭 회로(31)의 이득이 제어되는 것에 의하여, 해당 가변 이득 증폭 회로(31)에서 출력되는 재생 신호(S_RF)의 신호 레벨이 소정 레벨로 유지된다.Reliable data by this

Only when k is the Viterbi decode output corresponds to 1 and at the same time falls between the reference data D _REF1 and D _REF2 , the signal level of the reproduction signal S _RF is detected so that it is variable in the hold voltage of the sample hold capacitor 73. By controlling the gain of the gain amplifier circuit 31, the signal level of the reproduction signal S _RF output from the variable gain amplifier circuit 31 is maintained at a predetermined level.

In this way, even when noise is mixed in the reproduction signal S _RF , the influence of the noise can be effectively avoided, and the signal level of the reproduction signal S _RF can be maintained at a predetermined level, thereby reducing the bit error. One reproduction data D _PBO (D _PBE ) can be obtained.

The reproduction data D _PBO and D _PBE return to the original array before being divided into even and odd series in the selection circuit 80, and then the error detection and correction circuit 81, the data extension circuit 82, and the digital analog. Via the conversion circuit 83, it is converted into the video signal S _VPB in reverse to the time of recording.

(1-7) Effect of Example

k)가 비터비 디코드 출력 1에 대응하고, 기준 데이타 D_REF1과 D_REF2사이에 들어갈 때만, 재생 신호(S_RF)의 신호 레벨을 검출하고, 그 검출 결과에 의거하여 재생 신호(S_RF)의 신호 레벨을 보정함으로써, 재생 신호(59)에 노이즈가 혼입하여 있는 경우에서도, 노이즈의 영향을 유효하게 회피하여 재생 신호(S_RF)의 신호 레벨을 소정 레벨로 유지할 수 있고, 이렇게 하여 재생 데이타(D_PB)의 비트 오류를 저감할 수 있다.According to the above configuration, reliable data (

k) corresponds to a Viterbi decoded output 1, and the reference data D only go between _REF1 and D _REF2, the reproduction signal (detection signal level of the S _RF), and the playback signal (S _RF) in accordance with the detection result of the By correcting the signal level, even when noise is mixed in the reproduction signal 59, the influence of the noise can be effectively avoided and the signal level of the reproduction signal S _RF can be maintained at a predetermined level. The bit error of D _PB ) can be reduced.

(2) another embodiment

k가 정 또는 부의 한쪽으로 D_REF1및 D_REF2에 들어간 경우에만 그 데이타를 이용하고 있지만, 이 대신 정 및 부의 양쪽에서

k 가 어떤 범위 내에 들어가는 경우를 각각 이용하여 그것으로부터 얻어지는 각각의 에러 전압을 귀환하여 가변 이득 증폭 회로를 제어하여도 좋다.In the above embodiment

The data is only available if k enters D _REF1 and D _REF2 on either side of the positive or negative, but instead the positive and negative

The variable gain amplifier circuit may be controlled by returning each error voltage obtained therefrom using each case where k falls within a certain range.

In the above-described embodiment, the case where the signal level of the reproduction signal S _RF is corrected by controlling the variable gain amplifier circuit has been described. However, the present invention is not limited thereto, and for example, the analog digital conversion circuit 37 is used. The comparison reference voltage may be varied, and the signal level of the reproduction signal may be corrected so that the signal level after the analog digital conversion becomes a predetermined signal level.

In the above embodiment, the case where the digital video signal is recorded and reproduced by applying the class IV partial response method is described. However, the present invention is not limited thereto, and the like is applied when recording and reproducing by applying another Viterbi decoder. Also widely applicable.

In the above embodiment, the case of recording and reproducing a digital video signal has been described, but the present invention is not limited to this, and can be widely applied to the case of recording and reproducing various kinds of digital signals.

Incidentally, in the above-described embodiment, the case where data is recorded and reproduced on the magnetic tape has been described, but the present invention is not limited to the magnetic tape and can be widely applied to a magnetic recording and reproducing apparatus using a magnetic recording medium.

As described above, according to the present invention, by detecting the signal level of the reproduction signal on the basis of reliable data of the Viterbi decoding circuit, even if noise is mixed in the reproduction signal, the effect of the noise is effectively avoided and the reproduction is performed. The signal level of the signal can be detected, and the reproduction signal can be corrected to a desired signal level by correcting the signal level of the reproduction signal based on the detection result.

In this way, the effect of noise can be effectively avoided, and the signal level of the reproduction signal is kept at a predetermined level, whereby a magnetic recording and reproducing apparatus can be obtained in which the bit error is reduced.

Claims (1)

An apparatus for recording and reproducing a data signal, comprising: means for precoding the digital data signal in a partial response manner to form a precode data signal; Means for recording the pro code data signal on a magnetic recording medium; Means for reading data recorded on the recording medium to generate a corresponding analog reproduction signal; Means for processing the analog reproduction signal according to a partial response scheme to form a processed data signal; Means for converting the processed data signal into a digital reproduction signal; Signal dividing means for dividing the digital reproduction signal into first and second signal portions; Decoding means for decoding the digital reproduction signal according to a Viterbi algorithm to generate a decoded signal; Detecting means for detecting the level of the reproduction signal only when certain data of the decoding means is equal to or larger than a predetermined value; And signal level correction means for correcting a signal level of the reproduction signal on the basis of the output of the level detection means.

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