JPS63113981A - Digital signal detecting circuit - Google Patents

Abstract

PURPOSE:To always maximize a phase margin by sampling an input signal with an A/D converter once, and controlling the phase of a sampling clock so as to minimize the variance of sampling data. CONSTITUTION:An integrator 18 integrates a reproducing signal 1 from a head. An A/D converter 13 converts the output of the integrator 18 to a digital signal. Sampling is executed by a clock 4 extracted from the signal 1 in the same way at this time. A digital wave equalizer 9 waveform-equalizes the sampled reproducing signal after integrating. The output of the equalizer 9 is accumulated in a memory 14, and an arithmetic processing circuit 15 calculates and processes least square error of the data and outputs a phase control signal 7. On the other hand, a clock extracting circuit 11 extracts a clock 3 from the signal 1, the clock 3 is inputted to a phase control circuit 12, a phase is controlled by the signal 7 and a sampling clock 4 is outputted. By executing the sampling of the converter 13 with the clock 4, the phase margin in the sampling can be sufficiently kept.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic recording/reproducing device for digital signals, and particularly to a digital signal detection circuit used when detecting a digital signal from a reproduced signal.

[Conventional technology]

Over the past few years, devices for recording and reproducing video and audio signals have been using a digital recording method in which the signals are converted into digital signals and then recorded. This is because digital recording can significantly improve image and sound quality compared to analog recording (FM variant: A), and there is no deterioration even after multiple copies, and the reliability of the device itself is also improved. This is because it is possible.

However, digital recording methods require higher density recording than analog recording, and the most important issue is how to faithfully reproduce recorded digital signals. FIG. 7 is a block diagram of a device (such as a digital VTR) that converts such video signals and audio signals into digital signals and records and reproduces them.

The input video signal 30 is first converted into a digital signal by an A/D converter 31. This digital signal is input to a recording processor 32, where the data is rearranged, a correction code, a synchronization signal, etc. are added, and the signal is sent to a modulator 33. The modulator 33 converts the original digital signal into a code (called a channel code) suitable for recording on a tape or the like, and performs parallel-to-serial conversion. Thereafter, the signal is current-amplified by a recording amplifier 34 and then recorded on a tape by a recording head 35. on the other hand,
The signals recorded on the tape are reproduced as minute signals by the reproduction head 3B. The signal obtained here is the reproduction amplifier 37
After amplifying the signal to a level suitable for signal processing, the signal is sent to the digital signal detection circuit 38. The digital signal detection circuit 38 performs waveform equalization on this signal so that digital data (channel-coded digital signal here) can be detected, and then clock extraction and digital data detection are performed. A digital signal is obtained at the output of the demodulator 39 using this digital data and clock. However, since this signal has jitter caused by the tape running system, it is passed through a time base corrector 40 to absorb the jitter and make a reproduced digital signal synchronized with the input video signal or reference signal. This reproduced digital signal is corrected for data errors caused by the recording/reproducing process in the reproduction processor 41, and errors exceeding the correction capability are corrected and rearranged to the original data order. Thereafter, it is converted into an analog playback video signal 43 by a D/A converter 42. In this way, signals recorded on tape can be reproduced. Generally, digital VTRs use NRZ type codes as channel codes. This is shown in Figure 8 (A
) as shown in the same figure (B).
This is because it is a code that associates "o" with "level" and "°L" level, and is suitable for high-density recording because the minimum magnetization reversal interval is long and the detection window width is wide.

The difficulty of self-clocking, which was traditionally considered a drawback, is also a PL.
This problem has been eliminated due to advances in L technology and the use of scrambled NRZ that adds pseudo-random signals.

Normally, a-minute detection is used for recording and reproducing NRZ signals. This is because when the signal shown in Fig. 8 (CB) is recorded, the reproducing head obtains a waveform as shown in Fig. 8 (C).
) After shaping the waveform as shown in (E) of the same figure, the original digital signal is detected from this signal by integrating it as shown in (E).

By overlapping the signals shown in FIG. 6(E) every two clock cycles, an eye pattern as shown in FIG. 6 can be obtained.

Now, a digital signal detection circuit used in a magnetic recording and reproducing device that records and reproduces such a digital signal detects a clock signal from the reproduced signal 1 (the reproduced signal after waveform equalization and integration) as shown in FIG. 9, for example. a clock extraction circuit 11 that extracts the signal 3, and a 1-bit A/D converter 17 that converts the reproduced signal 1 into a digital signal 2 using the sampling clock 4.
and a clock delay 16 that applies a fixed delay to the output clock 3 of the clock extraction circuit 11 in order to ensure sufficient phase margin for the reproduced signal l with respect to the clock. The signal error rate was minimized by adjusting the phase of the clock 3 so that sampling was performed at each point.

[Problem that the invention seeks to solve]

The conventional digital signal detection circuit described above cannot respond to changes in the input signal when the data rate of the input signal changes (for example, when performing high-speed playback or slow-motion playback in a digital VTR that digitally magnetically records and plays video signals). Since the clock has a fixed delay, the signal error rate may deteriorate even though the input signal waveform is sufficiently equalized.Also, although a PLL circuit is generally used as a clock extraction circuit, the voltage If sufficient compensation is not provided for changes and temperature changes, there is a drawback that a change in the amount of time delay of the output clock is induced, which may lead to deterioration of the signal error rate due to the above-mentioned environmental changes.

[Means for solving problems]

The digital signal detection circuit of the present invention includes a clock extraction circuit that extracts a clock from an input signal (a reproduced signal reproduced from a head), an integrator that integrates the input signal, and converts the output of the integrator into an N-bit digital signal. An A/D converter for conversion, a digital waveform equalizer for waveform equalizing the digitized signal into N bits, a memory for temporarily storing the output of the digital waveform equalizer, and a memory for temporarily storing the data stored in the memory. an arithmetic processing circuit that processes the clock and outputs a phase control signal; and a clock output from the clock extraction circuit, the clock whose phase is varied by the phase control signal output from the arithmetic processing circuit, and the clock that is sent to the A/D converter. and a phase control circuit, and uses the MSB of the digital waveform equalizer output as an output signal.

Figure 6 is a diagram showing the eye pattern of the reproduced signal (input signal of the digital signal detection circuit) after waveform equalization. From Figure 0, the point where the phase margin is maximum for a signal that has been sufficiently equalized in waveform. It can be seen that the value converges to two values at (point A).

The present invention focuses on the above point, and converts the input signal to the A of -HN bits.
In this method, sampling is performed using a /D converter, and the phase of the sampling clock is controlled so as to minimize variations in sample data, thereby always maximizing the phase margin.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the digital signal detection circuit of the present invention.

The integrator 18 integrates the reproduction signal 1 reproduced from the head. The A/D converter 13 inputs the output of the integrator 18, and
Convert to bit digital signal. At this time, sampling is performed using the clock 4 which is also extracted from the reproduced signal. The digital waveform equalizer 9 equalizes the waveform of the sampled and integrated reproduction signal. This digital waveform equalizer 1
9 can be configured, for example, by a transversal digital filter. In this example, the coefficients of each tap are fixed or semi-fixed, but a digital automatic equalizer may also be used. The output signal of the digital equalizer 9 exactly matches the value obtained by sampling the eye pattern of FIG. 6 at a clock cycle.

Now, if the relationship between the analog signal and the digital signal is as shown in Figure 4, the MSB of the output of the digital waveform equalizer 19 becomes the digital detection signal itself, and by outputting this, the digital signal is detected. It will be done. on the other hand,
As mentioned above, in order to control the sampling point for the data to be at point A in FIG. The least square error of the sequentially read data is calculated, compared with the previous value, and the process shown in the flowchart of FIG. 2 is performed to output the phase control signal 7.

First, an initial value is set in advance as an initial state, and the amount of delay of the clock is output as the phase control signal 7 (step 21). That is, the least square error of the data in this state is calculated and temporarily stored. This value is now set as EO. Next, step 22 to slightly increase the clock delay amount.
) Calculate the least squares error E1 again (step 23) and compare it with the previous value (step 24). If the value is smaller than the previous value, the clock delay amount is further increased and compared with the previous value (steps 22 to 24); if the value is larger than the previous value, the clock delay amount is decreased this time. (Step 25) Calculate the least squares error Step 26)
Compare with the previous value (step 27). If the value is smaller than the previous value, the clock delay amount is further decreased, the minimum squared error is calculated again, and compared with the previous value (steps 25 to 27). If the value is larger than the previous value, the delay amount is increased again and the above process is repeated. If necessary, the mode of the VTR is determined (whether the current state is the playback mode, etc.) (step 2), and the above trial process is ended.

On the other hand, the clock extraction circuit 11 extracts the clock 3, which is input to the clock phase control circuit 12, which selects the clock with the optimum phase according to the phase control signal 7 mentioned above, and outputs the sampling clock 4. By sampling the A/D converter 13 using this clock 4, a sufficient phase margin in sampling is maintained.

FIG. 3 is a block diagram showing an example of the clock phase control circuit 12.

This clock phase control circuit 12 has a clock phase control circuit 12.
It is composed of OR gates 51 to 57 that sequentially delay the clock 3 and each output of the OR gates 51 to 57 using a phase control signal 7 and a multiplexer 58 that outputs the selected clock as the sampling clock 4. Here, a logic IC is used as the delay element for ease of integration, but it can also be configured using a delay line or the like.

By using the selector, the amount of clock delay can be easily controlled using the phase control signal 7.

Generally, the recording data rate of digital VTR is 60 Mbit/s to 200 Mbit/s per channel.
/s, and it is difficult and unnecessary to calculate all the samples in terms of hardware.Therefore, for the data format shown in Figure 5, for example, it is necessary to write to memory in order to calculate only 16 bits of 5YNC. , if the readout operation is performed at low speed, the arithmetic processing circuit 15 can be configured with one general-purpose signal processor.

〔Effect of the invention〕

As explained above, the present invention obtains a good signal error rate in the high playback mode and slow motion playback mode of a digital VTR by controlling the sampling point of the input signal so that the phase margin is always maximized. This has the effect of ensuring stable operation under changes in temperature and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the digital signal detection circuit of the present invention, FIG. 2 is a flowchart showing processing of the arithmetic processing circuit 15, and FIG. 3 is a clock phase control circuit 1.
FIG. 4 is a diagram showing the relationship between analog signals and digital signals in the A/D converter 13, FIG. 5 is a diagram showing the data format of the digital VTR,
Figure 6 is a diagram showing the eye pattern of the input signal, Figure 7 is a diagram showing the basic configuration of a digital VTR, Figure 8 is a diagram showing the NRZ signal and each waveform in recording and reproduction, and Figure 9 is a digital signal detection circuit. FIG. 2 is a block diagram of a conventional example. l... Reproduction signal, 2... Digital detection signal, 3.
... Clock, 4... Sampling clock, 5.
... A/D output signal, 6... Memory output signal, 7... Phase control signal 11... Clock extraction circuit, 12... Clock phase control circuit, 13...
・A/D converter, 14...Memory, 15・
... Arithmetic processing circuit, 18 ... Integrator, 19.
... Digital waveform stopper, 50-57... OR gate. 58... Multiplexer. Patent Applicant: NEC Co., Ltd. Representative: Susumu Uchihara, Patent Attorney: Figure 2, Figure 4 () is the number of bits; Figure 5, Figure 6 (A) 011010111001000'01
0010111Figure 8

Claims (1)

[Claims] A digital signal detection circuit that detects a digital signal from a reproduced signal of a digital signal magnetic recording/reproducing device, etc., which uses a reproduced signal reproduced from a head as an input signal and extracts a clock from the input signal. An extraction circuit, an integrator that integrates the input signal, and an A/D converter that converts the output of the integrator into an N-bit digital signal.
A D converter, a digital waveform equalizer that equalizes the waveform of the signal digitized into N bits, a memory that temporarily stores the output signal of the waveform digital equalizer, and a memory that processes the data stored in the memory. an arithmetic processing circuit that outputs a phase control signal; and a clock phase control circuit that varies the phase of the clock output from the clock extraction circuit using a phase troll signal output from the arithmetic processing circuit and sends it to an A/D converter. A digital signal detection circuit which has a digital waveform equalizer output MSB as an output signal.