JPH02213278A - Facsimile decoding circuit - Google Patents

Facsimile decoding circuit

Info

Publication number
JPH02213278A
JPH02213278A JP1034036A JP3403689A JPH02213278A JP H02213278 A JPH02213278 A JP H02213278A JP 1034036 A JP1034036 A JP 1034036A JP 3403689 A JP3403689 A JP 3403689A JP H02213278 A JPH02213278 A JP H02213278A
Authority
JP
Japan
Prior art keywords
line
line memory
picture data
data
image data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1034036A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hasegawa
長谷川 広之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1034036A priority Critical patent/JPH02213278A/en
Publication of JPH02213278A publication Critical patent/JPH02213278A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate necessity to read picture data for one line from a line memory when the picture data for one line are wholly blank and to execute two-dimensional decoding at high speed by setting the attribute information of the picture data for one line in the line memory. CONSTITUTION:A line memory circuit 2 is defined as the line memory, to which a referred line is stored, and a line memory circuit 3 is defined as the line memory, to which the picture data for one line after decoding are stored. When the data are decoded, a two dimensional decoding circuit 1 reads a flag F1 of the line memory circuit 2 and confirms the attribute of the picture information. When the attribute of the picture data is not wholly blank for one line, the picture data for the required number of words are read from the line memory circuit 2 as the referred line while decoded data 19 are inputted from a line. When the attribute of the picture data is wholly blank for one line, the picture data are not read from the line memory circuit but the two-dimensional decoding is executed only by inputting a code. Then, a decoded result is successively written to the line memory circuit 3 and when it is finished to write the picture data for one line, the attribute of the picture data is written to a flag F2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はファクシミリ装置の2次元復号化回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a two-dimensional decoding circuit for a facsimile machine.

〔従来の技術〕[Conventional technology]

従来のファクシミリ装置の2次元復号化回路は、受信の
符号データを参照ラインメモリ回路に記憶された1ライ
ン前の符号データを順次読み出し参照して復号化した画
データを出力する。
A two-dimensional decoding circuit of a conventional facsimile machine outputs image data obtained by decoding received coded data by sequentially reading and referring to the coded data of the previous line stored in a reference line memory circuit.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の2次元復号化回路は、2次元の復号化処
理を、1ライン分を記憶した参照ラインメモリ回路から
順次読出した符号データを参照して復号対象の符号デー
タを復号した画データを出力するので、復号化時間が長
くなるという欠点がある。
The above-mentioned conventional two-dimensional decoding circuit performs two-dimensional decoding processing by decoding image data of the coded data to be decoded by referring to coded data sequentially read out from a reference line memory circuit that stores one line. Since it is output, there is a drawback that decoding time becomes long.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のファクシミリ復号化回路は、1ライン分の符号
データとこの符号データの属性情報とを記憶する第1の
ラインメモリと、復号された1ライン分の画データとこ
の画データの属性情報とを記憶する第2のラインメモリ
と、回線から受信し識別した前記属性情報を含む符号デ
ータを書き込んだ前記第1のメモリを参照して2次元の
復号化を行った画データとこの画データの属性情報とを
前記第2のラインメモリに書き込む2次元復号化回路と
を有している。
The facsimile decoding circuit of the present invention includes a first line memory that stores one line of encoded data and attribute information of this encoded data, and a first line memory that stores one line of decoded image data and attribute information of this image data. image data that has been two-dimensionally decoded with reference to the second line memory that stores the image data, and the first memory that has written the encoded data that includes the attribute information received from the line and identified, and the image data of this image data. and a two-dimensional decoding circuit that writes attribute information into the second line memory.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
は本発明の一実施例のブロック図である。
Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

本実施例は、1ライン分の符号データとこの符号データ
の属性情報(フラグFl)とをデータ線11を介して書
込みパルス12及びアドレス信号14に従って記憶する
第1のラインメモリ回路2と、復号された1ライン分の
画データとこの画データの属性情報(フラグF2)とを
データ線15を介して書込パルス16及びアドレス信号
18に従って記憶する第2のラインメモリ回路3と、回
線19から受信し識別したフラグF1を含む符号データ
を書き込んだ第1のラインメモリ回路2から読出しパル
ス13及びアドレス信号14によって読み出したデータ
を参照して復号した画データとこの画データのフラグF
2とをデータ線15を介して書込パルス16及びアドレ
ス信号18によって第2のラインメモリ回路2に記憶さ
せる2次元復号化回路1とを有して構成される。
This embodiment includes a first line memory circuit 2 that stores code data for one line and attribute information (flag Fl) of this code data via a data line 11 in accordance with a write pulse 12 and an address signal 14, and a decoding circuit. A second line memory circuit 3 stores one line of image data and attribute information (flag F2) of this image data via a data line 15 in accordance with a write pulse 16 and an address signal 18; The image data decoded by referring to the data read out by the read pulse 13 and address signal 14 from the first line memory circuit 2 into which code data including the received and identified flag F1 was written and the flag F of this image data.
2 and a two-dimensional decoding circuit 1 for storing data in the second line memory circuit 2 via a data line 15 using a write pulse 16 and an address signal 18.

次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

フラグFl、F2はラインメモリ回路2.3にそれぞれ
記憶された1ライン分の画データの属性を示す。ライン
メモリ回路2を参照ラインが記憶されているラインメモ
リとし、ラインメモリ回路3を、復号化後の1ラインの
画データが記憶されるラインメモリとする。2次元復号
化回路1は復号化を行うとき、ラインメモリ回路2のフ
ラグF1を読み出し、画データの属性を確認する。画デ
ータの属性が1ライン全部白データ(1ライン全白)で
ない場合には、回線から復号データ19を入力しつつ参
照ラインとして必要ワード数の画データをラインメモリ
回路2から読出す0画データの属性が1ライン全白の場
合には、ラインメモリ回路から画データの読出しは行な
わず、符号の入力のみで2次元の復号化を行い復号結果
を順次ラインメモリ回路3へ書込み、1ラインの画デー
タ書込みが終了した時点で、画データの属性をF2に書
込む。
Flags Fl and F2 indicate the attributes of one line of image data stored in the line memory circuit 2.3, respectively. The line memory circuit 2 is a line memory in which a reference line is stored, and the line memory circuit 3 is a line memory in which one line of decoded image data is stored. When performing decoding, the two-dimensional decoding circuit 1 reads the flag F1 of the line memory circuit 2 and checks the attributes of the image data. If the attribute of the image data is not 1 line all white data (1 line all white), 0 image data is read out from the line memory circuit 2 as a reference line while inputting decoded data 19 from the line. When the attribute of 1 line is completely white, image data is not read from the line memory circuit, two-dimensional decoding is performed only by inputting the code, and the decoding results are sequentially written to the line memory circuit 3. When the image data writing is completed, the attributes of the image data are written to F2.

このようにすると、画データ属性が全白ラインを示して
いる時には画データの読出しが行なわれず符号の入力の
みになるので復号化時間を高速化できる。
In this way, when the image data attribute indicates a completely white line, the image data is not read out and only the code is input, so that the decoding time can be speeded up.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ラインメモリ内に1ライ
ン分の画データの属性情報をおくことで、1ラインの画
データが全白であるような場合に1ライン分の画データ
をラインメモリから読出すことが不要なので2次元復号
化を高速化できるという効果がある。
As explained above, the present invention stores the attribute information of one line of image data in the line memory, so that when one line of image data is completely white, one line of image data is stored in the line memory. Since it is not necessary to read data from the data, there is an effect that two-dimensional decoding can be speeded up.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すブロック図である。 1・・・2次元復号化回路、2.3・・・ラインメモリ
回路。
FIG. 1 is a block diagram showing an embodiment of the present invention. 1... Two-dimensional decoding circuit, 2.3... Line memory circuit.

Claims (1)

【特許請求の範囲】[Claims]  1ライン分の符号データとこの符号データの属性情報
とを記憶する第1のラインメモリと、復号された1ライ
ン分の画データとこの画データの属性情報とを記憶する
第2のラインメモリと、回線から受信し識別した前記属
性情報を含む符号データを書き込んだ前記第1のメモリ
を参照して2次元の復号化を行った画データとこの画デ
ータの属性情報とを前記第2のラインメモリに書き込む
2次元復号化回路とを有することを特徴とするファクシ
ミリ復号化回路。
a first line memory that stores one line of encoded data and attribute information of this encoded data; a second line memory that stores one line of decoded image data and attribute information of this image data; , the image data that has been two-dimensionally decoded by referring to the first memory in which coded data including the attribute information received and identified from the line is written and the attribute information of this image data are transferred to the second line. A facsimile decoding circuit comprising: a two-dimensional decoding circuit for writing into a memory.
JP1034036A 1989-02-13 1989-02-13 Facsimile decoding circuit Pending JPH02213278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1034036A JPH02213278A (en) 1989-02-13 1989-02-13 Facsimile decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1034036A JPH02213278A (en) 1989-02-13 1989-02-13 Facsimile decoding circuit

Publications (1)

Publication Number Publication Date
JPH02213278A true JPH02213278A (en) 1990-08-24

Family

ID=12403105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1034036A Pending JPH02213278A (en) 1989-02-13 1989-02-13 Facsimile decoding circuit

Country Status (1)

Country Link
JP (1) JPH02213278A (en)

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