JPH0311145B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image synthesizing device, and more particularly to an image synthesizing device that synthesizes at least two image signals.

An example of such a conventional high-speed image compositing method is, for example, image compositing in television. While receiving a certain program on the schedule, another program (counterprogram) is received, its image signal is stored in one frame memory (RAM), and the image stored in the memory is read out at a predetermined position of the schedule program. D/A
After conversion, a composite image was obtained by switching the image signals using a switching circuit. in this case,
Basically, it is a combination of analog signals, so
The switching circuit could be an analog switch. However, the above-mentioned conventional method cannot be used in real-time processing of run-length encoded image signals obtained by facsimile or the like.

As is well known, run-length encoding is a method for compressing and storing large continuous signals such as image signals. In other words, for example, in a place where there are 320 consecutive white pixels, what previously required a storage capacity of 320 bits is a code of several bits that means white and a code of several bits that means 320 (run length).
This method compresses the data to just 10-odd bits. Furthermore, there is also a method of increasing the compression ratio by making the run length variable using, for example, a modified Huffman code conversion code. In order to synthesize image signals compressed and encoded in this way, it is necessary to use the help of a computer, and therefore the processing is slow and non-real time.

The present invention has been made in view of the above points, and an image of a desired area in a second image represented by a compressed image signal is added to a desired area in a first image represented by a compressed image signal. The purpose of the invention is to efficiently obtain a third image signal representing a composite image obtained by combining the first image with a first storage means storing a first compressed image signal representing the first image; a second storage means storing a second compressed image signal representing the image; an instruction means for instructing a desired area in the first image and a desired area in the second image;
When a first compressed image signal is being read from the first storage means and a compressed image signal corresponding to an image of a desired area of the first image is being read from the first storage means, readout control means for reading out a compressed image signal corresponding to an image in a desired area in the second image out of the second compressed image signal from the second storage means; and a compressed image signal read out from the first storage means. a first decoding means that outputs a first image signal by decoding the image signal;
a second decoding means for outputting a second image signal by decoding the compressed image signal read from the storage means; and a second decoding means for outputting a second image signal by decoding the compressed image signal read from the storage means; by selecting a first image signal from the second decoding means corresponding to the inside of the desired area, and selecting a second image signal from the second decoding means corresponding to the inside of the desired area. The present invention provides an image synthesizing device having a selection means for outputting a third image signal representing a composite image obtained by synthesizing images of a desired area in the second image.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a system block diagram of an image composition apparatus according to the present invention. Reference numeral 1 denotes a document, which is structured to move in the direction of the thick arrow (hereinafter referred to as the sub-scanning direction or the X-axis direction) while being illuminated by an illumination device (not shown). 2 is a lens; 3 is a one-dimensional solid-state imaging device such as a CCD; the image of the original 1 is formed on the imaging plane of the CCD 3 via the lens 2; The thin arrows on the document 1 indicate the direction in which the CCD 3 sequentially scans based on the clock of the clock circuit 4 (hereinafter referred to as the main scanning direction or Y-axis direction). 5 is a video amplification circuit for amplifying the video signal obtained as a result of scanning to a desired value; 6;
is a binarization circuit that binarizes the video signal into either white or black. 7 is a run length encoder which uses, for example, CCITT's modified Huffman encoding method to encode the run length. Reference numeral 8 denotes an image memory having a hierarchical structure of at least three layers, as will be described later, using, for example, a RAM, and a magnetic disk 12 and a magnetic tape 13 as auxiliary storage devices. Reference numeral 9 denotes an image synthesizing device according to the present invention, which has a function of extracting a specific portion of one of two run-length encoded images and inserting it into a predetermined portion of the other image.

The run-length encoded signal by the run-length encoder 7 is decoded by the run-length decoder 10 via the signal line 17, and is printed by the printer 11, or is sent as an image via the signal line 14. The images are stored in the memory 8 and synthesized via the signal line 16 from the image synthesis circuit, and the synthesized image is outputted from the signal line 15, decoded by the run-length decoder 10, and printed by the printer 11. Signal lines 21 and 22 are input/output lines of the image synthesis circuit.

As mentioned above, signals that do not need to be combined or stored are transmitted via the signal line 17, which is functionally the same as the signal line 18 that bypasses the encoding circuit altogether. The compositing process not only processes the two images stored in the image memory 8, but also processes the two images stored in the image memory 8.
For signal 21 or 19 being read at 3,
Already stored images may be obtained from the signal line 16 and combined. Furthermore, the synthesized image is not only stored in the image memory 8 but also connected to the signal line 22 or 20.
It may also be directly transmitted to the printer 11 via the printer 11.
23 is a sequence controller that controls the operation of the image synthesis circuit.

FIG. 2 shows the image memory 8, image synthesis circuit 9, and sequence controller 2 shown in FIG.
FIG. 3 is a block diagram of the main parts of No. 3.

The image memory 8 has a hierarchical structure consisting of at least three layers, and is divided into a main image memory 8a, a sub-image memory 8b, and a composite image memory 8c. Hardware address counters 26, 29, and 46 each having an independent memory
, and independent address reference is possible. Of course, it is also possible to have a structure in which the addresses of each memory are allocated to a series of address spaces and the sequence controller 23 can refer to the data.

24 is a modified Huffman code decoder (hereinafter referred to as an M.H. decoder), which converts the main image encoded and stored by the run-length encoder 7 into a main image color signal (B/W (1)) 48 , a main image end-of-line signal (EOL(1)) 57, and a main image run length (RUN(1)) 62. Note (1)
means a signal related to the main image. The signal 48 is input to the data selector 30, the signal 57 is input to the data selector 33, and the signal 62 is input to the run length counter 25. The run length counter 25 counts up in synchronization with the clock pulse _2OT , and when it counts up until it matches the run length (RUN (1)) 62 of the M/H decoder 24, it is reset and at the same time starts counting up the address counter 26. By doing so, the next M.H encoded data in the main image memory 8a is read. Therefore, the output 51 of the run length counter 25 corresponds to real time, and hereinafter this real time processed output signal 51 will be referred to as real time main image run length (run length (1)). Further, the reset signal 54 used by the run length counter 25 is hereinafter referred to as the main image run length counting completion signal (EOR(1)). Each signal 51, 54
are input to data selectors 31 and 32, respectively.

The sub-image signal is also decoded in the same manner as the main image signal described above. That is, the M/H decoder 27 includes a run length counter 28 in the M/H decoder 24 for the main image.
is the main image run length counter 25, and the address counter 29 is the main image address counter 26.
correspond to each. Each signal of a sub-image color signal (B/W(2)) 49, a sub-image end-of-line signal (EOL(2)) 58, and a sub-image run length (RUN(2)) 63 obtained from the M/H decoder 27 are input to data selectors 30, 33 and run length counter 28, respectively. Similar to the processing of the main image signal, the run length counter 28 generates a real-time processed sub-image run length (run length (2)) 52;
It also outputs a reset signal, that is, a sub-image run length counting completion signal (EOR(2)) 55. Each signal 5
2, 55 are further data selectors 31, 32
is input. Note that (2) below indicates a signal related to the sub-image.

Various signals based on the main image and sub-image obtained in the above manner are used to select the main image or the sub-image by data selectors 30, 31, 32 and 33 according to the EOC signal, which will be described later, to produce a composite image color. signal (B/W (3)) 50, real-time composite image run length (Run Length (3)) 53, composite image run length count end signal (EOR (3)) 56, and composite image end-of-line signal (EOL ( 3))
Get 59. Note that (3) indicates a signal related to the composite image. Each signal 50, 53, 59 is input to the M/H encoder 45, and as described later, is M/H encoded in response to the signal 56, and is stored at the address of the composite image memory 8c determined by the address counter 46. be done.

Data selectors 30, 31 and 32 are switched and controlled in real time by an enable of composite signal (EOC) 60 from a flip-flop 64 to perform image composition.

The process by which the EOC signal is formed is as follows.
First, Y ₀ is written into the Y-axis start address memory 35 via the data bus 61 of the sequence controller 23 . Similarly, Y ₁ is written to the Y-axis end address memory 36, and
X ₀ is written in the memory 40 for the axis start address, and the memory 41 for the X-axis end address is written.
X ₁ is written to . X ₀ , X ₁ , in the sub-image
The address diagram of Y ₀ and Y ₁ is shown in FIG. In other words, the coordinates Y ₀ , Y ₁ , X ₀ of the area surrounded by a square in the figure
and X ₁ are written into memories 35, 36, 40 and 41, respectively. Next, compare the output of the Y-coordinate counter 34, which counts the _clocks from the clock circuit 4 in _FIG .
Comparators 37 and 38 generate outputs when the Y-axis direction reaches Y ₀ and Y ₁ , respectively, and input them to gate circuits 44 and 65, respectively, as Y-coordinate enable signals. Similarly, comparators 42 and 43 compare the output of the X-coordinate counter 39 for specifying the X-axis position of the sub-scanning with the outputs X _{0 and 0} and _X1 , an output is generated, and the output is input to the flip-flop 66 and used as an enable signal for the X coordinate. Y in gate circuits 44 and 65
The coordinate enable signal and the X coordinate enable signal are ANDed and the EOC signal 60 is obtained via the flip-flop 64. Therefore, if we refer to the EOC signal in terms of positive logic with reference to FIG. 12, it is a signal that becomes high level when the inside of the sub-image surrounded by a square is being accessed.

Next, the composite image color signal (B/W (3)) 50 and the real-time composite image run length (run length (3)) 5
3 and composite image end-of-line signal (EOL
(3)) The composite image signal encoded from 59 through the M/H encoder 45 is written into the composite image memory 8c. 46 is an address counter for controlling the address, which counts EOR (3).
When EOR (3) is input continuously, the end detection circuit 47 determines that the image has ended, and the address counter 46 stops counting.

The synthesized image run length counting end signal EOR(3) 56 includes the output of the AND gate 44, that is, the synthesis start signal Y _S 68, and the output of the AND gate 65, that is, the synthesis end signal Y _E 69. is applied. This occurs while the run length counter 25 or 28 is counting the run length, and the channel switching signal EOC6 is
When image synthesis is performed by inverting, the run length in the middle of counting in the channel before switching is handled as counting is completed with the run length in the middle of counting, encoded and stored in the memory 8c, This is for incrementing the address counter 46. This is called synthesis preprocessing.

Run length counter 28 is reset by synthesis start signal Y _S 68. Further, the run length counter 25 is reset by the synthesis end signal Y _E 69.
This occurs while the run length counter 25 or 28 is counting the run length, and the channel switching signal EOC
When 60 is inverted and image synthesis is performed, the run length that is being counted in the channel after being switched must be treated as the length from the run length that is being counted to the end of counting that counts are completed. This is called post-synthesis processing.

By performing the above-described pre-composition processing and post-composition processing, it is possible to perform composition of run-length codes, which are non-real-time data, in the real-time domain.

67 is an initial setting circuit. The XY coordinate memories 35, 36, 40, and 41 initially contain the coordinates of the part of the sub-image shown in FIG.
Store Y ₀ , Y ₁ , X ₀ and X ₁ . Then, image synthesis is executed in a pseudo manner, and when the synthesis start signal Y _S 68 becomes high level for the first time, that is, (X ₀ , Y ₀ )
The initial setting circuit 67 detects when the
The run length counter 28 and address counter 29 are stopped and the run length and address are held. Next, the XY coordinate memories 35, 36, 40 and 41 store the coordinates Y' ₀ , Y' ₁ , X' ₀ and X' ₁ of the part of the composite image shown in FIG. 12 surrounded by a square. urge Then, when formal image synthesis is executed, the sub-images X ₀ , X ₁ , Y ₀ and
The image inside the rectangular area indicated by Y ₁ is combined with the main image, and the combined image X′ ₀ , X′ ₁ , Y′ ₀ and Y′ ₁
It will fit into the rectangular area indicated by . The situation is shown in FIGS. 11 and 12. In addition, A,
A' is a main image, B and B' are sub-images, and C and C' are composite images. Therefore, in the image composition according to the present invention, an image cut from an arbitrary location can be inserted into an arbitrary location.

FIG. 3 is a more detailed block diagram centered on the main image memory 8a, run length counter 25, and address counter 26 of the block diagram shown in FIG. Components common to FIGS. 1 and 2 are given common numbers. The main image data stored in the main image memory 8a is decoded by the M.H decoder 24, and the color signal B/W (1) 48,
It is separated into a run length RUN(1) 62 and an end-of-line signal EOL(1) 57.

Also, 73 is the enable of Huffman signal
EOH (1) is a signal line that becomes high level when the data on signal lines 48, 62, and 57 are enabled. That is, the run length RUN(1) is applied to the B input terminal of the comparator 72, and when the enable signal EOH(1) 73 rises, the counters 25a and 25b corresponding to the run length counter 25 in FIG. At the same time, the counter 25a starts counting.
Since the output Q of is applied to the A input terminal of the comparator 72, the counter 25a has the run length
When counting is done until it becomes equal to A= of the comparator 72
The B output terminal 54 becomes high level and becomes the run length counting end signal EOR(1) 54. At the same time, the address counter 26 is incremented and the counters 25a and 2 are incremented via the OR gates 74 and 75.
5b. The address of the memory 8a is incremented, the next data is output, and the M/H decoder 2
When the decoding is completed at 4, the EOH (1) 73 goes high again, so the counters 25a and 25b start counting the run length of the next data. The counters 25a and 25b usually count exactly the same value, but when the synthesis end signal Y _E 6
Only when 9 is input, the counter 25b is reset. Therefore, the run length (1) at that time is the run length counted by the counter 25a after the synthesis end signal _YE is input. This is post-synthesis processing.
VSYNC is a sub-scanning synchronizing signal, and resets counters 25a and 25b every time an X-axis scan is completed. Also, the signal VERT EN is a sub-scanning enable signal.
This signal is at a high level only during execution of an operation, and is intended to prevent the address counter 26 from counting during other periods. Sequence controller 23
has signal lines 76 and 77 for initializing the address counter. That is, in order to select a desired image from the main image memory 8a which stores a plurality of images, its leading address is set. By inputting the count value of the address counter 26 to the sequence controller, the signal line 156 can determine the capacity required to store one image as a run-length code.

FIG. 4 is a more detailed block diagram of the M.H decoder 24 and address counter 26 shown in FIG. Since the block diagram of FIG. 4 is common to the main image channel and the sub-image channel, only the main image channel will be described.

For example, one byte of the main image memory 8a is 8
Use one with a bit configuration. 78 is a shift register with parallel input and serial output; when the shift enable signal 93 is at a high level, the parallel data is converted into serial data according to the clock 2O/ _T applied through the AND gate 80, and then sent to the shift register 81 through 94. Output to. The counter 26a is an octal counter, and together with the counter 26b constitutes the address counter 26 in FIG. At the same time, the address counter 26b is incremented by 1 byte. Therefore, by simply setting the shift enable signal line 93 to a high level, a series of encoded image signals from the signal line 94 in response to the clock 2O/ _T can be shifted from the serial input parallel output having a data length of 13 bits. It is input to register 81. 83 is a ROM for converting a modified Huffman code using the address line as input and the data line as output. The M/H code consists of a white run code word, a black run code word, and a make-up code defined by the CCITT standard. The output of the ROM 83 consists of a color signal B/W 48, a run length R, a make-up code output M, an end-of-line EOL 57, and an enable signal EN.

The data is decoded and the enable signal EN
When becomes high, the shift enable signal 93 at the output of flip-flop 91 goes low, turning off AND gate 82, thereby stopping further shifting of data, and transferring data to latch 86 via AND gates 87 and 89. and 88
Latch the data to . When the data is a black run or a white run, the make-up code output M is at a low level, so the data selectors 84 and 8
5 selects the B input, sets all upper 6 bits to zero, and assigns white or black run length to the lower 5 bits. When the data is a make-up code, the make-up code output M becomes high level, the data selectors 84 and 85 select the A input, set the lower 5 bits to all zeros, and assign the make-up code to the upper 6 bits. . this is
This is an operation to reduce the number of data in ROM83. Therefore, the run length RUN62 uses the output of latch 86 as the upper 6 bits and the output of latch 88 as the lower 5 bits.
Consists of a total of 11 bit data lines. 90 is a flip-flop that detects the enable signal EN of the ROM 83 in synchronization with the clock 2O/ _T , and if EN becomes high level, the gates 87 and 8
9 is opened and the output data of latches 86 and 88 are established, output 92 becomes high level and the run length counter 25a starts counting. Eventually, the output of the run length counter 25a and the run length RUN6
When the values of 2 become equal, the A=B output of the comparator 72 goes high, resetting the counter 25a, and at the same time, the output of the flip-flop 90 goes low to stop counting, and at the same time, the output of the flip-flop 91 goes low. to high level and start shifting the next image data. By repeating the above operations, image data is sequentially decoded.

FIG. 5 shows the sub-image memory 8 _b in FIG.
This is a more detailed block diagram centered on the run length counter 28 and address counter 29, and corresponds to FIG. 95 is Enable of Huffman (EOH (2)), 96 and 97 are Orgate, 98
and 99 is an AND gate, 100 is an inverter, 101 is a comparator, 102 is an inverter, 1
03 is an AND gate, 104 is a flip-flop, 105 is a data selector, and 106 is a signal line. The differences from Fig. 3 are as follows.

When EOL (2) is high level, inverter 1
02 and the AND gate 103 do not output the EOR (2) signal, and the initial setting circuit 67
(inside the dashed box) has been added. For example, in FIG. 12, since the area of the image cut out from the sub-image is relatively small, the EOL signal 58 is not included therein. However,
If you specify the area to be cropped to the edge of the screen,
Or, if there is some kind of malfunction, there is a possibility that the EOL signal will be detected. Since this embodiment employs only the EOL signal of the main image, it is not desirable that the EOL signal of the sub-image be detected. Therefore, the EOR signal is turned off by the AND gate 103 to prevent the EOL signal of the sub-image signal from being written to the composite image memory 8c.

In addition, the initial setting circuit 67 within the broken line receives the initial setting signals (X ₀ ,
When Y ₀ )SET is high, AND gate 98 is open and data selector 105, controlled via inverter 100, selects the B input from flip-flop 104.
Therefore, the run length counters _28a and _28b constituting the run length counter 28 in FIG. 2 start counting after the flip-flop 104 is reset by VSYNC, and eventually the synthesis start signal Y _S 68 is input. Since the output of the flip-flop 104 becomes low level, the output of the run length counter _28a is changed through the data selector 105 and the AND gate 99.
The ENP input and the ENT input of the address counter 29 become low level, and counting is stopped. Therefore, the address counter 29 and the run length counter 28
In a, the address where the sub-image data of the portion corresponding to the synthesis start position (X ₀ , Y ₀ ) is stored and its position in the run length are stored, and counting is stopped there. Next, when the initial setting signal (X ₀ , Y ₀ ) SET of the sequence controller 23 is at a low level, that is, in the synthesis mode, the AND gate 98 closes and the counter 28 _a
Not reset by VSYNC. Also, the data selector 105 has selected the A input,
Flip-flop 10 cleared with VSYNC
Since the Q output of 4 is low level, AND gate 99
is turned off, and even if the VERT EN number is input,
The Andres counter 29 and the run length counter _28a remain at their initial setting values.
Eventually, the coordinates (X′ ₀ ,
When scanning progresses to Y' ₀ ) and the synthesis start signal Y _S becomes high level, the Q output of flip-flop 104 becomes high level and counters 29 and 28a start counting. Through the above operations, it is possible to synthesize an image cut out from an arbitrary location of the sub-image onto an arbitrary location of the main image to obtain a composite image.

FIG. 6 is a more detailed block diagram of the XY coordinate detection circuit shown in FIG. 2. Components common to those in FIG. 2 are given the same numbers.

The Y coordinate counter 34 receives a horizontal synchronization signal
Reset with HSYNC, count clock 2O/ _T , and output main scanning address. Further, the X-coordinate counter 39 is reset by the vertical synchronizing signal VSYNC, counts HSYNC, and outputs the sub-scanning address. Data writing to the memories 35, 36, 40, and 41 is equivalent to the memory of the microcomputer MPU inside the sequence controller 23. When the DMA control line 118 is set to a low level, that is, in memory write mode, the AND gates 111 to 114 are opened and the read/write control line (R/W) 119 is enabled. Memory (RAM) 35, 36, 40 and 4
1 data input terminal is common data bus 61
The memory is selected by the chip select terminal CS. Reference numeral 116 denotes a decoder for memory selection, which decodes the address bus 117 to allocate it to the address space of the MPU of the sequence controller 23.
In DMA mode, the signal line 118 goes high, so each memory goes into read mode.
Also, since chips are selected by OR gates 107 to 110, all memories can be accessed regardless of decoder 116.

In the example shown in Figure 6, if the MPU data bus is, for example, 8 bits, 12 to 13 bits of XY
Since the coordinate counters 34 and 39 are insufficient, each memory 35, 36, 40, and 41 stores the XY coordinates sliced into 8 bits. In addition, each memory 35, 36, 40 and 41 has
Although a format in which one piece of coordinate data is stored in each memory is shown, for example, a format in which two or more pieces of coordinate data are stored in one memory and read out in a time-sharing manner may also be used.

This is because, as explained in FIG. 5, once the reading of the sub-image memory _8b is started by the composition start signal Y _S 68, it is read out in perfect synchronization with the main image memory _8a . This is because even if the subsequent enable of composite signal ENC60 changes by several pixels, only the outline of the composite image changes, and the image itself does not change at all. Therefore, it is not necessary to time-divide one pixel; for example, when dividing into four, four pixels may be used.

Note that the method by which the sequence controller 23 refers to the address counters 26, 29, and 46 has not been specifically described;
6, 40 and 41.

Note that the comparators 37, 38, 42, 43 and flip-flops 64, 66 have the same structure and operation as explained in FIG.

FIG. 7 is a detailed block diagram of a composite image compressor for compressing and storing composite images. EOC signal 60 is inverter 124
via data selectors 30, 31 and 32
is switching. EOR (1) 54 or EOR (2) 55 selected by the data selector 32 is
OR gates 70 and 71 add the Y _S signal and Y _E signal, and AND gate 123 synchronizes with clock 2O/ _T to generate EOR (3) signal 56, which connects latch 1.
The data latched in 20, 121 and 122 is being read. The EOR(3) signal also becomes the strobe signal for the M.H code encoder 45 and the enable signal for the address counter 46 via AND gate 129 and latch 130. That is, each time the run length count is completed, the latch 12
Read data from 0, 121 and 122. During image synthesis, data selectors 30 to 33 select B/W ( ₂ ), run length ( ₂ ), EOR (2),
Since EOL (2) is selected, B/W (3) 5
0, run length (3) 53 and EOL (3) 59
are signals related to the sub-images, respectively, and when image synthesis is not in progress, are signals related to the main image.

The signals 50, 53, and 59 are Huffman encoded by the modified Huffman encoder 45 using the EOR(3) 56 signal, and the address counter 46 is incremented. The M/H encoded composite image is stored at the address of the composite image memory 8c designated by the address counter 46 in response to the read/write W/R signal from the AND gate 132 which receives EOR(3) and the read/write signal.

EOL(3) signal 59 is the flip-flop 125
is detected and becomes the horizontal synchronization signal HSYNC. Also, since the end of the image is determined when the EOL (3) signal is input five times in a row, the shift register 1
26 and a 5-input AND gate 127 are used to detect the end. Its output is synchronized with the clock 2O/ _T by a flip-flop 128 to obtain an end signal END. The signal has the function of stopping address counter 46 via AND gate 129.

The flip-flop 131 outputs a vertical enable signal, VERT EN signal, which rises with VSYNC and falls with END.

FIG. 8 is a more detailed block diagram centered on the M/H code encoder 45 shown in FIG. 134 is a ROM for M/H code encoding
Then, the M/H code is output to _D1 and the data length is output to _D2 . A shift register 135 converts the parallel input MH codes into a serial signal. Also 136
is a shift register for rearranging the serially converted MH code into parallel data of 8 bits each. When the run length counting end signal EOR (3) is input, data is latched and loaded into the latch 138 and the shift register 135 by the AND gate 137 in synchronization with the clock 2O/ _T . The latched data length _D2 is the comparator 143
is applied to the B input of
42 and shift registers 135 and 136. The counter 141 is an 8-bit counter that increments the address counter 46 every 8 bits and also reads data from the memory _8c via the AND gate 132. counter 14
2 is for counting the data length of the MH code, the counting result is applied to the A input of the comparator 143, and when A and B become equal, the counter 142
and flip-flop 139.
is inverted to stop counters 142, 141 and shift registers 135 and 136. Also,
The AND gate 144 also stops the address counter 46.

An example of an input device for XY coordinates is shown in FIGS. 9 and 10. 145 is a simple XY coordinate input device, 146 is its numeric key switch, 147 is X, Y, M, =, and exit key;
8 is a function key, and 149 is a light emitting display. With this device, if you want to set the X ₀ coordinate to 132 mm, for example, press "X", "O/", "=", "1", "3", "2", "EXCUTE" and the light emitting display 149 will show the At the same time, a numerical value corresponding to 132 mm is input into the X ₀ memory 40 via the sequence controller 23. Input of other coordinates is performed in the same manner. Note that the EXCUT key is used to officially register the value that has been temporarily registered and displayed on the display.

The function key 148 is used to save the trouble of inputting coordinate data each time, and is used to recall coordinate data once registered with a single touch.

In the XY coordinate input device shown in FIG. 10, coordinates are not input numerically but by touching a coordinate designation area 152 on a digitizer 150 with a stylus pen 153. Therefore, the original is placed in the coordinate designation area 15.
2 can be specified using the stylus pen 153. The specified area is CRT display 1
54 along with the characters. Further, 151 is a menu area in which various commands can be provided. The menu area 151 occupies a part of the digitizer 150,
The sequence controller 23 can distinguish between menus and coordinates by determining the magnitude of numerical values.

As explained above, according to the present invention, run-length encoded image data can be combined with each other, so the storage capacity of the image memory can be reduced, which is highly effective in reducing the cost of the apparatus. The method shown in the illustrated embodiment is only one embodiment of the present invention, and other methods may be used as long as the basic principle is the same.

Although the present invention has been described only with respect to run-length encoded image data, even if one of the images is unencoded image data, it can be combined very easily. In FIG. 1, signals 18, 19, and 20 indicated by broken lines indicate the flow of unencoded data, but the present invention also includes the synthesis of such data.

Further, in FIG. 1, 155 is a character generator, and it is also possible to insert a character into the square area of the composite image shown in FIG. Conversely, it is also possible to make the outside of the rectangular area a character. FIG. 13 shows a block diagram of an apparatus for synthesizing a run-length encoded image signal and a character generator according to this embodiment. In the figure, components common to those in FIG. 2 are given the same numbers. The system shown in FIG. 13 uses the run-length encoded image signal stored in the main image memory 8-1 and the output signal of a character generator consisting of a buffer memory 158 and a character memory 157. It is for synthesizing. Figure 13 is the second
The only difference is that the sub-image data expander (Fig. 5) in the figure is replaced with a character generator, and the rest is exactly the same as in Fig. 2.

158 is a buffer memory (RAM) whose address line is controlled by a data selector 159.
Y coordinate counter 34 and X coordinate counter 39
, or the address bus line 177 of the sequence controller 23. 160 is a switching control line for this purpose.

First, the format of the character to be synthesized is registered in the buffer memory 158 from the sequence controller 23 via the data bus line 61 by controlling the control line 160. The format is expressed, for example, in ASCII code. Next, by controlling the control line 160, the address line of the buffer memory 158 is set to the Y coordinate counter 34 and the X coordinate counter 39.
Connect to the signal from and read the character code written earlier at the specified coordinates. Its output controls the address bus of character memory 157 and generates a character output signal corresponding to a predetermined character code. The output is input to a run length counter 161, run length encoded, and generates a sub-picture color signal 49, a real-time sub-picture run length 52, and a sub-picture run length counting end signal 55, which are combined with the main picture signal. . The operation of the synthesis circuit is similar to that described in FIG.

FIG. 14 is a detailed view of the main part of FIG. 13.
The character memory 157 is a ROM (read only memory) that stores 64 types of 8×8 dot characters. Address lines _A0-2 decode the lower three bits of the X-coordinate counter 39 to control characters in the sub-scanning direction. Address lines _A3-8 are for character selection.
The output line 176 of the character memory 157 is output in 8-bit parallel form, and is converted from parallel to serial by a shift register 163. The shift register 163 shifts data in synchronization with the system clock 171, obtains a ripple output signal from an octal counter 162 for detecting shift completion, and loads a parallel character output signal 176. The ripple output 173 also becomes an enable signal for the Y coordinate counter 34, and by stepping in synchronization with the system clock 171, the buffer memory 158
Select the next character code stored in . The buffer memory 158 consists of a 6-bit 4096-word RAM (random access memory), and its address lines A0 _{to A5} are character Y
Coordinates, A _6-11 are for selecting the X coordinate of the character. 172 is a horizontal synchronization signal. As described above, the Y coordinate counter 34, the X coordinate counter 39, the buffer memory 158, the character memory 157, the shift register 163, and the octal counter 162 constitute a character generator.

Next, the output of the shift register 163 is set to latch 1.
64, and exclusive OR 166 detects where black and white are inverted. A run length counter 165 counts the system clock 171, and when a predetermined value is reached, outputs a ripple output RCO, and outputs a sub-image run length counting completion signal EOR(2) 55 via an OR gate 170. Also, the black and white of the image is reversed and the exclusive or 166
When the output of becomes high level, run length counter 1
65 is cleared and at the same time outputs EOR(2) via the OR gate 170. At this time, the run length is latched in latch 168 and is the real-time sub-image run length run length (2) 52. Also,
The video signal passing through latch 164 is then transferred to latch 167.
and sub-image color signal B/W(2)4
It becomes 9. AND gate 169 is for latching data in synchronization with system clock 171 when the EOR(2) signal is output. The synthesis start signal Y _S 68 is used to clear the run length counter 165.

As described above, the synthesis device according to the present invention can also be applied to synthesis of a run-length encoded image signal and another image signal, for example, an image signal from a character generator.

As explained above, according to the present invention, the first compressed image signal representing the first image is read from the first storage means, and the compressed image signal corresponding to the image in the desired area of the first image is read out from the first storage means. a second image representing a second image from the second storage means when being read;
out of the compressed image signals corresponding to an image in a desired area in the second image, and outputs a first image signal by decoding the compressed image signal read from the first storage means. and outputting a second image signal by decoding the compressed image signal read from the second storage means, and selecting the first image signal corresponding to the outside of the desired area of the first image; The second image signal is selected corresponding to the inside of the desired area.

As a result, the compressed image signal representing the first image and the compressed image signal corresponding to the image in the desired area in the second image are not read from the first and second storage means at separate times. Since both compressed image signals are read out in parallel, the time required to read out both compressed image signals is shortened, and both compressed image signals can be converted into image signals that can be processed in real time, and the first image Real-time signal synthesis is possible without storing the image signal corresponding to the image of the desired area in the second image and the image signal corresponding to the image of the desired area in the second image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall system of an image synthesizing apparatus according to the present invention, FIG. 2 is a block diagram showing the configuration of an image synthesizing apparatus according to the present invention, and FIG.
The figure is a block diagram showing the configuration of the main image data expander, and FIG. 4 is a block diagram showing an embodiment of the modified Huffman code decoder.
FIG. 5 is a block diagram showing the configuration of the sub-image data expander, FIG. 6 is a block diagram showing the configuration of the X-Y coordinate detection circuit, FIG. 7 is a block diagram showing the configuration of the composite image compressor, and FIG. Figure 8 is a block diagram showing one embodiment of the modified Huffman code encoder, Figure 9 is an explanatory diagram showing the configuration of one embodiment of the coordinate input device, and Figure 10 is another implementation of the coordinate input device. An explanatory diagram showing an example configuration,
Fig. 11 is an explanatory diagram showing the image synthesis of the main image and sub-image, Fig. 12 is an explanatory diagram showing the address of the image synthesis of the main image and sub-image, and Fig. 13 is the run-length encoded image signal. FIG. 14 is a block circuit diagram showing a synthesis device of a character generator and a character generator, and FIG. 14 is a block circuit diagram showing details of the main part of FIG. 13. 1... Original, 2... Lens, 3... CCD, 4
...Clock circuit, 5...Video amplifier circuit, 6...
... Binarization circuit, 7 ... Run length encoder, 8
...Image memory, 9...Image synthesis circuit, 10...
...Run-length decoder, 11...Printer,
12...Magnetic disk, 13...Magnetic tape, 2
3... Sequence controller, 24... Modified Huffman code decoder, 25... Run length counter, 26... Address counter, 27...
Modified Huffman code decoder, 28...Run length counter, 29...Address counter, 30
~33...Data selector, 34...Y coordinate counter, 35...Memory for Y-axis start address ( _Y0 ), 36...Memory for Y-axis end address ( _Y1 ), 37, 38...Comparator, 39
...X-coordinate counter, 40...Memory for X-axis start address ( _X0 ), 41...Memory for X-axis end address ( _X1 ), 42, 43...Comparator, 45...Modified Huffman code Encoder, 46...Address counter, 47...End detection circuit, 48...Main image color signal (B/W
(1)), 49...Sub-image color signal (B/W
(2)), 50... Composite image color signal (B/W
(3)), 51...Real-time main image run length (run length (1)), 52...Real-time sub-image run length (run length (2)), 53...Real-time composite image run length (run length length (3)), 54... Main image run length counting end signal (EOR (1)), 55... Sub image run length counting end signal (EOR (2)), 56... Composite image run length counting end signal (EOR(3)), 57... Main image end-of-line signal (EOL(1)), 58... Sub-image end-of-line signal (EOL(2)), 59...
...Composite image end-of-line signal (EOL (3)),
60... Enable of composite signal (ENC), 61... Data bus, 62... Main image run length (RUN (1)), 63... Sub image run length (RUN (2)), 67... Initial Setting circuit, 68...
Synthesis start signal Y _S , 69...Synthesis end signal Y _E , 7
3... Enable of Huffman (EOH (1)), 9
5... Enable of Huffman (EOH (2)), 1
17...Address bus, 118...DMA control line, 119...Read/write (R/W) control line,
145...XY coordinate input device, 146...Numeric key switch, 147...Execute key, 1
48... Function key, 149... Light emitting display, 150... Digitizer, 151... Menu area, 152... Coordinate specification area, 153...
...Stylus pen, 154...CRT display, 155...Character generator.

Claims (1)

[Scope of Claims] 1. A first storage means that stores a first compressed image signal representing a first image; and a second storage means that stores a second compressed image signal that represents a second image. , instruction means for instructing a desired area in the first image and a desired area in the second image; and reading a first compressed image signal from the first storage means, and reading out a first compressed image signal from the first storage means; When a compressed image signal corresponding to an image in a desired area of is being read out from the first storage means, a desired area in the second image of the second compressed image signal is read out from the second storage means. readout control means for reading out a compressed image signal corresponding to the image; first decoding means for outputting a first image signal by decoding the compressed image signal read from the first storage means; a second decoding means for outputting a second image signal by decoding the compressed image signal read from the second storage means; A desired area in the first image is selected by selecting a first image signal from the decoding means and a second image signal from the second decoding means corresponding to the inside of the desired area. and selecting means for outputting a third image signal representing a composite image obtained by combining images of a desired area in the second image.