JPH02213156A - 半導体フレーム - Google Patents

半導体フレーム

Info

Publication number
JPH02213156A
JPH02213156A JP1034352A JP3435289A JPH02213156A JP H02213156 A JPH02213156 A JP H02213156A JP 1034352 A JP1034352 A JP 1034352A JP 3435289 A JP3435289 A JP 3435289A JP H02213156 A JPH02213156 A JP H02213156A
Authority
JP
Japan
Prior art keywords
stitch
die pad
bonded
chip
solder material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1034352A
Other languages
English (en)
Inventor
Mitsuharu Ishibashi
光治 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1034352A priority Critical patent/JPH02213156A/ja
Publication of JPH02213156A publication Critical patent/JPH02213156A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、チップが搭載される半導体フレームに係り
、特にステッチボンド不良の解消に関するものである。
〔従来の技術〕
第５図はチップが搭載された従来の半導体７レムを示す
斜視図、第６図は、第５図のＢ−Ｂ’線におけろ断面図
であり、半導体フレーム１の中央部にダイパット５があ
り、ろう材６を介してチップ２を接着した後、金線４で
チップ２と宙釣り部７およびリード１０のメツキ部９を
それぞれ接続している。なお、３はステッチを示す。
次にＩＣ組立てについて説明する。
ウェハプロセス、ウェハテストが完了したウェハは、グ
イシング工程に投入され個々のチップ２に分割される。
分割されたチップ２は、良品チップのみろう材６を介し
て第７図に示すような半導体フレーム１のダイパッド５
の中央にグイボンドされる。次に金線４でチップ２と宙
釣り部７およびリード１ｏがそれぞれ接続された後、第
８図に示すようにモールド樹脂１１で所要の形状とされ
、外気と遮断されろ。次にモールド樹脂１１の表面に品
種名等の刻印が印刷され、形状にリードフオームされる
。
〔発明が解決しようとする課題〕
上記のような従来の半導体フレームでは、チップ２のグ
イボンド時にろう材６が宙釣り部７のステッチ領域まで
流れることがあるため、ワイヤボノド時に宙釣り部７の
ステッチ領域にステッチ３がボンドできなくなることが
あるという問題点があった。
この発明は、上記のような問題点を解消するためになさ
れたもので、グイボンド時にろう材が宙釣り部まで流れ
ないようにしてステッチボンドの不良をなくし、歩留り
を向上させることが可能な半導体フレームを得ることを
目的とする。
〔課題を解決するための手段〕
この発明に係る半導体フレームは、宙釣り部のステッチ
がボンディングされるステッチ領域とダイパット間にろ
う材阻止用の突起を設けたものである。
〔作用〕
この発明においては、グイパ・フトにチップをボンディ
ングするためのろう材が突起によって阻止され、ステッ
チ領域まで流れろことがなくなる。
〔実施例〕
第１図はこの発明の半導体フレームの一実施例を示す斜
視図、第２図は、第１図のＡ−Ａ’林における断面図を
示す。これらの図において、第５図、第６図と同一符号
は同一のものを示し、８はろう材阻止用の突起である。
すなわち、分割されたチップ２は、ダイパット５の中央
にろう材６を介してグイボンドされ、その時、ろう材６
はチップ２の裏面を全面的に濡らすため、グイパット５
の四方に流れる。そして、ついには宙釣り部７まで流れ
るが、この発明では、宙釣り部７のステッチ３がボンデ
ィングされる領域とダイパッド５間にろう材阻止用の突
起８を設けているので、ステッチ３をステ・ソチ領域に
確実にボンディングでき、歩留りが向上する。
この発明においても、ダイシング→ダイボンド→ワイヤ
ボンド→モールド→刻印→リードフオームの順に工程が
進み、上記のようにしてチップ２が搭載された半導体フ
レーム１は、その後、第３図に示すようにモールド４！
１脂１１で樹脂モールドされ、刻印された後、第４図１
ζ示すようにリードフオームされて完成する。
〔発明の効果〕
この発明は以上説明したとおり、宙釣り部のステッチが
ボンディングされるステッチ領域とダイパット間にろう
材阻止用の突起を設けたので、チップのグイボンド時に
ろう材がステッチ領域まで流れることがなくなり、確実
にステッチがボンディングでき、高歩留９で精度の高い
ＩＣが得られるという効果がある。
【図面の簡単な説明】
第１図はこの発明の半導体フレームの一実施例を示す斜
視図、第２図は、第１図のＡ−Ａ’線における断面図、
第３図はこの発明の半導体フレームを用いての樹脂モー
ルド状態を示す断面図、第４図はＩＣ完成状態を示す断
面図、第５図は従来の半導体フレームを示す斜視図、第
６図は、第５図のＢ−Ｂ’林における断面図、第７図は
半導体フレームの概要を示す図、第８図は従来の半導体
フレームを用いての！１詣モールド状態を示す断面図で
ある。 図において、１は半導体フレーム、２はチップ、３はス
テッチ、４は金線、５はグイパット、６はろう材、７は
宙釣り部、８はろう材阻止用の突起、９はメツキ部、１
０はリード、１１はモールド樹脂である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人　大　岩　増　雄　　　（外２名）第 図 第 図 第 図 〕〕モールドｍ曙 第 図 第 図

Claims (1)

    【特許請求の範囲】
  1. チップがボンディングされるダイパットと、このダイパ
    ットに接続された宙釣り部と、前記ダイパッドの外周に
    配置された複数のリードからなる半導体フレームにおい
    て、前記宙釣り部のステッチがボンディングされるステ
    ッチ領域と前記ダイパット間にろう材阻止用の突起を設
    けたことを特徴とする半導体フレーム。
JP1034352A 1989-02-14 1989-02-14 半導体フレーム Pending JPH02213156A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1034352A JPH02213156A (ja) 1989-02-14 1989-02-14 半導体フレーム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1034352A JPH02213156A (ja) 1989-02-14 1989-02-14 半導体フレーム

Publications (1)

Publication Number Publication Date
JPH02213156A true JPH02213156A (ja) 1990-08-24

Family

ID=12411761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1034352A Pending JPH02213156A (ja) 1989-02-14 1989-02-14 半導体フレーム

Country Status (1)

Country Link
JP (1) JPH02213156A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0546435A2 (en) * 1991-12-12 1993-06-16 STMicroelectronics S.r.l. Protection device for integrated circuit associated with relative supports
DE4318727A1 (de) * 1992-06-05 1993-12-09 Mitsubishi Electric Corp Halbleitervorrichtung mit LOC-Struktur sowie dazugehöriges Herstellungsverfahren und dazugehöriger Zuführungsdraht-Rahmen
WO2001091175A1 (en) * 2000-05-26 2001-11-29 Casem (Asia) Pte Ltd Method and device for bleed out control in solder bonding
JP2008066553A (ja) * 2006-09-08 2008-03-21 Furukawa Electric Co Ltd:The 半導体装置

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0546435A2 (en) * 1991-12-12 1993-06-16 STMicroelectronics S.r.l. Protection device for integrated circuit associated with relative supports
EP0546435A3 (ja) * 1991-12-12 1994-03-16 Sgs Thomson Microelectronics
DE4318727A1 (de) * 1992-06-05 1993-12-09 Mitsubishi Electric Corp Halbleitervorrichtung mit LOC-Struktur sowie dazugehöriges Herstellungsverfahren und dazugehöriger Zuführungsdraht-Rahmen
US5535509A (en) * 1992-06-05 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Method of making a lead on chip (LOC) semiconductor device
US5724726A (en) * 1992-06-05 1998-03-10 Mitsubishi Denki Kabushiki Kaisha Method of making leadframe for lead-on-chip (LOC) semiconductor device
DE4318727C2 (de) * 1992-06-05 1998-03-12 Mitsubishi Electric Corp Verfahren zur Herstellung einer Halbleitervorrichtung mit LOC-Struktur sowie dazugehöriger Zuführungsdrahtrahmen
US5763829A (en) * 1992-06-05 1998-06-09 Mitsubishi Denki Kabushiki Kaisha Leadframe including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the leadframe
US5900582A (en) * 1992-06-05 1999-05-04 Mitsubishi Denki Kabushiki Kaisha Lead frame including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the lead frame
WO2001091175A1 (en) * 2000-05-26 2001-11-29 Casem (Asia) Pte Ltd Method and device for bleed out control in solder bonding
JP2008066553A (ja) * 2006-09-08 2008-03-21 Furukawa Electric Co Ltd:The 半導体装置

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