JPH0221144B2 - - Google Patents
Info
- Publication number
- JPH0221144B2 JPH0221144B2 JP56135726A JP13572681A JPH0221144B2 JP H0221144 B2 JPH0221144 B2 JP H0221144B2 JP 56135726 A JP56135726 A JP 56135726A JP 13572681 A JP13572681 A JP 13572681A JP H0221144 B2 JPH0221144 B2 JP H0221144B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- sio
- interlayer insulating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 23
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 3
- 230000001678 irradiating effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 238000002844 melting Methods 0.000 description 9
- 230000008018 melting Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000007704 transition Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
Description
【発明の詳細な説明】
本発明は、レーザーアニール等の様な瞬時高温
熱処理を用いて製造する、多層構造の半導体装置
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer semiconductor device using instantaneous high-temperature heat treatment such as laser annealing.
多層構造を有する半導体装置のうち、特に、第
二層目以上の層に能動素子領域を有する半導体装
置の製造工程においては、能動素子領域となる半
導体膜を能動素子を形成するのに適する単結晶に
近い膜にするため、その半導体膜にレーザーアニ
ール等の瞬時高温熱処理を施すという手段が用い
られる。 Among semiconductor devices having a multilayer structure, especially in the manufacturing process of a semiconductor device having an active element region in the second layer or higher, the semiconductor film that becomes the active element region is formed using a single crystal film suitable for forming an active element. In order to obtain a film close to that of the semiconductor film, a method is used in which the semiconductor film is subjected to instantaneous high-temperature heat treatment such as laser annealing.
第１図は、多層構造を有する半導体装置におい
て第二層目の能動素子領域となるべき半導体膜を
レーザーアニールする場合の断面図である。第１
図はMOS型デバイスの断面図であり、１はシリ
コン基板、２はSiO2膜、３はソース、ドレイン、
４は多結晶シリコンゲート電極、５は金属配線、
６は層間絶縁膜、７はSiO2膜、８は２層目のシ
リコン膜、９が第１層目の能動領域、８が第２層
目の能動領域である。第１図において層間絶縁膜
である厚いSiO2膜６上に被着したシリコン膜８
を単結晶に近づけるため、８の表面にレーザー光
１０を照射し、温度を上昇させるのであるが、レ
ーザー光１０の部は膜８及び６を透過し、第１層
９に達する。特に、第２層目の素子分離領域を構
成するSiO2膜７が存在する場合は、レーザー光
１０が大部分透過して第１層９に達し、第１層を
構成するすでに完成した素子を極く短時間ではあ
るが、1000℃以上に昇温させることになる。この
様な場合、高温の影響で多結晶シリコンゲート４
を持つFETの特性が変化したり、第１層目の金
属配線５とシリコン基板１の一部に形成されたソ
ース・ドレイン領域３との合金化反応が進んでソ
ース・ドレイン接合を破壊する等という問題点が
存在する。 FIG. 1 is a cross-sectional view when laser annealing a semiconductor film to become a second layer active element region in a semiconductor device having a multilayer structure. 1st
The figure is a cross-sectional view of a MOS type device, where 1 is a silicon substrate, 2 is a SiO 2 film, 3 is a source, a drain,
4 is a polycrystalline silicon gate electrode, 5 is a metal wiring,
6 is an interlayer insulating film, 7 is a SiO 2 film, 8 is a second layer silicon film, 9 is a first layer active region, and 8 is a second layer active region. In FIG. 1, a silicon film 8 is deposited on a thick SiO 2 film 6, which is an interlayer insulating film.
In order to make the layer closer to a single crystal, the surface of the layer 8 is irradiated with a laser beam 10 to raise the temperature, but a portion of the laser beam 10 passes through the films 8 and 6 and reaches the first layer 9. In particular, when the SiO 2 film 7 that constitutes the second layer element isolation region is present, most of the laser beam 10 passes through and reaches the first layer 9, damaging the already completed elements that constitute the first layer. Although it is only for a very short time, the temperature will be raised to over 1000℃. In such a case, the polycrystalline silicon gate 4 may be damaged due to the high temperature.
The characteristics of the FET may change, or the alloying reaction between the first-layer metal wiring 5 and the source/drain region 3 formed on a part of the silicon substrate 1 may progress and destroy the source/drain junction. There is a problem.
こうした、レーザー光による能動素子領域の不
必要な昇温を防止するため、レーザー光のSiO2
膜透過を阻止する一つの方法として、半導体装置
を第２図に示される構造に改良するという考え方
がある。この方法における改良点は、層間絶縁膜
１６，１６′の境界にMo，Ｗ等の高融点金属膜
２０を設けたことである。高融点金属膜２０は、
赤外から波長約3000Å附近の紫外領域にわたつて
70％程度の比較的高い反射率を持つので通常のア
ニールに使用する波長のレーザー光２１を、第２
層領域を構成するSiO2膜７又はシリコン膜８に
照射しても、光は膜７，８及び１６′を透過した
後、高融点金属膜２０の表面で大部分反射され
る。従つて第１層９に達する光エネルギー量は非
常に小さく、温度上昇がおさえられるのである。 In order to prevent unnecessary temperature rise of the active element area due to laser light, SiO 2
One way to prevent membrane permeation is to improve the structure of the semiconductor device as shown in FIG. 2. An improvement in this method is that a high melting point metal film 20 such as Mo or W is provided at the boundary between the interlayer insulating films 16 and 16'. The high melting point metal film 20 is
From infrared to ultraviolet wavelengths around 3000Å
Since it has a relatively high reflectance of about 70%, the laser beam 21 of the wavelength used for normal annealing is
Even when the SiO 2 film 7 or the silicon film 8 constituting the layer region is irradiated, most of the light is reflected by the surface of the high melting point metal film 20 after passing through the films 7, 8 and 16'. Therefore, the amount of light energy reaching the first layer 9 is very small, and the temperature rise can be suppressed.
しかるに、絶縁膜と金属の密着強度は、半導体
と絶縁膜との密着強度と比較して弱い。Mo，Ｗ
等の高融点金属膜２０と、層間絶縁膜１６，１
６′は、温度を1000℃程度にしても、金属とSiO2
との反応による中間層をほとんどつくらずに接触
しており膜の密着強度は膜のはく離が生ずるため
に必要な剪断応力に換算した値で109dyne／cm2の
桁である。一方、絶縁膜１６′、金属膜２０にレ
ーザー光が入射し、１６′，２０が1000℃付近ま
で急激に温度上昇した場合に、膜１６′と膜２０
の熱膨張係数の差によつて１６′，２０の膜界面
に生じる熱歪の応力は109dyne／cm2〜1010dyne／
cm2の間にあり、膜の密着力を越えることがある。
このため、絶縁膜１６′と高融点金属膜２０の界
面ではく離が起こるという欠点がある。層間絶縁
膜１６′の膜厚を厚くしたり、あるいは、２層以
上の多層能動素子領域を構成するために、層間絶
縁膜と高融点金属膜の積層構造をくり返し使用す
ると、レーザー光照射による温度上昇に伴い一つ
の層間絶縁膜一金属膜界面に加わる応力が増々大
きくなり、はく離する確率が増える。 However, the adhesion strength between an insulating film and a metal is weaker than the adhesion strength between a semiconductor and an insulating film. Mo,W
etc., and interlayer insulating films 16 and 1.
6' is metal and SiO 2 even if the temperature is about 1000℃.
The adhesion strength of the film is on the order of 10 9 dyne/cm 2 , which is the value converted to the shear stress required to cause the film to peel. On the other hand, when the laser beam is incident on the insulating film 16' and the metal film 20, and the temperature of the films 16' and 20 rises rapidly to around 1000°C, the film 16' and the metal film 20
The thermal strain stress generated at the film interface between 16' and 20 due to the difference in thermal expansion coefficients is 109 dyne/ cm2 to 1010 dyne/cm2.
cm 2 and may exceed the adhesion of the membrane.
Therefore, there is a drawback that peeling occurs at the interface between the insulating film 16' and the high melting point metal film 20. If the thickness of the interlayer insulating film 16' is increased or if a laminated structure of an interlayer insulating film and a high melting point metal film is used repeatedly to configure a multilayer active element region with two or more layers, the temperature due to laser light irradiation may increase. As the temperature rises, the stress applied to the interlayer insulating film-metal film interface increases, and the probability of peeling increases.
以上に述べた様に、絶縁膜と高融点金属膜界面
のはく離現象は、多層構造を有する半導体装置の
製造工程上大きな障害となるものである。 As described above, the peeling phenomenon at the interface between the insulating film and the high melting point metal film is a major hindrance in the manufacturing process of semiconductor devices having a multilayer structure.
本発明は、上記に述べた欠点を除去しようとす
るものであり、以下図面と共に本発明の詳細を説
明明する。 The present invention seeks to eliminate the above-mentioned drawbacks and will be explained in detail below in conjunction with the drawings.
第３図は本発明の内容を説明するための半導体
装置断面図である。第３図において第１，２図と
同一のものには同一番号を付している。この半導
体装置における層間絶縁膜部の製造方法を説明す
ると、まず第１層目能動領域９を形成した後、層
間絶縁膜３６を形成する。絶縁膜３６上に膜厚
500〜1000Åの薄いTi４０を被着する。次に第２
の層間絶縁膜３６′をTi膜４０上に形成した後、
第２層目の能動素子を形成すべきシリコン膜３８
及び素子分離用絶縁膜３７を選択的に形成する。
最後に、レーザー光４２を照射して、膜３８を単
結晶化する。 FIG. 3 is a cross-sectional view of a semiconductor device for explaining the content of the present invention. In FIG. 3, the same parts as in FIGS. 1 and 2 are given the same numbers. To explain the method of manufacturing the interlayer insulating film portion in this semiconductor device, first, the first layer active region 9 is formed, and then the interlayer insulating film 36 is formed. Film thickness on the insulating film 36
Deposit a thin Ti40 layer of 500-1000 Å. Then the second
After forming the interlayer insulating film 36' on the Ti film 40,
Silicon film 38 where the second layer of active elements is to be formed
Then, an element isolation insulating film 37 is selectively formed.
Finally, the film 38 is made into a single crystal by irradiation with laser light 42.
以上に説明した本発明における製造工程で、第
１，２図と異なる点は、層間絶縁膜３６，３６′
の中間に存在する金属として、Mo，Ｗ等の高融
点金属の代わりにTiを用いることである。Tiは、
融点1668±10℃で高温の熱処理に耐える。また、
TiはMo，Ｗと同じく光に対する反射率が大きい
からレーザー光照射による下層能動素子領域の温
度上昇を防ぐ。しかもTiはSiO2膜と500℃程度の
温度で反応し、TiとSiO2との相平衡に基くTiの
酸化層からなる転移層を形成するという性質を持
つている。従つて、第３図の半導体装置の製造工
程においてレーザー光４２を照射すると、膜３
６′，４０の温度が、500℃程度は上昇するから、
膜３６，３６′の境界にTi４０を含む転移層４１
が形成され、膜３６とTi４０の密着強度が著し
く増加する。第３図の例では、シリコン膜８のレ
ーザー照射工程を同時に、TiとSiO2との転移層
形成に利用できるという利点があるが、第２の層
間絶縁膜３６′を形成した後、転移層形成だけを
目的として膜３６′の上からレーザー光照射又は
通常の熱処理を行なつてもよい。 In the manufacturing process of the present invention explained above, the difference from FIGS. 1 and 2 is that the interlayer insulating films 36, 36'
The idea is to use Ti instead of high melting point metals such as Mo and W as the metal that exists between the two. Ti is
It has a melting point of 1668±10℃ and can withstand high temperature heat treatment. Also,
Like Mo and W, Ti has a high reflectance to light, so it prevents temperature rise in the lower active element region due to laser beam irradiation. Moreover, Ti has the property of reacting with the SiO 2 film at a temperature of about 500°C, forming a transition layer consisting of an oxidized layer of Ti based on the phase equilibrium between Ti and SiO 2 . Therefore, when the laser beam 42 is irradiated in the manufacturing process of the semiconductor device shown in FIG.
Since the temperature at 6', 40 rises by about 500℃,
A transition layer 41 containing Ti 40 at the boundary between the films 36 and 36'
is formed, and the adhesion strength between the film 36 and the Ti 40 increases significantly. The example shown in FIG. 3 has the advantage that the laser irradiation process of the silicon film 8 can be used to form a transition layer between Ti and SiO 2 at the same time, but after forming the second interlayer insulating film 36', the transition layer is Laser light irradiation or conventional heat treatment may be performed on the film 36' for the sole purpose of formation.
なお、第３図において、第１層と第２層の電気
的接続は金属膜４０、層間絶縁膜３６，３６′の
一部を開口し、この開口部に金属又は半導体を埋
込めばよい。 In FIG. 3, electrical connection between the first layer and the second layer can be achieved by opening a portion of the metal film 40 and the interlayer insulating films 36, 36', and filling the opening with a metal or semiconductor.
以上の様に本発明では、多層構造を有する半導
体装置において層間絶縁膜の中間に反射率の高い
金属膜が設けられているので、レーザー光照射時
に光エネルギーが反射されて下層能動素子領域に
おいて素子特性の劣化、電極と半導体基板の反応
による接合破壊が生じない。さらに、金属膜とし
て、SiO2膜と容易に反応し転移層を形成するTi
等を用いるので、SiO2膜と金属との密着強度が
大きく、瞬時熱処理時に大きい応力が生じてもは
く離がないという特徴をもつている。この様に本
発明は多層構造の能動素子領域をもつ半導体装置
の製造にその効果を発揮するものである。 As described above, in the present invention, a metal film with high reflectance is provided between the interlayer insulating films in a semiconductor device having a multilayer structure. No deterioration of characteristics or bond breakdown due to reaction between the electrode and the semiconductor substrate. Furthermore, as a metal film, Ti, which easily reacts with the SiO 2 film and forms a transition layer, is used.
etc., the adhesion strength between the SiO 2 film and the metal is high, and it has the characteristic that it does not peel off even if large stress is generated during instantaneous heat treatment. In this way, the present invention exhibits its effects in manufacturing a semiconductor device having an active element region having a multilayer structure.
第１図および第２図は従来の方法で製造した多
層の能動素子領域をもつ半導体装置の断面図、第
３図は本発明の一実施例の方法で製造した多層の
能動素子領域をもつ半導体装置の断面図である。
１……シリコン基板、９……第一層目の能動素
子領域、２０……Mo，Ｗ等の高融点金属膜、３
６，３６′……層間絶縁膜SiO2、７，１７，３７
……第２層目領域のSiO2、４０……Ti膜、４１
……SiO2膜３６，３６′とTi膜４０の間の転移
層、４２……レーザー光。
1 and 2 are cross-sectional views of a semiconductor device having a multilayer active device region manufactured by a conventional method, and FIG. 3 is a cross-sectional view of a semiconductor device having a multilayer active device region manufactured by a method according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the device. 1...Silicon substrate, 9...First layer active element region, 20...High melting point metal film such as Mo, W, etc., 3
6, 36'... Interlayer insulating film SiO 2 , 7, 17, 37
...SiO 2 in the second layer region, 40...Ti film, 41
...transition layer between the SiO 2 films 36, 36' and the Ti film 40, 42...laser light.
Claims (1)
を被着する工程と、前記第１の層間SiO2膜の上
にTi膜を形成し、このTi膜上に第２の層間SiO2
膜を被着する工程と、前記第２の層間SiO2膜上
に第２の半導体素子形成用膜を形成し、この形成
用膜にレーザ光を照射し、前記SiO2膜とTi膜と
を反応させる工程とを備えたことを特徴とする半
導体装置の製造方法。1 A step of depositing a first interlayer SiO 2 film on the first semiconductor element layer, forming a Ti film on the first interlayer SiO 2 film, and depositing a second interlayer SiO 2 film on the Ti film. 2
A step of depositing a film, forming a second semiconductor element forming film on the second interlayer SiO 2 film, and irradiating this forming film with laser light to separate the SiO 2 film and the Ti film. A method for manufacturing a semiconductor device, comprising a step of causing a reaction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135726A JPS5837927A (en) | 1981-08-28 | 1981-08-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56135726A JPS5837927A (en) | 1981-08-28 | 1981-08-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5837927A JPS5837927A (en) | 1983-03-05 |
| JPH0221144B2 true JPH0221144B2 (en) | 1990-05-11 |
Family
ID=15158441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56135726A Granted JPS5837927A (en) | 1981-08-28 | 1981-08-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837927A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6074463A (en) * | 1983-09-29 | 1985-04-26 | Fujitsu Ltd | Trimming method for resistance film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56111213A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Preparation of thin film semiconductor device |
| JPS56126956A (en) * | 1980-03-11 | 1981-10-05 | Fujitsu Ltd | Semiconductor device |
-
1981
- 1981-08-28 JP JP56135726A patent/JPS5837927A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56111213A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Preparation of thin film semiconductor device |
| JPS56126956A (en) * | 1980-03-11 | 1981-10-05 | Fujitsu Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5837927A (en) | 1983-03-05 |
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