JPH02206292A - Code converting circuit for variable length code - Google Patents

Abstract

PURPOSE:To make unnecessary the effective bits of a variable length code as an input and to simplify a circuit by adding more than one discriminatable additional bits after the effective data of a variable length encoded word at a different bit length, making the lengths fixed, and detecting and eliminating the additional bits from the fixed length encoded word. CONSTITUTION:When (n)-bit variable length codes are inputted from variable length code input terminals DI1 to DIn, the bits of an input shift register 14 are shifted by one to a high-order side at the timing of a clock 2. A comparing circuit 15 inputs one discriminatable additional bit or more other than the highest-order bit of the input shift register 14 in units of a clock, and the circuit 15 detects a pattern. Further an output shift register 17 shifts the bits by one to the high-order side, and simultaneously inputs one bit outputted from the input shift register 14 to the lowest-order bit. A counter 16 counts the bits until the data of the output shift register 17 amount to the (n) bits, and when they amount to the (n) bits, the data of the output shift register 17 are outputted from output terminals DO1 DOn in parallel.

Description

Detailed description of the invention (Technical field to which the invention pertains) The present invention relates to a code conversion circuit for variable length codes of television signals.8 (Prior art) As a code conversion circuit for variable length codes of television signals. ,
- An example of a boat fishing configuration is shown in Figure 3. In the same figure, DII
, DI2...DIn are variable length code input terminals, BII,
Br3...BIm is an input terminal for the effective number of bits of a variable length code, 1 is a rotation circuit, 2 is a first flip-flop circuit, 3 is a switching circuit, 4 is a second flip-flop circuit, and 5 is a third flip-flop circuit. 6 is a control circuit, D
ol, 002...D On is an output terminal.

Briefly describing the operation of this code conversion circuit, n-bit variable length codes are input in parallel to the rotate circuit 1 from the variable length code input terminals DII to DIn. Rotito circuit 1
has a function of rotating data by an arbitrary number of bits within n bits and outputting the data in parallel. The number of shifts in the rotate circuit 1 is controlled by the control circuit 6 based on information input to the control circuit 6 from the effective bit number input terminals B11 to BIm of the variable length code. The output signal of the rotate circuit 1 is transmitted to a first flip-flop circuit 2,
It is simultaneously written to the second flip-flop circuit via the switching circuit 3. In this case, if there is unwritten data that protrudes from n bits during the previous data write, it is transferred from the first flip-flop circuit 2 via the switching circuit 3 to the second flip-flop circuit 2 by adding it to the beginning of the parallel data. Written into circuit 4.

In this way, when the parallel data written to the second flip-flop circuit 4 does not reach n bits, the first bit of the primary variable length code data is written to the second flip-flop circuit 4. The data is converted to be located at the end of the data and written to the second flip-flop circuit 4.

In this way, when the number of data written to the second flip-flop circuit 4 reaches n bits, the content is written to the third flip-flop circuit 5, and at a predetermined timing, the data is output to the output terminal. Dot~
Output from Don.

This code conversion circuit requires two pieces of data: a variable length code and the number of effective bits of the variable length code.

There is a drawback that the circuit has a complicated configuration as shown in FIG.

(Objective of the Invention) It is an object of the present invention to solve the above conventional drawbacks and to simplify one circuit configuration by eliminating the need for the effective number of bits of a variable length code as an input.

(Structure of the Invention) (Characteristics of the Invention and Differences from the Prior Art) In order to achieve the above object, the present invention assigns short code words and long code words to events with high and low occurrence frequencies, so that the average In a variable-length encoding circuit that shortens codewords, a fixed-length codeword is input by adding one or more distinguishable additional bits after the valid data of a variable-length codeword with a different bit length. , the additional bits are detected and removed from the fixed-length code word, and only the variable-length code is converted into a continuous bit string and output.

In the conventional technology, when performing code conversion, two pieces of data are required: the variable length code and the effective number of bits of the variable length code.One advantage of the present invention is that the effective number of bits of the variable length code is not required as input. different.

(Example) FIG. 1 shows a circuit diagram according to an embodiment of the present invention.

In the figure, DII, DI2...DIn are variable length code input terminals, 10 is a clock terminal, 11 is a reset terminal, 12 is an input request terminal, 13 is a delay circuit, 14 is an input shift register, 15 is a comparison circuit, 16 is a counter, 17
is an output shift register, 18 is an output request terminal, 001,
002...Don is an output terminal.

Next, to explain the operation, when this circuit starts operating, a reset pulse is input to the reset terminal 11, and all bits of the input shift register 14 and output register 17 are set to 0.
" is cleared. At the same time, the counter value of the counter 16 is cleared to "0".

This circuit operates based on the clock input from the clock terminal 10.

Figure 2 shows the clock units ((1) to (9)) of the input shift register 14 and output shift register 17 when the bit width of the variable-length code input terminals DII to DIn is 8 bits.
) data (a□~a,,b1~b2.c1~as)
are shown at Sl (input) and 82 (output), respectively.

Now, when n-bit variable length codes are input in parallel to the input shift register 14 from the variable length code input terminals DII to DIn, the bits of the input shift register 14 are changed to the clock (2) shown in FIG. Shift one bit to the upper side at the appropriate timing.

In the comparison circuit 15, the input is shifted in clock units? .

Input one or more distinguishable additional bits excluding the most significant bit of the register 14, and in the inversion, the most significant bit of the input bit string is II I 11, and "0" is added to the subsequent least significant bits. The comparison circuit 15 detects the pattern. If this pattern is detected, the comparison circuit 15 outputs an input request pulse to the input request terminal 12 and the delay circuit 13 at the timing of clocks (4) and (6) shown in FIG. Shows the next clock (
At the timings 5) and (7), the delay circuit 13 outputs an input request pulse to the input shift register 14, and at the same time inputs variable length codes to the input shift register 14 from the variable length encoding terminals DII to DIn.

The output shift register 17 shifts one bit to the higher order side, and at the same time inputs the one bit output from the input shift register 14 to the least significant bit.

The counter 16 is configured so that the data in the output shift register 17 is n.
When the number of n bits is reached, a request pulse is output from the output request terminal 18 at the timing of clock (9) shown in FIG. 2, and the data of the output shift register 17 is transferred to the output terminal D○. Output in parallel from 1 to Don.

As the additional bit mentioned above, “
07+ (see FIG. 2), the reverse is also possible without any problem. Furthermore, the same effect can be obtained using any other distinguishable additional bit.

(Effects of the Invention) As described above, according to the present invention, the effective number of bits of a variable length code is not required as an input unlike in the conventional case, and therefore the route can be configured easily. Further, it is also easy to configure the code conversion circuit using a microprocessor (MPU) or a digital signal processor (DSP).

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a code conversion circuit as an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the code conversion circuit of FIG. 1, and FIG.
The figure is a circuit diagram of a conventional code conversion circuit. DII~DIn...Variable length code input terminal, 001~
Don...Output terminal, 10...Clock terminal, 1
1... Reset terminal, 12... Input request terminal, 1
3...Delay circuit, 14...Input shift register, 1
5... Comparison circuit, 16... Counter, 17... Output shift register, 18... Output request terminal. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] In a variable-length encoding circuit that shortens the average codeword by assigning short and long codewords to events with high and low occurrence frequencies, respectively, after valid data of variable-length codewords with different bit lengths, A code word made into a fixed length by adding one or more distinguishable additional bits is input, and the additional bits are detected and removed from this fixed length code word, and only a variable length code is made into a continuous bit string. A code conversion circuit for a variable length code, which converts and outputs a variable length code.