JPH02205783A - Apparatus for evaluating software error - Google Patents

Abstract

PURPOSE:To efficiently evaluate the software error of a mode easy to generate when a signal is changed over by mounting a plurality of delay circuits and a signal forming circuit calculating the exclusive OR of the output signals of said delay circuits and an operation effective signal. CONSTITUTION:The test signal A on a signal line 101 is distributed to be inputted to delay circuits 11-13 and the control signals T1...Tn on a signal line 104 are also respectively inputted to the circuits 11-13. By this mechanism, the input signals A inputted to the circuits 11-13 are outputted from said circuits 11-13 with the delay quantities respectively determined by the signals T1...Tn. These output signals are inputted to a signal forming circuit 2 and the operation effective signal V effective for writing/reading operation on a signal line 103 is also inputted to said circuit 2. In the circuit 2, the exclusive OR of these input signals is calculated to form an output signal B which is, in turn, outputted to a signal line 102. The output signal B on the signal line 102 becomes a test driver signal to be inputted to an LSI to be evaluated. By this method, a test signal waveform having many change-over points within one cycle is given to the LSI and the software error of the LSI can be evaluated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a soft error evaluation method, and particularly to an output waveform output from a tester within one cycle.

(Prior Art) Conventionally, in software error evaluation methods, the signals output from the tester within one cycle are either switched from the signals of the previous cycle or are not valid for operations such as writing/succession. t or from a valid value.

(Problems to be Solved by the Invention) In the conventional software error evaluation device described above, the number of signal switchings generated from the tester within one signal cycle is small, so the number of signal switchings within a unit time is also low for the LSI being evaluated. Less is.

Therefore, there is a drawback that mode software errors that tend to occur when switching signals cannot be efficiently evaluated.

An object of the present invention is to eliminate the above drawback by combining several signal switching points t-% within one signal cycle, and to efficiently evaluate mode software errors that are likely to occur during signal switching. An object of the present invention is to provide a software error evaluation method configured as follows.

(Means for Solving the Problems) The software error evaluation method according to the present invention is designed to include a plurality of delay circuits and a signal generation circuit.

The multiple delay circuits are for providing multiple amounts of delay to the tester cycle.

The signal generation circuit is for determining the exclusive OR of the outputs of the plurality of delay circuits and the operation enable signal.

(!l! Condolences) Next, the present invention will be explained with reference to the oral side.

FIG. 1 is a block diagram showing an embodiment of a software error evaluation method according to the present invention.

In FIG. 1, 11 to 13 are first, second, and nth delay circuits, respectively, and 2 is a signal generating circuit. Further, the signal line 101 carries a test signal A that provides the pulse width of the tester cycle signal.

The signal line 102 carries the test output B=i, the signal line 103 carries the operation valid signal V having a valid value for operation, and the signal line 104 carries the delay amount T 1 * T 2 m...-,,T
It is used to carry n control signals.

Test signal A on signal line 101 is distributed to delay circuit 1
1 to 13 and a control signal Ts on the signal line 104,
Tt...Tn are also input to delay circuits 11 to 13, respectively. As a result, the test signals A input to the delay circuits 11 to 13 are Tt, Tt...Tn, respectively.
Delay circuits 11 to 13 with a delay amount determined by
is output from.

The output signals outputted from the delay circuits 11 to 13 are input to the signal generation circuit 2, and an operation enable signal Vt effective for the write/continue operation on the signal line 103 is input. The signal generation circuit 2 calculates the exclusive OR of the above input signals to generate the output signal B, and then generates the signal 1j! This is output on 102.

The output signal B on the signal line 102 becomes a tester driver signal and is input to the LSI to be evaluated.

Thereby, a test signal waveform having many switching points within one cycle can be provided to the L8IK to evaluate software errors in the LSI.

(Effects of the Invention) As explained above, the present invention is achieved by reducing several signal switching points within one cycle.

Since many types of signals can be applied to the LSI to be evaluated within a unit time, it is possible to efficiently evaluate software errors in modes that tend to occur when switching signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a software evaluation method according to the present invention. 11-13-...Delay circuit 2...Signal creation circuit 101-104...Signal line patent applicant NEC Corporation

Claims (1)

[Claims] It is characterized by being configured to include a plurality of delay circuits for giving a plurality of delay amounts to a tester cycle, and a signal generation circuit for obtaining an exclusive OR of the outputs of the plurality of delay circuits and an operation enable signal. Software error evaluation method.