JPH05126912A - Pattern address generating device - Google Patents

Abstract

PURPOSE:To enable an IC tester to generate a pattern address at a high speed. CONSTITUTION:A sequencer 12 and microprogram memory 13 generate an initial address for generating continuous pattern addresses S2 and control instruction S3 for designating a repetitive number. An address counter 14 and repeat counter 15 generate a series of continuous pattern addresses S2 in accordance with the instruction S3. Namely, the address counter 14 increments the pattern addresses S2 at every rate clock pulse S1 and the repeat counter 15 counts the repetitive number by performing subtraction. When the repetitive number is reached, the counter 15 outputs a zero signal S5 and operates the sequencer 12 by sending the rate clock pulse S1 to the sequencer 12 as a sequencer clock S6 through an AND circuit 16. By operating the sequencer 12 at a low speed while the counters 14 and 15 operation at high speeds in such way, a pattern address can be generated at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating high-speed pattern addresses in applications such as IC testers.

[0002]

2. Description of the Related Art Conventionally, a pattern address generator used in an IC tester sequentially generates a series of pattern addresses for each test rate and applies the pattern addresses to a pattern memory that stores the test patterns to generate the test patterns. Is to test the device. At this time, the generation speed of the test pattern is almost determined by the generation speed of the pattern address. Therefore, it is desired to increase the speed of the pattern address generation device when testing a semiconductor.

FIG. 3 is a block diagram showing the structure of a conventional pattern address generator. In FIG. 3, reference numeral 21 is a rate generator, which generates a rate clock pulse S1 having various time intervals for advancing an individual test. Reference numeral 22 is a sequencer, and the signal output every time the late clock pulse S1 output from the rate generator 21 is applied becomes the pattern address S2. Reference numeral 23 is a micro program memory, and the content of the memory address determined by the pattern address S2 becomes a sequencer control instruction S3 that determines the next operation of the sequencer 22.

Next, the operation of the above conventional example will be described. FIG. 4 shows the operation timing of FIG. 3 described above. The rate clock pulse S output from the rate generator 21 is shown in FIG.
1 shows the timing of the pattern address S2 output from the sequencer 22 and the sequencer control instruction S3 output from the microprogram memory 23.

The late clock pulse S1 output from the late generator 21 first outputs one late clock pulse 1, and then 100 ns later, outputs a late clock pulse 2. Further, the late clock pulse 3 and the late clock pulse 4 are output every 100 ns. Then, after 70 ns, the late clock pulse 5 is output. Further, the late clock pulse 6 and the late clock pulse 7 are output every 70 ns.

The pattern address S2 output from the sequencer 22 is initially set to 0, and a sequencer control instruction S3 for controlling the sequencer is stored in the microprogram memory 23 in advance. Pattern address S
Since the contents of address 0 of the microprogram memory 23 where 2 corresponds to 0 are address increments, the pattern address S2 output by the sequencer 22 is changed to 1 by the late clock pulse 1.

Next, the content of the address 1 of the microprogram memory 23 is also an address increment, so that the pattern address S2 changes to 2 by the late clock pulse 2. Similarly, since the contents of the address 2 of the micro program memory 23 are also address increments, the pattern address S2 changes to 3 by the late clock pulse 3.
Next, the contents of address 3 of the microprogram memory 23 outputs an instruction to the sequencer 22 to jump the pattern address S2 to 10, so that the pattern clock S4 changes to 10 by the late clock pulse 4.

Next, since the contents of the address 10 of the microprogram memory 23 are address increments, the pattern address S2 is changed to 11 by the late clock pulse 5. Similarly, since the contents of the address 11 of the micro program memory 23 are address increments, the pattern address S2 is changed to 12 by the late clock pulse 6. Similarly, since the contents of address 12 of the microprogram memory 23 are address increments, the pattern address S2 is changed to 13 by the late clock pulse 7. Thus, the pattern address including the jump of the pattern address S2 can be generated.

[0009]

However, in the above-mentioned conventional pattern address generator, the upper limit of the pattern address generation speed is determined by the operation speed of the sequencer. However, in testing a semiconductor, the speed of the semiconductor is remarkably improved, and therefore a higher test rate is desired.

The present invention solves such a conventional problem, and an object thereof is to obtain a high-speed pattern address with a simple circuit.

[0011]

The present invention comprises an address counter and a repeat counter that can be controlled by the output of a microprogram, generates continuous pattern addresses by the output of the address counter, and generates a continuous pattern by the repeat counter. By counting the number of times and transferring the late clock pulse to the sequencer when the specified number of times is generated, the operation speed of the sequencer can be made lower than the generation speed of the pattern address.

[0012]

According to the present invention, a series of high-speed pattern addresses are generated by the operation of the counter and the sequencer is operated at a low speed, whereby a high-speed pattern address can be obtained with a simple circuit.

[0013]

1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 11 is a rate generator,
A late clock pulse S1 is generated having various time intervals for advancing the individual tests. Reference numeral 12 is a sequencer, and the signal output every time the sequencer clock S6 is applied becomes the memory address S4. Reference numeral 13 denotes a micro program memory, and the content of the micro program memory address determined by the memory address S4 determines the next operation of the sequencer 12 and other components as a control instruction S3. Reference numeral 14 denotes an address counter, which operates according to the control command S3 output from the microprogram memory 13 at the trailing edge of the late clock pulse S1, and this output becomes the pattern address S2. 15 is a repeat counter,
It operates at the trailing edge of the late clock pulse S1 according to the control command S3 output from the micro program memory 13, and is normally decremented by 1 every time the pattern address S2 is generated, and when it becomes zero, a zero signal S5 is output. An AND circuit 16 transfers the late clock pulse S1 to the sequencer 12 as the sequencer clock S6 when the zero signal S5 output from the repeat counter 15 is 1.

Next, the operation of the above embodiment will be described. FIG. 2 shows the operation timing of FIG.
Late clock pulse S1 output from the rate generator 11,
The memory address S4 output by the sequencer 12, the control instruction S3 output by the microprogram memory 13, the pattern address S2 output by the address counter 14, the value S7 of the repeat counter 15, and the zero signal S output by this.
5 shows the timing of the sequencer clock S6 output from the AND circuit 16.

The late clock pulse S1 output from the late generator 11 first outputs one late clock pulse 1 as shown, and then outputs the late clock pulse 2 after 20 ns. Late clock pulse 3 every 20ns,
The late clock pulse 4 is output. Then, after 15 ns, the late clock pulse 5 is output. Further, the late clock pulse 6 and the late clock pulse 7 are output every 15 ns.

Memory address S output from the sequencer 12
4, the pattern address S2 of the address counter 14 and the value S7 of the repeat counter 15 are initially set to 0, and the microprogram memory 13 stores a control command S3 for controlling a sequencer or the like in advance.

Memory address S output from the sequencer 12
Although 4 is initially 0, the memory address is added to the microprogram memory 13, and the instruction to set the address counter 14 which is the content of the memory address 0 to 1 and increment it twice is read. According to this instruction, 1 is set in the address counter 14 by the late clock pulse 1, and a value of 2 is set in the repeat counter 15.

At the same time, a zero signal S5 is sent to the AND circuit 16.
The sequencer clock S6 is generated by the late clock pulse 1 for 1 because the memory address S4 output from the sequencer 12 changes to 1. After that, the address counter 14 is incremented by 1 and the repeat counter 15 is decremented by 1 for each late clock pulse S1. That is, the pattern address S2 becomes 2 by the late clock pulse 2 and the pattern address S2 becomes 3 by the late clock pulse 3.

On the other hand, the repeat counter 15 is sequentially decremented,
When it becomes zero due to the late clock pulse 3, the zero signal S
5 is output as 1. When the zero signal S5 is 1, the late clock pulse 4 is applied to the sequencer 12 as the sequencer clock S6 through the AND circuit 16, and the instruction stored in the address 1 of the microprogram memory 13 sets the address counter 14 to 10. The instruction to increment three times is read.

Late clock pulse 4 according to this instruction
Causes the address counter 14 to be set to 10 and the repeat counter 15 to be set to a value of 3. After that, the address counter 14 is incremented by 1 and the repeat counter 15 is decremented by 1 for each late clock pulse S1. That is, the pattern address S2 becomes 11 by the late clock pulse 5, and the pattern address S2 becomes 11 by the late clock pulse 6.
2 becomes 12 and the pattern clock S2 becomes 13 by the late clock pulse 7. The pattern address can be generated in the same manner as the above-mentioned conventional example.

[0021]

As described above, in the pattern address generator of the present invention, a series of pattern addresses is generated by a counter, and the sequencer is operated only when the addresses are not continuous. Can be generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional pattern address generator.

FIG. 4 is a diagram showing a timing chart of FIG.

[Explanation of symbols]

11 ... Rate generator, 12 ... Sequencer, 13 ... Micro program memory, 14 ... Address counter, 15 ... Repeat counter, 16 ... AND circuit.

Claims (1)

[Claims] 1. A sequencer, an address counter controlled by the sequencer, and a repeat counter, wherein the number of repetitive operations of the address counter by a clock is counted by the repeat counter, and when a predetermined number designated by the repeat counter is counted, A pattern address generation device characterized in that a clock is sent to the sequencer to operate the sequencer.