JPH02205781A - Defective scanning path diagnostic circuit - Google Patents

Abstract

PURPOSE:To judge which LSI among N scanning path built-in LSIs gets out of order by selecting the scanning output of the LSI of the final stage and that of each LSI by the indication of a scanning mode. CONSTITUTION:The scanning path input and output signal terminals of N scanning path built-in LSIs are connected in series and the output of a selection circuit selecting the scanning output of the LSI of the final stage and that of each LSI on the basis of a selection signal by the indication of a scanning mode is set to a scanning path diagnostic signal. At the time of trouble, since the LSI scanning outputs 2 of the scanning path built-in LSI 5-8 are connected to the input signal of the selection circuit 10, when the selection signal 12 is set so as to select the LSIs 5-8 in succession, the LSI scanning output signal of the individual scanning path built-in LSI is outputted to a selection scanning output signal 11. This signal 11 is observed and the scanning built-in LSI of the foremost stage wherein an output signal, wherein the signal 11 is fixed to logical '0' to '1', is observed is judged to be out of order.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a defect diagnosis circuit for an electronic circuit, and more specifically, to a fault diagnosis circuit for an electronic circuit.
The present invention relates to a scan path failure diagnostic circuit that takes into account the ability to easily determine whether an SI has failed.

(Prior Art) FIG. 2 shows a conventional example of an electronic circuit using N LaIs with built-in scans.

Scan input signal (8
I) The scan input signal 11 is input to the terminal 11',
The scan output signal terminal 12' is connected to the scan input signal terminal 11' of the next stage built-in scan LSI 16. Similarly connected sequentially, the final stage scan built-in LS
A scan output signal terminal 12' of 118 serves as a scan output signal to the outside.

The data output terminal DO of each L8115.16.17 and 18 is connected to a combinational circuit to which the input group and output group are connected.

To perform diagnosis, the scan mode operation is set to diagnostic mode and a scan signal is input.

Timing is determined in each LSI according to the scan clock signal 14, and a scan output signal 12 indicating the result is output from the final stage LSI 18.

By observing this scan output signal, it is possible to diagnose whether the electronic circuit is good or bad.

(Problem to be Solved by the Invention) The above-mentioned conventional electronic circuit using N LSIs with built-in scan outputs logic "0" and "1" as the scan input signal 11.
L8115 with built-in scan
~18 LSI is logic 10" or logic"
11'', the scan output signal 12 of the final stage scan 11:LS118 becomes logic 10.
``or logic'' is fixed at 11m, so it can be diagnosed that this electronic circuit is defective.

However, it is impossible to diagnose which LSI is faulty among the LSIs used in an electronic circuit by simply observing the scan output signal 12;
LS115-18 with built-in scan is used to point out SI.
Since it is necessary to carefully observe each scan output signal 12', there is a drawback that fault diagnosis takes time.

The purpose of the present invention is to
To provide a scan path failure diagnostic circuit tube that can easily determine which LSI has failed.

(Ninth Means for Solving the Problems) In order to achieve the above object, the scan path failure diagnosis circuit according to the present invention is a scan path failure diagnosis circuit of an electronic circuit in which IItLs engineering in the scan canvas is used. 1 on the bus! Connect the scan output signal terminals of the LSI to the scan input signal terminals of the next-stage scanvase built-in LSI in sequence, and connect the @LSI's x
Assuming that the $ scan power signal is the first external observation signal, a selection circuit is provided which inputs the N scan canvases F'3ffiL S I O scan output signal terminals and selects and outputs one of them using a selection signal. and the selection circuit output is configured to be a second external observation signal.

(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a scan path failure diagnosis circuit according to the present invention. When scanning the scan built-in LSIs 5 to 8, the scan mode signal 3 is designated as scan mode.

Next, the logic ``'0'''1''t is obtained from the scan input signal holder l.
”Input a repeating scan signal.

The scan input is latched with scan clock signal 4,
The signal is sequentially propagated to the scan built-in LSIs 5 to 8, and the final stage LSI 5 repeatedly outputs the same logic @0''1'' as the scan input signal 1 as the scan output signal 2 after N clocks.

The above is the output when this electronic circuit is operating normally. During the above operation, one of the LSIs in RL8 in the scan 5 to 8 is stuck at logic "'0" or Fi logic "'1". In the event of a failure, the scan output signal 2 is fixed at logic ``'O'' or logic ``1'' as in conventional electronic circuits.

In the present invention, within the above-mentioned failure scan, L of 1LsI5 to 8
Since the SI scan output 2' is connected to the input signal of the selection circuit 100, the song selection signal 12t-zLs in the scan is
When rs to 8t- is set to be selected, the LSI scan output signal of each LSI with a built-in scan is output as the selection scan output signal (second external observation signal) 11.

This signal 1lt- is observed, and the 1 selection scan output signal 11 is fixed at m"o", i, or 11". It can be determined that the scan built-in LSI at the previous stage is faulty.

(Effects of the Invention) As explained above, the present invention provides a
Connect the scan input and output signals of IELSI in series, select the scan output of Li3N with the highest RR by specifying the scan mode, and use the selection signal to select the scan output of each L81°, and use the selection output as the scan path diagnostic signal. This configuration has the advantage that it is possible to easily determine which LSI has a defective scan canvas.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a scan path failure diagnosis circuit according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional scan path failure diagnosis circuit. 1.11...Scan input signal 2.12...Scan input signal 3.13...Scan mode signal 4.14...Scan clock signal 5-8...Scan built-in LSI 9.19 ... Combinational circuit 10 ... Selection circuit 11 ... Selection scan output signal 12 ... Selection signal

Claims (1)

[Claims] In a scan path defect diagnostic circuit for an electronic circuit using N LSIs with built-in scan paths, the scan output signal terminal of each LSI with built-in scan paths that performs scan mode operation is used as the scan input of the next LSI with built-in scan paths. The scan output signal of the LSI with a built-in scan path at the final stage is connected to the signal terminals sequentially to be used as a first external observation signal, and the scan output signal terminals of the N LSIs with a built-in scan path are input, and one of them is selected. 1. A scan path failure diagnostic circuit, comprising: a selection circuit that selects and outputs a signal; and the output of the selection circuit is configured to be a second external observation signal.