JPH02205340A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02205340A
JPH02205340A JP2517289A JP2517289A JPH02205340A JP H02205340 A JPH02205340 A JP H02205340A JP 2517289 A JP2517289 A JP 2517289A JP 2517289 A JP2517289 A JP 2517289A JP H02205340 A JPH02205340 A JP H02205340A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
oxide film
semiconductor substrate
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2517289A
Other languages
Japanese (ja)
Other versions
JP2876612B2 (en
Inventor
Hidetoshi Nakada
中田 英俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2517289A priority Critical patent/JP2876612B2/en
Publication of JPH02205340A publication Critical patent/JPH02205340A/en
Application granted granted Critical
Publication of JP2876612B2 publication Critical patent/JP2876612B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To prevent the leaving of strain in a semiconductor substrate by forming a polycrystalline silicon film and a nitride film onto the semiconductor substrate in an element region, conducting the thermal oxidation of a silicon layer and the formation of an element isolation oxide film and removing the nitride film and the polycrystalline silicon film when the silicon layer buried in a trench is thermally oxidized and the element isolation oxide film is shaped. CONSTITUTION:A first oxide film 2, a first polycrystalline silicon film 3, a nitride film 4 and a second polycrystalline silicon film 5 are shaped successively onto a semiconductor substrate 1, and a trench is shaped. A polycrystalline silicon film 9 for burying and the second polycrystalline silicon film 5 are etched back, the silicon layer 9 is left only in the trench, and an element isolation oxide film 10 is formed through thermal oxidation while using the nitride film 4 as a mask. Stress generated in the process is applied to the first oxide film 2, the first polycrystalline silicon film 3 and the nitride film 4, but it hardly has an effect on the substrate 1. Accordingly, strain 11 is generated in the first polycrystalline silicon film 3, but it is not generated in the substrate 1.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は半導体装置の製造方法に関し、特に、素子分離
酸化膜を備えた半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device provided with an element isolation oxide film.

[従来の技術] 従来のこの種半導体装置の製造方法を、第4図(a)〜
(f)を参照して説明する。まず、第4図(a)に示す
ように、半導体基板1上に第1の酸化WA2および窒化
M4を順次形成した後に、選択的に形成したフォトレジ
スト6をマスクにして窒化膜4、第1の酸化膜2および
半導体基板1を順次エツチングして溝を形成する。続い
て、第4図(b)に示すように、熱酸化法により、溝内
壁に第2の酸化M!A8を形成する0次に、第4図(C
)に示すように、全面に埋め込み用多結晶シリコン層9
を形成して溝を埋め込み、次いで、第4図(d)に示す
ように、埋め込み用多結晶シリコン層9をエッチバック
して溝にのみこれを残す、続いて、第4図(e)に示す
ように、窒化膜4をマスフとして、埋め込み用多結晶シ
リコン層9を熱酸化してその上表面に素子分離酸化膜1
0を形成した後に、第4図(f)に示すように、窒化膜
4を除去する。
[Prior Art] A conventional method for manufacturing this type of semiconductor device is shown in FIGS. 4(a) to 4(a).
This will be explained with reference to (f). First, as shown in FIG. 4(a), after sequentially forming a first oxide WA2 and a first nitride M4 on a semiconductor substrate 1, a first nitride film 4 and a first nitride film 4 are formed using a selectively formed photoresist 6 as a mask. The oxide film 2 and the semiconductor substrate 1 are sequentially etched to form a groove. Subsequently, as shown in FIG. 4(b), a second oxidation layer M! is applied to the inner wall of the groove by a thermal oxidation method. 4 (C
), a polycrystalline silicon layer 9 for embedding is formed on the entire surface.
Then, as shown in FIG. 4(d), the polycrystalline silicon layer 9 for embedding is etched back to leave it only in the trench.Subsequently, as shown in FIG. 4(e), As shown, the buried polycrystalline silicon layer 9 is thermally oxidized using the nitride film 4 as a mask, and an element isolation oxide film 1 is formed on its upper surface.
After forming 0, the nitride film 4 is removed as shown in FIG. 4(f).

[発明が解決しようとする問題点] 上述した従来の半導体装置の製造方法は、清に埋め込ん
だ多結晶シリコンを熱酸化して素子分離酸化膜を形成す
る時に、素子領域の半導体基板上には酸化膜と窒化膜し
かないので、溝に埋め込んだ多結晶シリコンを熱酸化し
て発生したストレスは素子分離酸化膜周囲の窒化1gI
4、酸化膜2および半導体基板1に直接かかり、半導体
基板1に歪11を生じさせてしまう、その結果、リーク
電流の増大等装置の正常な動作を阻害する現象があられ
れる。
[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method described above, when an element isolation oxide film is formed by thermally oxidizing the buried polycrystalline silicon, the semiconductor substrate in the element region is Since there are only oxide and nitride films, the stress generated by thermal oxidation of the polycrystalline silicon buried in the trench is reduced to 1gI of nitride around the element isolation oxide film.
4. It is directly applied to the oxide film 2 and the semiconductor substrate 1, causing distortion 11 in the semiconductor substrate 1. As a result, phenomena such as an increase in leakage current that inhibit the normal operation of the device occur.

また、溝に埋め込まれた多結晶シリコンは、酸化膜によ
り半導体基板から絶縁されているため、電気的に浮遊状
態となって電位が定まらず、これが装置の誤動作を誘発
する原因となる。
Further, since the polycrystalline silicon buried in the trench is insulated from the semiconductor substrate by an oxide film, it is electrically floating and its potential is not fixed, which causes malfunction of the device.

[問題を解決するための手段] 本発明による半導体装置の製造方法は、一導電型半導体
基板上に多結晶シリコン膜と窒化膜とを順次形成する工
程と、所定の領域の前記窒化膜、前記多結晶シリコン膜
および前記一導電型半導体基板を順次エツチング除去し
て溝を形成する工程と、少なくとも溝内壁部分に酸化膜
を形成する工程と、前記酸化膜を異方性のあるエツチン
グ雰囲気に晒して前記溝の側壁にのみ前記酸化膜を残す
工程と、溝内に埋め込み用シリコン層を形成する工程と
、前記窒化膜をマスクとして前記埋め込み用シリコン層
の露出部を酸化して素子分離酸化膜を形成する工程と、
前記窒化膜および前記多結晶シリコン膜を順次エツチン
グ除去する工程とを有している。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a step of sequentially forming a polycrystalline silicon film and a nitride film on a semiconductor substrate of one conductivity type, A step of sequentially etching away the polycrystalline silicon film and the one conductivity type semiconductor substrate to form a trench, a step of forming an oxide film on at least the inner wall portion of the trench, and a step of exposing the oxide film to an anisotropic etching atmosphere. a step of leaving the oxide film only on the side walls of the trench; a step of forming a buried silicon layer in the trench; and a step of forming an element isolation oxide film by oxidizing the exposed portion of the buried silicon layer using the nitride film as a mask. a step of forming;
and a step of sequentially etching and removing the nitride film and the polycrystalline silicon film.

[実施例] 次に、本発明の実施例について、図面を参照して説明す
る。
[Example] Next, an example of the present invention will be described with reference to the drawings.

第1図(a)〜(h)は、本発明の一実施例の工程順を
示す断面図である。まず、第1図(a>に示すように、
半導体基板1上に第1の酸化膜2(例えば熱酸化法によ
る膜厚200人〜1000人の酸化膜)、第1の多結晶
シリコン膜3(例えば化学的気相成長法による膜厚50
0人〜5000人の多結晶シリコン)、窒化膜4(例え
ば化学的気相成長法による膜厚500人〜5000人の
窒化膜)および第2の多結晶シリコン膜5(例えば化学
的気相成長法による膜厚500人〜5000人の多結晶
シリコン)を順次形成した後に、フォトレジスト6を用
いて選択的に第2の多結晶シリコン膜5、窒化膜4、第
1の多結晶シリコン膜3、第1の酸化M2および半導体
基板1を順次エツチング除去して溝を形成する。
FIGS. 1(a) to 1(h) are cross-sectional views showing the order of steps in an embodiment of the present invention. First, as shown in Figure 1 (a),
On a semiconductor substrate 1, a first oxide film 2 (for example, an oxide film with a thickness of 200 to 1,000 oxides formed by thermal oxidation) and a first polycrystalline silicon film 3 (for example, a 50-millimeter thick oxide film formed by chemical vapor deposition)
0 to 5,000 polycrystalline silicon), a nitride film 4 (for example, a nitride film with a thickness of 500 to 5,000 by chemical vapor deposition), and a second polycrystalline silicon film 5 (for example, by chemical vapor deposition) After sequentially forming polycrystalline silicon films with a thickness of 500 to 5,000 times using a photoresist 6, a second polycrystalline silicon film 5, a nitride film 4, and a first polycrystalline silicon film 3 are selectively formed using a photoresist 6. , the first oxide M2 and the semiconductor substrate 1 are sequentially etched away to form a groove.

続いて、第1図(b)に示すように、全面に第3の多結
晶シリコン膜7(例えば化学的気相成長法による膜厚5
00λ〜2000人の多結晶シリコン)を形成し、次い
で、第1図(c)に示すように、全面を熱酸化して第2
の酸化膜8(例えば膜厚1000人〜6000人の酸化
膜)を形成する。続いて、第1図(d)に示すように、
全面を異方性のあるエツチング雰囲気に晒して溝の側壁
にのみ第2の酸化JII8を残す、この時のエツチング
は、第2の酸化膜8が第2の多結晶シリコン膜5および
第1の窒化膜4の側壁に残らないようにオーバーにする
Subsequently, as shown in FIG. 1(b), a third polycrystalline silicon film 7 (for example, a film with a thickness of 5 cm by chemical vapor deposition) is deposited on the entire surface.
00λ~2000 polycrystalline silicon), and then, as shown in FIG. 1(c), the entire surface is thermally oxidized to form a second layer.
An oxide film 8 (for example, an oxide film with a thickness of 1,000 to 6,000 thick) is formed. Next, as shown in Figure 1(d),
The entire surface is exposed to an anisotropic etching atmosphere and the second oxide JII 8 is left only on the side walls of the groove.This etching is such that the second oxide film 8 is exposed to the second polycrystalline silicon film 5 and the first oxide film 8. It should be made so that it does not remain on the side walls of the nitride film 4.

次に、第1図(e)に示すように、全面に半導体基板1
と同導電型の不純物〈例えばボロン)を含有した埋め込
み用多結晶シリコン層9(例えば化学的気相成長法によ
る膜厚1μ〜3μの多結晶シリコン)を形成し、続いて
、第1図(f)に示すように、埋め込み用多結晶シリコ
ン層9および第2の多結晶シリコン膜5をエッチバック
し、溝内にのみ埋め込み用多結晶シリコン層9を残す。
Next, as shown in FIG. 1(e), a semiconductor substrate 1 is placed over the entire surface.
A buried polycrystalline silicon layer 9 (for example, polycrystalline silicon with a thickness of 1 μm to 3 μm formed by chemical vapor deposition) containing an impurity of the same conductivity type (e.g., boron) as shown in FIG. As shown in f), the buried polycrystalline silicon layer 9 and the second polycrystalline silicon film 5 are etched back, leaving the buried polycrystalline silicon layer 9 only in the trench.

次に、第1図(g)に示すように、窒化膜4をマスクと
して熱酸化を行い、素子分離酸化膜10(例えば膜厚2
000人〜8000人の酸化膜)を形成する。この工程
で発生するストレスは、第1の酸化fi2、第1の多結
晶シリコン膜3および窒化膜4にはかかるが、半導体基
板1にはほとんど影響を与えない、したがって、第1の
多結晶シリコン膜3には歪11が発生するが、半導体基
板1には発生しない、最後に、第1図(h)に示すよう
に、窒化膜4および第1の多結晶シリコン膜3をエツチ
ング除去する。
Next, as shown in FIG. 1(g), thermal oxidation is performed using the nitride film 4 as a mask, and the element isolation oxide film 10 (for example, a film thickness of 2
000 to 8,000 oxide film). The stress generated in this step is applied to the first oxide fi2, the first polycrystalline silicon film 3, and the nitride film 4, but has almost no effect on the semiconductor substrate 1. Strain 11 occurs in film 3, but not in semiconductor substrate 1.Finally, as shown in FIG. 1(h), nitride film 4 and first polycrystalline silicon film 3 are removed by etching.

次に、第2図(a>、(b)を参照して、本発明の他の
実施例について説明する。この実施例では、第2図(a
>に示すように、先の実施例において用いられた第2の
多結晶シリコン膜5が形成されていない、溝を形成した
後、先の実施例と同様の手段を用いて溝内壁にのみ第2
の酸化膜8を形成する。次いで、第2図(b)に示すよ
うに、溝内に選択エピタキシャル法を用いて、基板と同
導電型の単結晶シリコン層9aを成長させる。これ以降
の工程は、先の実施例と同様である。
Next, another embodiment of the present invention will be described with reference to FIGS.
>, after forming a groove in which the second polycrystalline silicon film 5 used in the previous example is not formed, a groove is formed only on the inner wall of the groove using the same means as in the previous example. 2
An oxide film 8 is formed. Next, as shown in FIG. 2(b), a single crystal silicon layer 9a having the same conductivity type as the substrate is grown in the trench by selective epitaxial method. The subsequent steps are the same as in the previous embodiment.

次に、第3図(a)〜(c)を参照して、本発明のさら
に他の実施例について説明する。この実施例でも、先の
実施例と同様に、最初の実施例で用いられた第2の多結
晶シリコン膜5が省略されている。溝を形成した後、第
3図(a)に示すように、気相成長法を用いて、第2の
酸化膜8を形成する4次いで、第3図(b)に示すよう
に、第2の酸化膜8に異方性エツチングを施してこれを
溝内壁部のみに残す。次に、全面にノンドープの埋め込
み用多結晶シリコン層9を形成する。続いて、第3図(
c)に示すように、多結晶シリコン層9をエッチバック
して溝内にのみこれを残す。
Next, still another embodiment of the present invention will be described with reference to FIGS. 3(a) to 3(c). In this embodiment, as in the previous embodiment, the second polycrystalline silicon film 5 used in the first embodiment is omitted. After forming the grooves, as shown in FIG. 3(a), a second oxide film 8 is formed using a vapor phase growth method. The oxide film 8 is anisotropically etched to leave it only on the inner wall of the trench. Next, a non-doped buried polycrystalline silicon layer 9 is formed over the entire surface. Next, Figure 3 (
As shown in c), the polycrystalline silicon layer 9 is etched back leaving it only in the trench.

この場合、多結晶シリコン層9の表面が、窒化膜表面よ
り幾分低くなるようにエッチバックする。
In this case, the surface of the polycrystalline silicon layer 9 is etched back so that it is somewhat lower than the surface of the nitride film.

この後の工程は、他の実施例と同様である。The subsequent steps are the same as in the other examples.

なお、第2の酸化膜8の形成方法は、多結晶シリコン層
の熱酸化あるいは化学的気相成長法などの外に、基板表
面に熱酸化を施すものであってもよい。
The second oxide film 8 may be formed by thermally oxidizing the polycrystalline silicon layer or by chemical vapor deposition, or by thermally oxidizing the substrate surface.

[発明の効果] 以上説明したように、本発明は、溝に埋め込んだシリコ
ン層を熱酸化して素子分離酸化膜を形成するときに、素
子領域の半導体基板上に多結晶シリコン膜および窒化膜
を設けてこれを行い、その後に窒化膜および多結晶シリ
コン膜を除去するものであるので、本発明によれば、溝
に埋め込んだシリコンを熱酸化して素子分離酸化膜を形
成する際に発生するストレスは、素子分離酸化膜の周囲
の窒化膜および多結晶シリコン膜にはかかるが、半導体
基板にはかからないようにすることができる。したがっ
て、歪は多結晶シリコン膜には発生するが、これを半導
体基板側には発生させないようにすることができる。そ
して本発明によれば、素子分離酸化膜の周囲の多結晶シ
リコン膜は後に除去されるので、結局、半導体基板には
歪が残らないようにすることができる。
[Effects of the Invention] As explained above, the present invention provides a method for forming a polycrystalline silicon film and a nitride film on a semiconductor substrate in an element region when thermally oxidizing a silicon layer embedded in a trench to form an element isolation oxide film. This is done by providing a nitride film and then removing the polycrystalline silicon film. Therefore, according to the present invention, the silicon buried in the trench is thermally oxidized to form an element isolation oxide film. This stress is applied to the nitride film and polycrystalline silicon film surrounding the element isolation oxide film, but can be prevented from being applied to the semiconductor substrate. Therefore, although strain occurs in the polycrystalline silicon film, it can be prevented from occurring on the semiconductor substrate side. According to the present invention, the polycrystalline silicon film around the element isolation oxide film is removed later, so that no strain remains in the semiconductor substrate after all.

また、1に埋め込まれたシリコン層は、溝の底面で半導
体基板と接続されるように形成されるので、これを半導
体基板と同電位に固定でき、デバイスの動作を安定化さ
せることができる。
Further, since the silicon layer embedded in 1 is formed so as to be connected to the semiconductor substrate at the bottom of the groove, it can be fixed at the same potential as the semiconductor substrate, and the operation of the device can be stabilized.

1・・・半導体基板、 2・・・第1の酸化膜、3・・
・第1の多結晶シリコン膜、 4・・・窒化膜、5・・
・第2の多結晶シリコン膜、 6・・・フォトレジスト
、 7・・・第3の多結晶シリコン膜、8・・・第2の
酸化膜、 9・・・埋め込み用多結晶シリコン層、 9
a・・・埋め込み用単結晶シリコン層、10・・・素子
分離酸化膜、 11・・・歪。
DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First oxide film, 3...
・First polycrystalline silicon film, 4... Nitride film, 5...
・Second polycrystalline silicon film, 6... Photoresist, 7... Third polycrystalline silicon film, 8... Second oxide film, 9... Polycrystalline silicon layer for embedding, 9
a... Single crystal silicon layer for embedding, 10... Element isolation oxide film, 11... Strain.

Claims (1)

【特許請求の範囲】[Claims] 一導電型半導体基板上に多結晶シリコン膜および窒化膜
を順次形成する工程と、所定の領域の前記窒化膜、前記
多結晶シリコン膜および前記一導電型半導体基板を順次
エッチング除去して溝を形成する工程と、少なくとも溝
内壁部分に酸化膜を形成する工程と、前記酸化膜を異方
性のあるエッチング雰囲気に晒して前記溝の側壁にのみ
前記酸化膜を残す工程と、溝内に埋め込み用シリコン層
を形成する工程と、前記窒化膜をマスクとして前記埋め
込み用シリコン層の露出部を酸化して素子分離酸化膜を
形成する工程と、前記窒化膜および前記多結晶シリコン
膜を順次除去する工程とを具備することを特徴とする半
導体装置の製造方法。
A step of sequentially forming a polycrystalline silicon film and a nitride film on a semiconductor substrate of one conductivity type, and forming a groove by sequentially etching away the nitride film, the polycrystalline silicon film, and the semiconductor substrate of one conductivity type in a predetermined region. a step of forming an oxide film on at least the inner wall portion of the trench; a step of exposing the oxide film to an anisotropic etching atmosphere to leave the oxide film only on the side walls of the trench; a step of forming a silicon layer; a step of oxidizing the exposed portion of the buried silicon layer using the nitride film as a mask to form an element isolation oxide film; and a step of sequentially removing the nitride film and the polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising:
JP2517289A 1989-02-03 1989-02-03 Method for manufacturing semiconductor device Expired - Lifetime JP2876612B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2517289A JP2876612B2 (en) 1989-02-03 1989-02-03 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2517289A JP2876612B2 (en) 1989-02-03 1989-02-03 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02205340A true JPH02205340A (en) 1990-08-15
JP2876612B2 JP2876612B2 (en) 1999-03-31

Family

ID=12158586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2517289A Expired - Lifetime JP2876612B2 (en) 1989-02-03 1989-02-03 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2876612B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020056659A (en) * 2000-12-29 2002-07-10 박종섭 Method for forming element isolating film of semicoductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020056659A (en) * 2000-12-29 2002-07-10 박종섭 Method for forming element isolating film of semicoductor device

Also Published As

Publication number Publication date
JP2876612B2 (en) 1999-03-31

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