JPH02205109A - Scan latch circuit - Google Patents

Abstract

PURPOSE:To prevent waste circuit delay from being generated on an ordinary data path by a scan path by setting a path to scan-in/out by separating from the ordinary path. CONSTITUTION:Ordinary data is inputted to an input terminal D, and is latched at a closed loop formed with a selector 3 and a clock gate 4. Scan data is inputted from a terminal SDin. To latch the value of the terminal SDin at the closed loop, it is necessary to set Sin, C0, and C1 at a low level, a high level, and the low level, respectively. As a result, the value of the SDin is latched at a node 6. The signal level of output F is set at polarity opposite to that applied on the terminal SDin. Therefore, no waste circuit delay is generated on the ordinary path even when an inverter 2 and the selector 3 which form the scan path is added. Thereby, it is possible to perform scan in/out on a part sensitive to the delay time of a critical path, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to testing of integrated circuits such as microprocessors, and particularly relates to a scan latch circuit suitable for scan-in/out to a portion sensitive to delay time. .

[Conventional technology]

Conventional scannable registers include, for example, flip-flops as shown in U.S. Pat. No. 4,669,061.

[Problem that the invention attempts to solve]

In the above-mentioned conventional technology, a selector is provided at the input portion of the latch, and a normal path and a scan path are selected based on a test signal, and even one normal path passes through the selector. Therefore, a time delay occurs due to the selector, making it difficult to apply to areas sensitive to delay time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan latch circuit that does not cause circuit delay due to the scan path of the normal path even if a scan path is provided for the latch.

[Means to solve the problem]

The above objective is achieved by setting the scan-in/out path away from the normal data bus and onto the feedback bus.

[Effect]

The delay time of the normal path of the scan latch is the time from when the input data is determined on the normal path until the output data is determined. On the other hand, since the latch feedback path has a value greater than 0 that does not affect the normal path, by providing a scan-in/out path on the feedback bus, extra circuit delay will be caused by the scan canvas on the normal path. will disappear.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a logic diagram illustrating a scan latch according to the present invention. This circuit consists of a clock gate 1, an inverter 2.
A selector 3, a clock gate 4, and an inverter 5 are interconnected. The input terminal of this circuit is D e S
Dlme S inw Cot Ci, and the output terminal is F.

The input terminal is connected to the input of the clock gate 1. The output of clock gate 1 is connected to node 6. Node 6 is connected to the first input terminal of selector 3 , the output of clock gate 4 and the input of inverter 5 . The output of selector 3 is connected to the input of clock gate 4. Input terminal 5Di- is connected to the fourth input terminal of selector 3.

The input terminal S1+a is connected to the second input p-terminal of the selector 3 and the inverter 2. The output of inverter 2 is connected to the third input terminal of selector 3.

The operation of clock gate 1 will be explained. clock gate 1
The first and second input terminals of
is input. The signal polarities of inputs GO and C1 must be opposite. When the inputs Co and Cx are at high level and low level, respectively, the clock gate 1 is in a cutoff state. In other words, the output of the clock gate is in a high impedance state.

When inputs Co and Cx are at low level and high level, respectively, gate 1 becomes conductive and outputs the inverted value of the input signal. Clock gate 4 also performs the same operation, but Cx and Ca, which are opposite to clock gate 1, are input to the first and second input terminals.

Normal data (not for testing) is input to the input terminal, and is latched into a closed loop formed by the selector 3 and the clock gate 4. In order to latch the value of the input terminal 5t11e Coo into the closed loop described above, first
High level for each C1.

The low level must be set to the high level. At this time, the clock gate 1 becomes conductive, the output of the selector 3 becomes the inverted output of the clock gate 1, that is, the value of the input terminal, and the clock gate 4 becomes cut-off. As a result, node 6 has the inverted polarity of the input.

Next, while keeping the 5fill input at high 4 level,
o.

Set the CL input to high level and low level, respectively. At this time, clock gate 1 is in a cut-off state, the output of selector 3 is an inverted output of node 6, and clock gate 4 is in a conductive state. As a result, node 6 holds the inverted value applied to the input terminal. Pass the inverter 5 through the output terminal F.

The inverted value of node 6, ie, the value added to the terminal, is output.

Scan data is input from SD.

To latch the value of SDl,1 into the closed loop.

Inputs 5insco and Ct must be set to low level, high level, and low level, respectively.At this time, selector 3 outputs the inverted value of 5Dill, clock gate 4 is in a conductive state, and clock gate 1 is in a cutoff state. . As a result, node 6 has SDi. The value of is latched. The signal level of the output F has the opposite polarity to that added to S D *n.

In FIG. 1, the normal bus includes input terminal D, clock gate 1, node 6, inverter 5, and output terminal F.

In a latch that is not a scan latch, node 6 and clock gate 4 are connected by an inverter that receives node 6 as an input. Therefore, even if the inverter 2 and selector 3 forming the scan path are added, no extra circuit delay will occur in the normal path.

FIG. 2 is a diagram showing another embodiment of the present invention. The difference from FIG. 1 is that a tri-state buffer 7 is added to the output of the selector 3.

When scanning out latched data, S
When out is set to high level, selector 3 is set to 5Dout.
The output value of is output. When 5out is low level,
5Dout is in a high impedance state. Therefore, there is also a method of connecting 5Dout to a common path for a plurality of scan latch circuits, and setting only the 5out input of one scan latch circuit to a high level.

Also in FIG. 2, the normal bus includes input terminal D, clock gate 1, node 6, inverter 5, and output terminal F. By adding tri-state buffer 7,
There is usually no extra circuit delay on the bus.

FIG. 3 is a diagram showing another embodiment according to the present invention.

The difference from FIG. 1 is that a signal from the reset input terminal R is added to the selector 3.

When a high level is applied to the reset terminal R, the output of the selector 3 becomes a low level, and when Co and C are at a high level and a low level, respectively, the node 6 maintains a high level. When resetting the chip, typically GO, C1
are set to high level and low level, respectively.

Also in FIG. 3, the normal bus includes input terminal D, clock gate 1. These are the node 6, the inverter 5, and the output terminal F. Adding the reset signal R normally does not introduce any extra circuit delay on the bus.

〔Effect of the invention〕

According to the present invention, adding a scan-in/out circuit to a latch does not normally cause extra circuit delay on the bus. This makes it possible to scan in and out of areas that are sensitive to delay time, such as critical paths.
It becomes easier to design test circuits and create test methods.

[Brief explanation of the drawing]

1, 2, and 3 are circuit diagrams of embodiments of the present invention, respectively. 1.4... Clock gate, 2, 5... Inverter, 3... Selector, 6... Node, 7... Tri-state buffer. 112th] 2nd close

Claims (1)

[Claims] 1. A circuit for latching data, which connects a data input signal D to a first clock gate, and connects the first clock gate to a first input of a selector and a second clock gate. output and a first inverter, a scan data input to a fourth input of said selector, and an input C_0 to a first input of said first clock gate and a second input of said second clock gate. , an input C_1 is connected to a second input of said first clock gate and a first input of said second clock gate, and an input S_i_n is connected to a second input of said selector and a second input of said selector. the output of the second inverter is connected to the input of the second clock gate, the output of the second inverter is connected to the third input of the selector, the output of the selector is connected to the input of the second clock gate;
The selector is a circuit in which the clock gate is in a cutoff state when its first and second inputs are at a high level and a low level, respectively, and is in a conductive state when the polarity is reversed. and a scan latch circuit comprising a section that generates an AND of the second input, a section that generates an AND of the third and fourth inputs, and a section that generates a NOR of the two ANDs. 2. The scan latch circuit according to claim 1, further comprising a tri-state buffer added to the output of the selector. 3. The scan latch circuit according to claim 1, wherein a reset signal is added to the input of the selector.