JPS61128622A - Logical circuit constituting system - Google Patents

Abstract

PURPOSE:To decrease the components of a logical circuit without losing automatic generation functions of a CAD by using a conventional latch at a part of latches in an LSSD system logical circuit and supplying an AND gate clock to the said latch. CONSTITUTION:A shift-in input is fed sequentially to a terminal SIN and shift-in is executed by applying a shift clock SCK thereto (a). Then a test pattern is fed to input terminals A, B, D (b). A system clock C2 is applied. Then a value of the input of the conventional latch 4 is given to an output (c). A system clock C1 is applied and then a new value is set to an SRL3 (d). A value at an output terminal OUT is checked (e). The shift clock SCK is applied again, the content of the SRL3 is shifted out of an SOUT terminal and the pattern is checked (f). The module is tested by repeating the steps (a)-(f) above.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention belongs to the field of dealing with logic circuits such as electronic computers, and in particular, it belongs to the field of dealing with logic circuits such as electronic computers.
The present invention relates to a logic circuit configuration method called a si-tive 3can design method.

[Conventional technology]

As a conventional LSSD logic circuit, for example, r 1
4th Design Automation (:
:onference Proceedings J
(pages 462-468). FIG. 5 is a block diagram showing a conventional LSSD type logic circuit. In the figure, 1 is an LSI (Large 5cale Int
2 is the output terminal of the same module, and 3 is the S
RL (5hift Register Latch), 5 is an AND gate, and 6 is a buffer gate.

Next, the operation of the conventional logic circuit shown in FIG. 5 will be explained. 5RL3 functions like a normal latch during normal operation. That is, when the clock input terminal C of 5RL3 is "1" (enabled state), the value of the input terminal DI is transmitted as is to the output terminal 0, and the clock input terminal C is set to "O" (disabled state). Then, the blade terminal 0 continues to hold the value at that time. 5R
L3 has a shift function in addition to the above functions.

That is, 5RL3 has a shift-in input terminal SI, a shift-out output terminal SO, a shift clock input terminal SC, etc. in addition to the input/output terminals described above.

FIG. 5 shows a module such as an LSI, in which all 5RL3 are connected as one shift ring.

That is, the shift-out output terminal SO of one 5RL(1)3 is connected to the shift-in input terminal SI of the next SRL(2)3. When the shift clock that is commonly input to all 5RL3s enters the shift clock input terminal 5CKI times of each 5RL3, each 5RL3 is
The value of RL3 is newly set. That is, the SRL ring as a whole functions as a shift register. When testing a module, an appropriate pattern is sequentially applied from the tester to the shift-in terminal SIN of the module, and a shift clock is applied to perform a shift-in operation. That is, any value can be set for all 5RL3 from the tester. Similarly, all values of 5RL3 can be known by shifting and observing the shift out terminal 5OUT of the module. The test for one test pattern is performed as follows.

The tester sets the pseudo input pattern on the SRL ring by the shift-in operation. A test pattern is set on each input terminal A, B, and D of the module, and applied to each system clock C2, C1t-sequentially. For this,
All 5RL3s are populated with new values. After inspecting the pattern of the output terminal OUT of the module, the tester shifts out, takes out the pseudo quantity cover turn set on the SRL ring, and inspects it. In this way, 5
By making RL3 a pseudo input/output terminal, the rest of the logic circuit becomes a combinational circuit (a circuit composed only of gates).
ed Desi-gn-Computer-aided Design) Automatic generation of test patterns using K becomes possible. By the way, with recent advances in semiconductor technology, the degree of integration of LSIs has increased rapidly, and it has become extremely difficult to create test patterns manually in terms of both cost and quality. It is becoming very important to automatically generate patterns using the CAD.

[Problem that the invention seeks to solve]

The conventional logic circuit as described above is configured using FRL3t- for all latches in the logic circuit.

However, this 5RL3 is about 3 times smaller than a normal latch.
It has about twice the circuit scale (transistors, etc.).

Therefore, in the conventional logic circuit configuration method, an increase in the circuit scale due to the 5RL3 has been a very serious problem.

This invention was made to solve these problems, and aims to provide a logic circuit configuration method that minimizes the increase in the scale of one circuit and allows automatic generation of test patterns using CAD. .

[Means for solving problems]

In the logic circuit configuration method according to the present invention, only some of the latches in a logic circuit composed of gates and latches are used as shift register latches, and the other latches are configured using ordinary latches. An ungate clock is supplied to the normal latch.

[Effect]

In the logic circuit configuration method of the present invention, instead of using all the latches in the logic circuit composed of gates and latches as shift register latches, some of the latches are used as normal latches. 9. For this, by applying a clock arbitrarily from the system clock input terminal of the module, that is, by supplying an ungated clock. Logic circuit components (transistors, etc.) can be significantly reduced without compromising the ability of CAD to automatically generate tests for this logic circuit.

〔Example〕

FIG. 1 is a block diagram showing a logic circuit configuration system according to an embodiment of the present invention. Normally, this is applied to a larger module such as an LSI, but a small logic circuit is shown here to simplify the explanation. In the figure, 1 is the input terminal of the module, 2 is the output terminal of the module, 3 is 5RL (shift register latch),
4 is a normal latch (L), 5 is an AND gate, and 6 is a pamphlet gate. In FIG. 1, the system clock C1 entering 5RL3 is gated by the clock stop signal, but the system clock C2 entering the normal latch 4 is not gated and is supplied to the normal latch 4 ( Be careful of the ungated clock).

FIG. 2 is a diagram showing a time chart when testing the logic circuit of FIG. 1. In Figure 2, the first
A time chart of a signal (one test pattern) applied by the tester to the module when testing the module shown in the figure is shown. This consists of the following steps:

(a) Shift-in inputs are sequentially applied to the shift-in terminal SIN to perform shift-in with shift clock 5CKt. In the example shown in Fig. 2, 5RL(1)3°5RL(
2) The values of rlJ, rO, and J are set in 3 (pseudo input).

(b1 Next, apply a test pattern to each normal input terminal A, B, D.

(c) System clock C2t- is applied. As a result, the value on the input side of the normal latch 4 is transmitted to the output side.

(d) Apply system clock C1t. As a result, a new value is set in 5RL3.

(6) Check the value of the output terminal OUT (output pattern).

(f) In addition to the shift clock 5CKt-, the contents of 5RL3 are shifted out from the 5OUT terminal and this pattern is inspected (pseudo output). The above (a) to (f) are operations for one test pattern, but by repeating all of these operations several times (several tens to hundreds of times in a normal LSI), the module A test will be conducted.

3 and 4 are diagrams for explaining the operation of the latch in the logic circuit of FIG. 1, respectively. In each of the above figures, 7 is an OR gate.

As shown in FIG. 3, the input terminals AE are set to input terminals AE, and the system clock C1t- is applied. As a result, the value of the input terminal D■ of the normal latch 4 is transmitted to the output terminal OK, and the output terminal OUT is set. The one shown in Figure 4 is the third
It is the same as shown in the figure. In the case shown in FIG. 4, if the same input cover turns as above are applied to each input terminal A-E, the same output values as above appear after the gate delay time. In other words, the circuit shown in FIG. 3 and the circuit shown in FIG. 4 are the same, except that when viewed from the tester, a clock must be input once per period. This does not hold true if the output of the latch passes through a certain bus and is input to this latch again.
That is, this is the case where there is a loop. However, in the case of a logic circuit composed of latches rather than clip-flops, at least one
A separate launch or SRL is required. If you set it to 5RL3 instead of the usual latch 4.

That becomes a pseudo input/output terminal and the loop is broken.

By doing this, for all lunches,
Furthermore, the relationship between the circuit shown in FIG. 4 and the circuit shown in FIG. 4 can be made to hold.

One thing to note here is that since tS is isometrically changed from the circuit shown in FIG. 3 to the circuit shown in FIG. 4, it is necessary for K to input a clock to the latch. Therefore, the clock that enters the latch is connected directly from the input terminal l of the module (connects an ungated clock that is not switched by the crop stop signal) so that the tester can also be provided with an arbitrary clock. By configuring the logic circuit as described above, from the viewpoint of test pattern generation, the normal latch 4 is equivalently converted from the circuit shown in FIG. 3 to the circuit shown in FIG. 4 (as in the circuit shown in Figure 4, there is no ordinary latch 4). The conventional CAD program can be used as is by simply adding a function to search for a latch on one circuit and delete (short) it.

As mentioned above, in place of the SR130 shown in FIG. 1, a part of the logic circuit using a normal latch 4T,
It is clear that it can be tested in the same manner as the conventional logic circuit shown in the figure. Therefore, the test input cover pattern can be automatically generated using CAD.

〔Effect of the invention〕

As explained above, in a logic circuit configuration method, the present invention uses ordinary latches for some of the latches in a logic circuit composed of gates and latches instead of using shift register latches, By supplying an ungate clock to this normal latch, we have the excellent effect of significantly reducing the number of logic circuit components without impairing the automatic test generation function for this logic circuit using CAD. It is something to play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a logic circuit configuration method according to an embodiment of the present invention, FIG. 2 is a diagram showing a time chart when testing the logic circuit of FIG. 1, and FIGS. 3 and 4. 1 and 5 are diagrams for explaining the operation of the latch in the logic circuit of FIG. 1, respectively, and FIG. 5 is a configuration diagram showing a conventional LS SD type logic circuit. In figure D, 1... module input terminal, 2...
Output terminals of the module, 3...5RL (shift register latch), 4... normal latch, 5... AND gate, 6... buffer gate, 7... OR gate. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a logic circuit that is composed of a gate and a latch, and uses a shift register latch for the latch part, only some of the latches in this logic circuit are used as the shift register latches, and other latches are used as normal latches. A logic circuit configuration method characterized by supplying an ungate clock to this ordinary latch.