JPH02202714A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To obtain a stable output signal with use of a simple circuit by taking the signals with phases adverse to each other out of the input and output terminals of a gate to which a crystal oscillator is connected and adding both signals together and dividing them after applying the level control to these signals and transmitting them through another gate circuit. CONSTITUTION:A crystal oscillator 2 and a high resistance 3 are connected to both ends of the input/output terminals A and B of an inverter 1 together with the capacities 4 and 5 for generation of oscillations. The DC components are deleted by both capacities 6 and 9, and the signals of both terminals B and A are inputted to the inverters 12 and 13. The output signals C and D are added together via a NAND gate 14 for acquisition of a pulse having a frequency double as high as the desired one. This pulse signal is divided down to 1/2 by a frequency divider 15. Thus a pulse of a desired frequency is outputted through an output terminal 16.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a clock pulse generation circuit in a digital circuit.

(Prior art) In order to generate a stable lock pulse in a digital circuit, a crystal oscillator is usually used to connect both ends of the input and output of a gate circuit, and from each of the input terminal and output terminal of the gate. When the capacitor is connected to ground, K creates a crystal clock oscillator. By taking out this output from the gate of the next stage, a stable lock pulse can be obtained.

However, since the signal level of the sine wave waveform oscillated by the first-stage gate does not necessarily match the threshold value of the next-stage gate, the output pulse waveform of the next-stage gate tends to have a duty factor that deviates from the 50 factor. Ta.

When the density factor of a clock pulse deviates from 50%, in digital circuits that often use inverted clock signals as well as non-inverted clock signals, especially in microcomputers, the processing time until the next clock pulse arrives will decrease. Two methods have been known as techniques for narrowing the spacing and deteriorating the operating margin. One method is to generate a DC component corresponding to the deviation in the deviation detection circuit (integrator in A-body) when the duty factor deviates from 50%, and then feed back this DC signal. In this method, the threshold value of the gate of the oscillator is controlled and negative feedback control is performed so that the duty factor becomes 50%, that is, the DC component of the shift detection circuit becomes zero. The disadvantage of this method is that
It is necessary to adjust the setting of the control operating point, and furthermore, the operating point is likely to fluctuate due to temperature disturbances, etc.

Another method is a PLL system as shown in FIG. This is a vCO that oscillates at twice the desired frequency fo.
By dividing the output by 72 in the next stage, the duty
A pulse with a factor of exactly 50% is obtained and output from the gate. A part of the output of the splitter enters the phase comparator, where it compares the phase with the output wave of the highly stable crystal oscillator oscillating at fo, and the phase error component is fed back to the VCO through the next stage loop filter. The VCO is phase-logged to the crystal oscillator, and a stable pulse oscillation output can be obtained. Although this method is expected to work well in the normal environment of electronic equipment, various drawbacks arise when it is installed in an on-vehicle electronic circuit. For example, ignition noise may jump into the PLL band and modulate the frequency of the VCO, and the VCO's oscillator itself may be subject to vibrations while the car is running, resulting in impulse noise, and in severe cases, the PLL may
This has drawbacks such as the risk that the loop may become out of synchronization.

[Structure of the invention]

(Means and Effects for Solving the Problems) In order to prevent the clock generation circuit of the in-vehicle electronic circuit from being affected by frequency modulation caused by ignition noise and vibration during driving, the present invention uses crystal vibration. Take out the mutually opposite phase signals of the input and output terminals of the gate to which the child is connected, adjust both signal levels appropriately, pass them through another gate circuit, and add them to double the desired frequency. This is a clock generation circuit that obtains the frequency of V2 and divides the signal into V2 to make the data factor 50%.

(Example) FIG. 1 is a diagram showing an embodiment of the present invention.

The inverter 1 is made of, for example, a CMO8 device. A NOR gate circuit can also be used as a substitute as long as it has a gate that can handle the inversion effect. A crystal resonator 2 and a high resistance 3 for bias supply are connected in parallel to both ends of input/output terminals A and B of this inverter 10. The high resistance 3 can also be made with a transmic gate of MOS-IC. By connecting capacitors 4 and 5 to both terminals, this circuit starts oscillating with a sinusoidal waveform. The waveforms of the A and B terminals at this time are shown in Figure 2 (a) and (b).
The oscillation and phase are each oscillating in opposite phases.

Next, after the DC component is removed by the capacitors 6 and 9, the signals at the B terminal and the input terminal are input to the inverters 12 and 13. The voltage in this situation is illustrated in Figure 2 (
d) and (C). Here, inductor 8 and inductor 11 are used to bring the DC level of inverters 12 and 13 to zero. The resistor 7 and the resistor 10 are used for damping (preventing oscillation) the inductor 8 and the inductor 11.

Assuming that inverters 13 and 12 have the levels shown by the broken lines in Figure 2 (C) and (d) as their threshold values, their outputs will have waveforms as shown in Figure 2 (e) and (d). Become. When these pulse waveforms are added by the Nandt gate 14, a pulse having a speed twice the desired frequency is obtained as shown in FIG. 2(f). If this pulse waveform with twice the frequency speed is divided by a flip-flop, which is a 1/2 divider 15, a pulse with a duty conflict factor of 50% at the desired frequency is obtained as shown in Fig. 2 (h). The signal is obtained from the output terminal 16 of the branching unit.

Next, another embodiment is shown in FIG.

Capacity 17. The sum of capacitors 18 and 18 is the same value as capacitor 4 in FIG.
Settings are made so that a pulse with a predetermined pulse width can be obtained from the output of the inverter 13. The sum of capacitance 19 and capacitance 20 is also selected to have the same value as capacitance 5. 22 to 25 are high-resistance transmission gates or high-resistance transmission gates when manufactured with MOS/IC. ・VDD voltage is applied to the voltage between the positive power supply VDD terminal 21 and the ground using the high resistance 22 and the high resistor. Split,
Similarly, the power supply VDD is divided by high resistance A and high resistance 5, respectively. Although not shown, an AC sine wave is input superimposed on the divided bias voltage of VDD to obtain output pulses from the inverters 12 and 13. Thereafter, the addition and division of pulses into two stations is the same as that shown in FIG.

Furthermore, although not shown, the part of the excavator on the left side of the broken line in FIG. 3 may be connected to the right side of the broken line in FIG. 1 as a combination.

FIG. 4 shows yet another embodiment. The sinusoidal voltage at both terminals A and B of the crystal oscillator is adjusted to match the threshold values of inverters 13 and 12 with high resistances U and 5 and high resistance 22.2.
3 and input into inverters 13 and 12. Thereafter, the output pulses of the inverters 13 and 12 have waveforms as shown in FIGS. It is obtained from the output terminal 16.

FIG. 5 shows another embodiment in which the portion of the crystal oscillator on the left side of the broken line in FIG. 4 is removed. Terminal A, which is oscillating a sine wave with a large amplitude like a crystal oscillator on the left side of the broken line in Figure 4,
The B signal is directly input to inverter 13.12 in FIG. The output pulse is added up to t, and since the input sine wave signal is large, the pulse width is widened, so
Since the output will be zero (connect the mono multivibrators n and 26 to the outputs of inverters 13 and 12, respectively,
Mono-multi pie break to achieve the prescribed pulse width.

Select a time constant of 26 and set it so that the inverted output (Q) becomes (e) and (f) in Fig. 2. After that, in the same way, both output pulses are added by the Nant gate 14 and I
The frequency is divided by the divider 15 of A, and the duty signal is set at the desired frequency.
Pulses with a factor of 50% can be obtained.

FIG. 6 shows another embodiment of only the crystal oscillator portion described above. In an oscillator that operates with a large amplitude, the waveform is distorted by non-linear distortion, and when it is shaped into a pulse, the relative position at the time of addition becomes deviated, causing an error in the 50% duty factor. Therefore, by inserting resistor 4 in series in the tank circuit, the oscillation force can be suppressed and linearity can be improved.

〔Effect of the invention〕

The conventional example is a feedback loop system, which requires initial settings, and if a disturbance enters the loop band, it spreads throughout the system, but in the present invention, the signal flow is unidirectional, and the disturbance is The system as a whole is not disturbed by this, a stable output signal can be obtained with a simple circuit, and it has the advantage of being highly reliable as a clock signal supplied to in-vehicle electronic equipment.

[Brief explanation of the drawing]

1g1 is an embodiment of the present invention, FIG. 2 is a diagram showing a timing chart of an actual embodiment of the present invention, FIGS. 3 to N6 are diagrams showing other embodiments of the present invention, and FIG. It is a figure showing a conventional example. 1.12.13...Inverter, 2...Crystal resonator, 3...High resistance, 4,5.17.1g, 19.20
...Capacitance for oscillation, 7.10.28...Resistance for damping. 8.11...Inductor 15...V2 frequency divider, 22, 23.24.25...High resistance, 26.27...
・Mono multi vibrator. 14... Nantes gate, 16... Output terminal, representative patent attorney Kensuke Matsuyama Mitsuyuki Matsuyama

Claims (3)

[Claims] (1) An oscillation unit in which a crystal resonator and a high resistance are connected in parallel between the input and output terminals of an inverter, and the input and output terminals are grounded via a capacitor, and the outputs of the input and output terminals are added together via the inverter. and the added output is frequency-divided. (2) The clock generation circuit according to claim 1, wherein the oscillator has a damping resistor inserted therein. (3) The clock generation circuit according to claim 1, wherein both capacitances connected to the inverter input and output terminals are divided and the inductor is connected to ground.